Abstract: A flash memory storage system including a flash memory chip, a connector, and a flash memory controller is provided. The flash memory controller configures a plurality of logical addresses and maps the logical addresses to a part of the physical addresses in the flash memory chip, and a host system uses a file system to access the logical addresses. Besides, the flash memory controller identifies a deleted logical address among the logical addresses and marks data in the physical address mapped to the deleted logical address as invalid data.

Abstract: In one embodiment, in response to receiving a topology change notification at a network bridge having ports identified as either a network port or an edge port, address learning may be disabled on the network bridge. Once address learning is disabled, an association of all entries of a forwarding table of the network bridge having addresses previously forwarded on a particular network port of the network bridge may be changed to forward those addresses on all network ports of the network bridge (e.g., flooding the frames not addressed to edge ports on all network ports only). Subsequently, address learning may be enabled on the network bridge, thus repopulating the network port entries of the forwarding table in response to the topology change.

Abstract: Assuring recovery from failure of a storage server in a distributed column chunk data store of operably coupled storage servers, includes: partitioning a data table into chunks; implementing a distribution scheme with a specified level of redundancy for recovery of one or more failed servers among multiple storage servers; distributing the column chunks according to the distribution scheme; calculating column chunk parity; storing the calculated column chunk parity; managing metadata for the column chunk data store; and updating the metadata for distributing the column chunks among remaining storage servers upon receiving an indication to remove a storage serve.

Abstract: Methods, systems, and computer program products for controlling information read/write processing. The method includes assigning a plurality of division areas to a shared storage area for storing a shared object: specifying a division area used for read/write processing in accordance with user identification information for identifying a user; and executing the read processing for reading information from a specified division area and the write processing for writing information to the specified division area. The shared object is shared among a plurality of processes.

Abstract: Machine-readable media, methods, apparatus and system for managing sectors of a non-volatile memory are described. In some embodiments, a plurality of file segments may be written to a plurality of memory sectors (501), each memory sector of the plurality of memory sectors for each file segment of the plurality of file segments. Then, a plurality of flags may be searched from a first section of a sector table (502), each flag of the plurality of flags corresponding to the each file segment. A section may be selected from a second section and a third section of the sector table, wherein the section may be indicated by the plurality of flags (505,507). A plurality of physical addresses for the plurality of memory sectors may be written to the section (506,508).

Abstract: In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to identify a prefetch stream in cache misses from the data cache, and the prefetch unit is configured to issue prefetches predicted by the prefetch stream to prefetch data into the data cache. More particularly, the prefetch unit implements one or more stream engines that generate prefetches for respective prefetch streams. Each stream engine is configured to maintain limit data that indicates a number of prefetches that are permitted to be outstanding beyond a most recent demand access. The stream engine is configured to increase the limit responsive to the number of demand accesses that consume prefetched data at least equaling the limit.

Abstract: A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random access memories (RAMs), multiplexers, and pointers that allow static or dynamic bandwidth configuration as function of instruments examining the system traffic using queues. The interface allows many initiators having many logical threads to share and use many physical threads in different queue modules.

Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.

Abstract: Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.

Abstract: A system may comprise one or more source agents, target agents, and a plurality of directory agents, which may determine the target agent to which one or more transactions generated by the source agents is to be sent. A controller may identify one of a plurality of directory agents to process the transactions. The directory agent may determine the control and status registers of the target agents to which the transaction is to be sent. The target agent may complete the transaction after receiving the transaction from the directory agent. The directory agents may store a memory map to resolve the target agent to which the transactions is to be sent. The directory based distributed CSR access may provide scalability to ever increasing number of heterogeneous agents in the system.

Abstract: Embodiments of systems and methods for a storage system are disclosed. More particularly, in certain embodiments desired locations of storage devices may be zeroed out during operation of the storage system and areas that have been zeroed out allocated to store data when commands pertaining to that data are received. Specifically, in one embodiment a distributed RAID system comprising a set of data banks may be provided where each data bank in the set of data banks may execute a background process which zeroes areas of the storage devices of the data bank. When a command pertaining to a logical location is received a zeroed area of the physical storage devices on the data bank may be allocated to store data associated with that logical location.

Abstract: A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first TLB, the physical address is requested from a set of page tables. When the data processing device is in a hypervisor mode, a second TLB is accessed in response to the request to access the page tables. If the virtual address is located in the second TLB, the hypervisor page tables are bypassed and the second TLB provides a physical address or information to access another table in the set of page tables. By bypassing the hypervisor page tables, the time to translate an address in the hypervisor mode is reduced, thereby improving the efficiency of the data processing device.

Abstract: An event tracking hardware engine having N (?2) caches is invoked when an event of interest occurs, using a corresponding key. The event tracking engine stores a cumulative number of occurrences for each one of the different kinds of events, and searches in the N caches for an entry for the key. When an entry for the key is found, the engine increments the number of occurrences if no overflow of the cumulative number of occurrences would occur. However, if the incrementing would cause overflow, then instead of incrementing the cumulative number of occurrences, the engine promotes the entry for the event of interest to a next higher cache.

Abstract: Systems, methods and media for selectively closing pages in a memory in anticipation of a context switch are disclosed. In one embodiment, a table is provided to keep track of open pages for different processes. The table comprises rows corresponding to banks of memory and columns corresponding to cores of a multi-core processing system. When a context switch signal is received, the system unsets a bit in a column corresponding to the core from which the process is to be context-switched out. If no other process is using a page opened by the process the page is closed.

Abstract: A method for classifying a data packet containing a header is provided. The method may comprise parsing the header of a data packet into header elements. Rules in secondary lookup tables generated from a primary lookup table may be accessed. The respective header elements of the data packet may be compared to the respective fields of each of the secondary lookup tables, and rule results for each of the secondary lookup tables in a combinable format may be generated. In another embodiment, a method for generating secondary lookup tables from a primary lookup table is provided. The method may comprise accessing a primary lookup table defining packet classification rules and generating multiple secondary lookup tables from the primary lookup table. For each secondary lookup table, a selection of classification rules and a selection of fields of the multiple fields based on a rule set identifying predefined entries may be extracted.

Abstract: In an embodiment, a processor includes a data cache and a prefetch unit coupled to the data cache. The prefetch unit is configured to detect one or more prefetch streams corresponding to load operations that miss the data cache, and includes a memory configured to store data corresponding to potential prefetch streams. The prefetch unit is configured to confirm a prefetch stream in response to N or more demand accesses to addresses in the prefetch stream, where N is a positive integer greater than one and is dependent on a prefetch pattern being detected. The prefetch unit comprises a plurality of stream engines, each stream engine configured to generate prefetches for a different prefetch stream assigned to that stream engine. The prefetch unit is configured to assign the confirmed prefetch stream to one of the plurality of stream engines.

Abstract: A method of transmitting data between processors, including: establishing and storing an encoding method for each area of virtual address space of a first processor in a predetermined storage device; determining an area of virtual address space corresponding to data to be transmitted to a second processor; and determining the encoding method corresponding to the determined area of the virtual address space with reference to the storage device and transmitting the data to the second processor by using the determined encoding method.

Abstract: Technologies for high capacity storage servers with thin provisioning can support an increased storage capacity and an increased number of snapshots within a data storage system while maintaining a reduced memory footprint. Flexible virtual address translation can support both direct, and indirect, translation from a virtual address to an address in physical storage. A data structure, referred to as a volume table, may be provided for supporting the virtual to physical address translation. Multiple volume tables for the various volumes within a data storage system can be stored together in a global volume table. Granularities of storage allocation units, such as territories, provisions, and chunks can be reduced to improve efficiencies in the operation of the storage system. Processes for handling volume and snapshot I/O operations with various data structures can contribute to improved efficiencies while supporting increased storage capacities and an increased number of snapshots.

Abstract: A “LUN Table” enables Logical Unit Number (LUN) mapping/masking within an Input/Output Virtualization IOV adapter included in a Serial Attached Small Computer System Interface (“SAS” or “Serial Attached SCSI”). A plurality of System Images (“SI”) share block storage through the SAS. The IOV adapter includes one or more Virtual Functions (VF), a Physical Function (PF), and a LUN Table within the PF. The VF allows each SI to communicate I/0 requests with a storage device through the PF. The LUN Table maps the I/0 requests to unique locations within the storage device. Each SI is isolated from all other SIs. Interference between each SI is avoided. A VIOS or a LUN mapping/masking SAN are not required. I/0 latency, processor overhead and storage cost are improved over prior LUN mapping/masking solutions.

Abstract: The updating of only some memory locations in a multiple computer environment in which at least one applications program (50) executes simultaneously on a plurality of computers M1, M2 . . . Mn each of which has a local memory, is disclosed. Memory locations (A, B, D, E, X) in said local memory are categorized into two groups. The first group of memory locations (X1, X2, . . . Xn, A1, A2 . . . An) are each accessible by other computers. The second group of memory locations (B, E) are each accessible only by the computer having the local memory including the memory location. Changes to the values of memory locations in the first group only are transmitted to all other computers. A promotion mechanism is disclosed to promote memory locations in the second group into the first group in the event that application program execution means that a memory location in said second group is referred to by a memory location in the first group (ie the first group location now points to the second group location).

Abstract: A comparand word is input to a plurality of hash circuits, with each hash circuit responding to a different portion of the comparand word. The hash circuits output a hash signal which enables or precharges portions of a content addressable memory CAM. The comparand word is also input to the CAM. The CAM compares the comparand word in the precharged portions of the CAM and outputs information responsive to the comparison. When Internet addresses are processed, the output information is either port information or an index for locating port information.

Abstract: Methods for modifying a switching table of an Internet Protocol (IP) switch. The methods include: receiving a dynamic host configuration protocol (DHCP) option 43 request from a host of a LAN at an access port of the IP switch; transmitting the request to a DHCP server; intercepting a DHCP response for the request from the DHCP server; extracting an IP address from the intercepted DHCP response; and adding the extracted IP address to a corresponding entry (specific to the access port) of a switching table of the IP switch. The methods include: receiving an IP frame at an access port of the IP switch; reading an IP source address from the IP frame; and in the switching table either: creating a new entry including the IP source address and its associated port identifier or changing an existing entry based on the IP source address and the access port.

Abstract: Communication with adapters of a computing environment is facilitated. Instructions are provided that explicitly target the adapters. Information provided in an instruction is used to steer the instruction to an appropriate location within the adapter.

Abstract: A host computer includes a virtual disk control part for controlling an input/output request into a virtual disk. A plurality of storage subsystems includes a load monitoring part for measuring a load on a physical disk by the input/output request and storing load information in a disk management table. The virtual disk control part identifies, upon receiving the input/output request into a not-ever-outputted space in a virtual disk, an appropriate logical disk on the virtual disk based on the load information in the disk management table, sends the input/output request to the storage subsystem having the identified logical disk, and updates, upon receiving a completion acknowledgement of the input/output request, the load information in the disk management table based on the load information in the logical disk map information table.

Abstract: In a data transmission apparatus, provisions are made to be able to trace the result of processing or discarding of a specific packet from outside the apparatus. More specifically, in a data transmission apparatus that receives data having a header and, based on information carried in the header, performs processing such as destination determination, discard processing, and priority transmission processing on the received data by using a plurality of processing blocks, a memory for storing the processing results supplied from the respective processing blocks in the data transmission apparatus is provided, wherein a flag is appended only to the data that needs tracing and only the processing result of the thus flagged data is stored in the memory, and wherein, after completing the processing, only the processing result of the flagged data is forcefully output outside the apparatus thus enabling the processing result to be retrieved.

Abstract: A method for partitioning during an online node add. The method includes providing a data storage cluster with first and second nodes, and storing a table of data in the data storage cluster with a first partition storing a set of rows or data elements in the first node and a second partition storing a set of rows or data elements in the second node. The method includes adding a third node to the cluster and adding a third partition to the table using a partitioning mechanism to create a distribution mapping for data elements in the first, second, and third partitions. The distribution mapping provides substantially uniform distribution of the data elements over the first, second, and third partitions by the partitioning mechanism using modulo hash partitioning as a function of data elements or by combining hash and list partitioning such that data is retained on the original partitions.

Abstract: A system, method and computer program product for resizing a hash table while supporting hash table scalability and concurrency. The hash table has one or more hash buckets each containing one or more items that are chained together in a linked list. Each item in the hash table is processed to determine if the item requires relocation from a first bucket associated with a first table size to second bucket associated with a second table size. If the item requires relocation, it is linked to the second bucket without moving or copying the item in memory. The item is unlinked from the first bucket after waiting until there is no current hash table reader whose search of the hash table could be affected by the unlinking, again without moving or copying the item in memory.

Abstract: An indication of a host route to be added to a forwarding database table as an entry is received. The host route is added to a first hardware table or a second hardware table if a space is available in the second hardware table or in a first storage area of the first hardware table. The first hardware table has both a first storage area and a second storage area. If a space is not available in the second hardware table or the first storage area of the first hardware table, the first storage area of the first hardware table is automatically expanded to include unused space in the second storage area of the first hardware table. The host route is then added to a space in the expanded first storage area of the first hardware table.

Abstract: An improved system and method for removing a storage server in a distributed column chunk data store is provided. A distributed column chunk data store may be provided by multiple storage servers operably coupled to a network. A storage server provided may include a database engine for partitioning a data table into the column chunks for distributing across multiple storage servers, a storage shared memory for storing the column chunks during processing of semantic operations performed on the column chunks, and a storage services manager for striping column chunks of a partitioned data table across multiple storage servers. Any data table may be flexibly partitioned into column chunks using one or more columns with various partitioning methods. Storage servers may then be removed and column chunks may be redistributed among the remaining storage servers in the column chunk data store.

Abstract: Data tables that are required for the proper processing of font glyphs are automatically synthesized if they do not form part of an original font definition. The synthesized tables are stored in an annex file that is associated with the font, rather than being incorporated into the font definition. As a result, the integrity of the original font data is maintained, and does not adversely affect font protection systems that are based upon font data.

Abstract: A method for designing a read-only memory (ROM), and related device, includes partitioning a dataset into two or more sub-datasets that each have the same address space, but are of a smaller bit-width than the original dataset. The sub-datasets are row collapsed, and then respective memory cells for the sub-datasets are provided. The output of the memory cells provides the output of the ROM. Each memory cell includes a decoder that maps addresses to word lines based on mapping information obtained during row collapsing, and a logic array driven by the decoder that encodes the data words of the sub-dataset.

Abstract: Aspects of the present invention are directed at centrally managing the allocation of memory to executable images in a way that inhibits malware from identifying the location of the executable image. Moreover, performance improvements are implemented over traditional systems that enable relative addressed instruction to be resolved at runtime. In this regard, a method is provided that identifies a randomized location to load the executable image into a memory address space. Then, data that may be used to resolve the relative addressed instruction is loaded and maintained in memory. At runtime when pages that store relative addressed instructions are accessed, an arithmetic operation is performed to resolve the relative addressed instruction. As a result, only those relative addressed instructions on pages accessed during program execution are resolved.

Abstract: A table-based driving circuit for displays that switches between a normal operational mode and a read table block mode. The driving circuit comprises an address sequencer and a memory. The memory comprises the full table of individual sequences, such as interlacing or color-sequential sequence. In the read table mode, the next upcoming addresses are read, i.e. are downloaded, from the memory into an address table register in the address sequencer. In the normal operational mode, the address sequencer generates the addresses for the video data to be stored in the memory or to be displayed.

Abstract: A method and apparatus for different embodiments of incremental garbage collection of data in a secondary storage. In one embodiment, a method comprises locating blocks of data in a log that are referenced and within a range at a tail of the log. The method also includes copying the blocks of data that are referenced and within the range to an unallocated segment of the log.

Abstract: A method of assigning a multi-dimensional physical address to a tape-based data storage device is provided. The method includes accessing a first signal from a first communication path electrically coupled to a first tape-based data storage device, wherein the first signal indicates a physical position of the first tape-based data storage device with respect to a first axis. The method further includes accessing a second signal from a second communication path electrically coupled to the first tape-based data storage device, wherein the second signal is associated with a physical position of the first tape-based data storage device with respect to a second axis.

Abstract: A method for reducing a memory map table search time when employing a semiconductor memory device as a temporary memory of large capacity storage device, and a semiconductor memory device therefore, are provided. A MAP RAM is prepared for storing map table data related to the nonvolatile memory area in the volatile memory area. At an initial power-up operation, it is determined whether a logical address is searched for from the map table data while the map table data existing in a map storage area of the nonvolatile memory area is loaded into the MAP RAM. A physical address corresponding to the logical address is provided as an output, when the logical address is searched for. Search time for a memory map table is reduced and read performance in a high speed map information search is increased.

Abstract: A data storing part outputs n-bit data according to a reading address generated by an address generator. A peak value candidate selecting part selects a maximum value of a plurality of elements forming the n-bit data as a peak value candidate when data of one data unit is expressed as one element and outputs the peak value candidate together with a positional information indicating an element position of the peak value candidate. When the peak value candidate is larger than a peak value held in a peak value holding part, a peak value calculating part calculates an address of the peak value candidate using the positional information of the peak value candidate and a reading address, outputs the address and the peak value candidate to the peak value holding part, and updates content held in the peak value holding part.

Abstract: Provided are a backup data management system and a backup data management method capable of facilitating the management of backup data that is multiplexed between different storage apparatuses. The backup data management system includes a storage apparatus having a volume to be used by a host computer, at least one storage apparatus having volumes, and a management computer. The management computer creates a copy pair so that a snapshot of the volume included in a backup group is stored in all the volumes included in the backup group, and sets all copy pairs included in the designated backup group to a PAIR status when there is a creation request of the snapshot of the volume.

Abstract: A method, system, apparatus, and computer-readable medium are provided for improved maintenance of metadata relating to a mass storage array. The metadata may comprise the data structures utilized by a thin provisioning system. When the metadata changes, such as in response to the modification of the underlying data, changed metadata is created in the memory. A parity block is then read from the row of the array where the changed metadata is to be stored. A new parity is calculated for the row using only the old metadata, the changed metadata, and the parity read from the stripe. The old metadata need not be read from disk expressly, as is usually done. Instead, the value that is present in memory before the metadata change is utilized directly to calculate the new parity. The changed metadata and the new parity are then written to the array.

Abstract: A data processing system includes one or more nodes, each node including a memory sub-system. The sub-system includes a fine-grained, memory, and a less-fine-grained (e.g., page-based) memory. The fine-grained memory optionally serves as a cache and/or as a write buffer for the page-based memory. Software executing on the system uses a node address space which enables access to the page-based memories of all nodes. Each node optionally provides ACID memory properties for at least a portion of the space. In at least a portion of the space, memory elements are mapped to locations in the page-based memory. In various embodiments, some of the elements are compressed, the compressed elements are packed into pages, the pages are written into available locations in the page-based memory, and a map maintains an association between the some of the elements and the locations.

Abstract: A request tracking data prefetch apparatus for a computer system is described. The apparatus includes a prefetcher coupled to a memory of the computer system. A tracker is coupled to the prefetcher, and is configured to recognize an access to a plurality of cache lines of the memory by a processor of the computer system. A cache memory is coupled to the prefetcher. The prefetcher predictively loads a target cache line of the memory into the cache memory. The target cache line for the predictive load is indicated by the tracker.

Abstract: Methods of maintaining an address table for mapping logical addresses to physical addresses include continuously consolidating main address maps and an update address map, and periodically compacting the update address map. Consolidating includes selecting a main address map, reading valid mapping entries from the main and update address maps, constructing a mapping set including the valid mapping entries, and writing the mapping set to a second main address map. The update address map is compacted if a criterion is met, and includes copying the valid mapping entries to an unwritten block or metablock and assigning the unwritten block or metablock as a new update address map. The length of consolidation may depend on the average length of compacted mapping entries following a compaction operation. Increased performance due to lower maintenance overhead may result by using these methods.

Abstract: A system, method and computer program product for translations in a computer system. The system includes a general purpose register containing a base address of an address translation table. The system also includes a millicode accessible special displacement register configured to receive a plurality of elements to be translated. The system further includes a multiplexer for selecting a particular one of the plurality of elements from the millicode accessible special displacement register and for generating a displacement or offset value. The system further includes an address generator for creating a combined address containing the base address from the general purpose register and the generated displacement or offset value.

Abstract: Methods and apparatus may operate to receive allocation requests from a processor configured to manage memory comprising a non-volatile memory device configurable as a plurality of blocks comprising a plurality of sectors, assign partial page blocks from the plurality of blocks for memory storage, fill some of the sectors by storing data bits associated with the allocation request in the at least one of the plurality of sectors, determine that the sectors are full, assigning a full page block from the plurality of blocks, and transfer the data bits associated with the allocation request from the partial page blocks to the full page block. Other apparatus, systems, and methods are disclosed.

Abstract: Methods and apparatus are disclosed for generating a result based on a lookup result from a lookup operation using an associative memory and processing based on a discriminator portion of a lookup word. A first lookup operation is performed to generate a lookup result. In one implementation, a second lookup operation is performed based on a discriminator or the lookup result depending on the result of an evaluation, such as whether there was a hit or the lookup result matches a predetermined value. In one implementation, a second lookup operation is performed based on the discriminator, and either the result of the first or second lookup operation is used for subsequent processing. One implementation performs a lookup operation based on a lookup word to generate a lookup result, which is used to retrieve a base address and a bitmap from a memory.

Abstract: A method for managing a virtual memory system configured to allow multiple page sizes is described. Each page size has at least one table associated with it. The method involves maintaining entries in the tables to keep track of the page size for which the effective address is mapped. When a new effective address to physical address mapping needs to be made for a page size, the method accesses the appropriate tables to identify prior mappings for another page size in the same segment. If no such conflicting mapping exists, it creates a new mapping in the appropriate table. A formula is used to generate an index to access a mapping in a table.

Abstract: Handling I/O operations for a storage array includes distributing metadata among separate memories of a plurality of directors of the storage array, where the metadata correlates logical device data with physical device data. A first one of the directors receives an I/O operation for a particular logical device. Handling I/O operations may also include determining which of the plurality of directors contains metadata corresponding to the particular logical device, and, in response to the metadata being on a different one of the directors, the first director providing a request to the different one of the directors. The directors may be interconnected by an interconnect fabric. The first one of the directors may provide a request to the second one of the directors via the interconnect fabric. Determining which of the plurality of directors contains metadata correspond to the particular logical device may include using a lookup table.

Abstract: An SAS domain map is automatically generated at an SAS concentrator switch by a virtual mapping device that presents itself as a target for discovery by SAS devices interfaced with the concentrator, such as information handling systems and storage devices. During the SAS protocol discovery process, the virtual mapping device generates the SAS domain map by acquiring the device name and the device port for each concentrator port that interfaces with a device. A management application running on the concentrator applies the SAS domain map to provide network functions, such as zoning or diagnostics.

Abstract: A lookup unit matrix combines a plurality of lookup units to provide a longest prefix match for a search key longer than the lookup unit's mapper key. A portion of the search key is provided to each of the plurality of lookup units in a single search request issued to the lookup unit matrix. Each lookup unit in the lookup unit matrix performs a multi-level search for the result value based on the portion of the search key forwarded as the mapper key and the result of a multilevel search in the previous lookup unit. The search results in a value corresponding to the search key stored in a single location in one of the lookup units.

Abstract: Mapping tables are for stipulating information for primarily identifying computers, information for identifying a group of the computers and a logical unit number permitting access from the host computer inside storage subsystem, in accordance with arbitrary operation method by a user, and for giving them to host computer. The invention uses management table inside the storage subsystem and allocates logical units inside the storage subsystem to a host computer group arbitrarily grouped by a user in accordance with the desired form of operation of the user, can decide access approval/rejection to the logical unit inside the storage subsystem in the group unit and at the same time, can provide the security function capable of setting interface of connection in the group unit under single port of storage subsystem without changing existing processing, limitation and other functions of computer.