Abstract: The display color of, for example, a button image responsive to a command input into a facility operation display device is controlled by a palette value having a smaller number of bits than an RGB value. When the display color of the button image is changed, the palette value of a drawing object associated with the button image is changed to an RGB value. This eliminates the necessity of incorporating, for example, a high-performance CPU as a central arithmetic unit. In addition, it is not necessary to pre-store images corresponding to several kinds of display colors specified by RGB values, to thereby eliminates the necessity of incorporating, for example, a high-capacity storage medium in the facility operation display device. Accordingly, the device cost can be reduced.

Abstract: Systems, servers, methods, media, and programs for storing a list of options associated with object-types, such as a chart-type, selected during an on-line session. When a new object-type is selected, some of the options in the first object-type are copied from the options list associated with the first object-type to the options list associated with the second (new) object-type. The list of options to be transferred is determined by a set rules associated with a transferable array and a set of rules associated with a quarantine set. The transferrable array includes rules for options available for transfer, and quarantine list includes rules for options and type pairs that are not available for transfer.

Abstract: Embodiments of techniques and systems for using substitute virtualized-memory page tables are described. In embodiments, a virtual machine monitor (VMM) may determine that a virtualized memory access to be performed by an instruction executing on a guest software virtual machine is not allowed in accordance with a current virtualized-memory page table (VMPT). The VMM may select a substitute VMPT that permits the virtualized memory access, In scenarios where a data access length for the instruction is known, the substitute VMPT may include full execute, read, and write permissions for the entire guest software address space. In scenarios where a data access length for the instruction is not known, the substitute VMPT may include less than full execute, read, and write permissions for the entire guest software address space, and may be modified to allow the requested virtualized memory access. Other embodiments may be described and claimed.

Abstract: A method begins by a processing module determining an imbalance between inode utilization and data storage utilization. When the imbalance compares unfavorably to an imbalance threshold, the method continues with the processing module determining whether utilization of another inode memory and utilization of another corresponding data storage memory are not imbalanced. When the utilization of the other inode memory and the utilization of the other corresponding data storage memory are not imbalanced, determining whether the inode utilization is out of balance with respect to the data storage utilization. When the inode utilization is out of balance, the method continues with the processing module transferring data objects from a data storage memory to the other corresponding data storage memory and transferring mapping information of data objects from a inode memory to the other inode memory.

Abstract: Embodiments of the present invention are directed to a method and system for allowing data structures to be moved between storage locations of varying performance and cost without changing the application firmware. In one embodiment, rather than application firmware directly accessing memory, the application firmware requests a data structure by parameters, to which the implementation returns a pointer. The parameters can be, for example, the logical block address of a data sector, and the data structure can be mapping and associated information of that logical block address (LBA) to a location in the flash device.

Abstract: A method begins by a processing module determining an imbalance between inode memory utilization and data storage memory utilization. When the imbalance compares unfavorably to an imbalance threshold, the method continues with the processing module determining whether the inode memory utilization is out of balance with respect to the data storage memory utilization or whether the data storage memory utilization is out of balance with respect to the inode memory utilization. When the inode memory utilization is out of balance with respect to the data storage memory utilization, the method continues with the processing module transferring a set of data objects from a data object section to a data block section and transferring object mapping information of the set of data objects into block mapping information for the set of data objects.

Abstract: An apparatus and method are described for performing history-based prefetching. For example a method according to one embodiment comprises: determining if a previous access signature exists in memory for a memory page associated with a current stream; if the previous access signature exists, reading the previous access signature from memory; and issuing prefetch operations using the previous access signature.

Abstract: The present disclosure includes methods, devices, and systems for a logical address offset. One method embodiment includes detecting a memory unit formatting operation. Subsequently, in response to detecting the formatting operation, the method includes inspecting format information on the memory unit, calculating a logical address offset, and applying the offset to a host logical address.

Abstract: In response to a memory allocation request received from an application thread, a random number is obtained (e.g., from a random number list previously populated with multiple random numbers). A starting location in at least a portion of a bitmap associated with a region including multiple blocks of the memory is determined based on the random number. A portion of the bitmap is scanned, beginning at the starting location, to identify a location in the bitmap corresponding to an available block of the multiple blocks, and an indication of this available block is returned to the application thread.

Abstract: A disk drive is disclosed comprising a disk having a host addressable area and a reserved area, an exception table stored in the reserved area, a head actuated radially over the disk to write data to the disk, and control circuitry coupled to the head. The control circuitry receives a first command from the host to write first host data into a first physical sector on the disk, wherein the first host data comprises an amount of data less than a full storage capacity of the first physical sector. The control circuitry detects an uncorrectable error while reading the first physical sector during read-modify-write operation, and indicates in the exception table that the first physical sector is a partial sector including valid and invalid logical block addresses (LBAs).

Abstract: A mechanism for tracking memory accesses in a non-uniform memory access (NUMA) system to optimize processor task placement is disclosed. A method of embodiments of the invention includes creating a page table (PT) hierarchy associated with a thread to be run on a processor of a computing device, collecting access bit information from the PT hierarchy associated with the thread, wherein the access bit information includes any access bits in the PT hierarchy that are set by a memory management unit (MMU) of the processor to identify a page of memory accessed by the thread, determining memory access statistics for the thread, and utilizing the memory access statistics for the thread in a determination of whether to migrate the thread to another processor.

Abstract: A translation lookaside buffer (TLB) is disclosed formed using RAM and synthesisable logic circuits. The TLB provides logic within the synthesisable logic for pairing down a number of memory locations that must be searched to find a translation to a physical address from a received virtual address. The logic provides a hashing circuit for hashing the received virtual address and uses the hashed virtual address to index the RAM to locate a line within the RAM that provides the translation.

Abstract: A virtual-machine-based system provides a mechanism for a virtual machine monitor (VMM) to process a hypercall received from an application running in the virtual machine (VM). A hypercall interface causes the virtual memory pages, needed by the VMM to process the hypercall, to be available to the VMM. In one embodiment, when virtual memory pages needed by the VMM to process the hypercall are not available to the VMM, the application is caused to access the needed pages, in response to which the required virtual memory becomes available to the VMM.

Abstract: Some of the embodiments of the present disclosure provide a method for predicting, for a first virtual address, a first descriptor based at least in part on the one or more past descriptors associated with one or more past virtual addresses; and determining, for the first virtual address, a first physical address based at least in part on the predicted first descriptor. Other embodiments are also described and claimed.

Abstract: An image display device includes: an external light measurement unit measuring the illuminance of an external light a plurality of times, and generating a measurement value indicating the illuminance; a storage unit storing history data which shows the measurement values, and color mode data which shows a correspondence between the illuminance and a color mode; a determination unit, based on the history data, determining whether or not it is a changed condition wherein the illuminance changes upward or downward, or the illuminance fluctuates; and an adjustment unit, in the event that it is not the changed condition, determining the color mode to be applied based on the measurement values and the color mode data, and adjusting the color or brightness of an image in accordance with the color mode, and in the event that it is the changed condition, continuing the adjustment currently being applied as the image adjustment.

Abstract: An indirection system in a shingled storage device is described that uses an algorithm to map LBAs to DBAs based on a predetermined rule or assumption and then handles as exceptions LBAs that are not mapped according to the rule. The assumed rule is that a fixed-length set of sequential host LBAs are located at the start of an I-track. Embodiments of the invention use two tables to provide the mapping of LBAs to DBAs. The mapping assumed by the rule is embodied in the LBA Block Address Table (LBAT) which gives the corresponding I-track address for each LBA Block. The LBA exceptions are recorded using an Exception Pointer Table (EPT), which gives the pointer to the corresponding variable length Exception List for each LBA Block. The indexing into the LBAT and the EPT is derived from the LBA by a simple arithmetic operation.

Abstract: An implantable medical device and associated method store physiological data in response to detecting a physiological event. The medical device includes multiple first memory locations allocated to each of a number of physiological event types and a second single memory location allocated for storing entries of physiological signal data corresponding to each of the plurality of physiological event types.

Abstract: A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata.

Abstract: Since only one golden image (GI) of a snapshot can exist and is shared among a plurality of storage apparatuses, there was a problem that migration or copy thereof deteriorates the capacity efficiency and increases the cost for managing consistency. The present invention solves the above-mentioned problem by either (1) a direct sharing method of generating a parent-child relationship of snapshots among different storage apparatuses at the time of creating differential LUs from the GI or (2) a virtual sharing method of creating virtual LUs of the GI in the respective storage apparatuses and creating differential LUs of the snapshots from the created virtual LUs, using a storage virtualization function among a plurality of storage apparatuses.

Abstract: A controller includes a storage for a translation table showing logical and physical addresses in a flash memory in correspondence with one another; another storage storing FAT information indicating the state of data stored in each of pages contained in each of blocks and FAT information identifiers each identifying a block to which pages each storing therein the data in the state indicated by the FAT information belong, while keeping them in correspondence with one another; yet another storage for a block management table showing block identifiers, use-state judging information indicating whether the corresponding block is used/unused, and the FAT information identifiers corresponding to all the blocks indicated as being used by the use-state judging information, while keeping them in correspondence with one another; and a controller controlling unit managing data stored in the flash memory by using the translation table, the FAT information, and the block management table.

Abstract: Machine-reading media and method for managing data in a non-volatile memory. The method comprises the steps: a plurality of first logical offsets may be assigned to a plurality of first fragments of a first memory block, a first fragment of the plurality of first fragments may store data; a plurality of second logical offsets may be assigned to a plurality of second fragments of a second memory block, a second fragment of the plurality of second fragments may be associated with the first fragment, a second logical offset assigned to the second fragment may be identical to a first logical offset assigned to the first fragment; then, data may be copied from the first fragment to the second fragment.

Abstract: A virtual logical unit that stores learning metadata is allocated in a first storage server having a first plurality of clusters, wherein the learning metadata indicates a type of storage device in which selected data of the first plurality of clusters of the first storage server are stored. A copy services command is received to copy the selected data from the first storage server to a second storage server having a second plurality of clusters. The virtual logical unit that stores the learning metadata is copied, from the first storage server to the second storage server, via the copy services command. Selected logical units corresponding to the selected data are copied from the first storage server to the second storage server, and the learning metadata is used to place the selected data in the type of storage device indicated by the learning metadata.

Abstract: Embodiments of the present invention provide a system that generates an index for a cache memory. The system starts by receiving a request to access the cache memory, wherein the request includes address information. The system then obtains non-address information associated with the request. Next, the system generates the index using the address information and the non-address information. The system then uses the index to fulfill access the cache memory.

Abstract: Concurrent resizing and modification of a first RCU-protected hash table includes allocating a second RCU-protected hash table, populating it by linking each hash bucket of the second hash table to all hash buckets of the first hash table containing elements that hash to the second hash table bucket, and publishing the second hash table. If the modifying comprises insertion, a new element is inserted at the head of a corresponding bucket in the second hash table. If the modifying comprises deletion, then within an RCU read-side critical section: (1) all pointers in hash buckets of the first and second hash tables that reference the element being deleted are removed or redirected, and (2) the element is freed following a grace period that protects reader references to the deleted element. The first table is freed from memory after awaiting a grace period that protects reader references to the first hash table.

Abstract: Systems and/or methods that facilitate logical block address (LBA) to physical block address (PBA) translations associated with a memory component(s) are presented. The disclosed subject matter employs an optimized block address (BA) component that can facilitate caching the LBA to PBA translations within a memory controller component based in part on a predetermined optimization criteria to facilitate improving the access of data associated with the memory component. The predetermined optimization criteria can relate to a length of time since an LBA has been accessed, a number of times the LBA has been access, a data size of data related to an LBA, and/or other factors. The LBA to PBA translations can be utilized to facilitate accessing the LBA and/or associated data using the cached translation, instead of performing various functions to determine the translation.

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract: An electronic device receives satellite signals from positioning information satellites and acquires positioning information and time information. A stored data table comprises a first block of data having a first array of time difference data and a second block of data having a second array of time difference data that is different than the first array of time difference data. A stored memory address table stores the memory address of each of the first and second blocks of data, at least one the blocks of data being stored a plurality of times in the memory address table. The data block corresponding to the acquired positioning information is identified, the memory address corresponding to that data block is read, the data block data indicated by the memory address is acquired, and the time difference data for the segment corresponding to the positioning information is acquired from the data block.

Abstract: Described herein are method and apparatus for using an LLRRM device as a storage device in a storage system. At least three levels of data structures may be used to remap storage system addresses to LLRRM addresses for read requests, whereby a first-level data structure is used to locate a second-level data structure corresponding to the storage system address, which is used to locate a third-level data structure corresponding to the storage system address. An LLRRM address may comprise a segment number determined from the second-level data structure and a page number determined from the third-level data structure. Update logs may be produced and stored for each new remapping caused by a write request. An update log may specify a change to be made to a particular data structure. The stored update logs may be performed on the data structures upon the occurrence of a predetermined event.

Abstract: User data transferred from a host apparatus and a first information table 35 indicating correspondence between a logical address and a physical address are recorded in a first region of a flash memory 20. A second information table 38 composed of the physical block address storing the first information table 35 and the number of times of update of the physical block for recording the first information table from the time of manufacturing is recorded in a second region of the flash memory 20. The physical blocks of the first and the second regions are recorded independently from each other in a rotational manner. According to the recording of the second information table, the total number of times of rewriting of the first region is converted. This can suppress the number of times of rewriting of the second region and improve reliability of the number of times of update of the first information table from the time of manufacturing, the number being recorded in the second region.

Abstract: A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory.

Abstract: Various embodiments of a system and method for updating backup configuration information used by backup software to perform backup operations for a storage cluster are described. Backup configuration information specifying a configuration of the storage cluster may be stored. Subsequently, a particular change to the configuration of the storage cluster may be automatically detected. In response to detecting the particular change, the backup configuration information may be automatically updated to reflect the particular change to the configuration of the storage cluster. Subsequent backup operations may then be performed using the updated backup configuration information.

Abstract: Process, cache memory, computer product and system for loading data associated with a requested address in a software cache. The process includes loading address tags associated with a set in a cache directory using a Single Instruction Multiple Data (SIMD) operation, determining a position of the requested address in the set using a SIMD comparison, and determining an actual data value associated with the position of the requested address in the set.

Abstract: A lookup is performed using multiple levels of compressed stride tables in a multi-bit Trie structure. An input lookup key is divided into several strides including a current stride of S bits. A valid entry in a current stride table is located by compressing the S bits to form a compressed index of D bits into the current stride table. A compression function logically combines the S bits to generate the D compressed index bits. An entry in a prior-level table points to the current stride table and has a field indicating which compression function and mask to use. Compression functions can include XOR, shifts, rotates, and multi-bit averaging. Rather than store all 2S entries, the current stride table is compressed to store only 2D entries. Ideally, the number of valid entries in the current stride table is between 2D?1 and 2D for maximum compression. Storage requirements are reduced.

Abstract: One or more methods and systems of improving performance and reducing the size of a translation lookaside buffer are presented. In one embodiment, the method comprises using a bit obtained from a virtual page number to store even and odd page frame numbers into a single page frame number field of a miniature translation lookaside buffer (mini-TLB). In one embodiment, even and odd page frame number fields are consolidated into a single page frame number field. In one embodiment, the mini-TLB facilitates the use of a buffer or memory of reduced size. Furthermore, in one or more embodiments, aspects of the invention may be found in a system and method that easily incorporates and adapts the use of existing control processor instruction sets or commands of a typical translation lookaside buffer.

Abstract: Described embodiments provide a media controller that determines the size of a cache of data being transferred between a host device and one or more sectors of a storage device. The one or more sectors are segmented into a plurality of chunks, and each chunk corresponds to at least one sector. The contents of the cache are managed in a cache hash table. At startup of the media controller, a buffer layer module of the media controller initializes the cache in a buffer of the media controller. During operation of the media controller, the buffer layer module determines a number of chunks allocated to the cache. Based on the number of chunks allocated to the cache, the buffer layer module updates the size of the of the cache hash table.

Abstract: A plural-partitioned type nonvolatile storage device which solves the problem that a memory card composed of a flash memory and a controller, when a storage area is divided into a plurality of partitions, cannot be correctly used with a conventional host apparatus incapable of recognizing plural partitions. The memory card includes, as its storage areas, a device characteristic data storage area, a division table storage area, and a device storage area, where the device storage area is partitioned into plural partitions. The memory card can have different modes for adapting different accesses from the external host, and allows the external host to access partitions corresponding to the mode. Division information as to a dividing method for the plural partitions, and access information as to the host-accessible partitions corresponding to each individual mode are stored in the division table storage area.

Abstract: A method for processing booting failure of a computer system is adapted for being performed at a computer. The method includes the following steps. First, a parameter selecting signal is generated according to a triggering signal by a control module. Second, a driving parameter is chosen from a look-up table according to the parameter selecting signal by a basic input output system (BIOS), and the driving parameter is loaded into the BIOS and provided to a driving module. Third, a memory is driven according to the driving parameter by the driving module. Fourth, the driving parameter is stored by BIOS.

Abstract: A method of transmitting data between a plurality of inter-connected elements. The method comprises receiving a message from a first element, said message comprising a routing key plus optionally a data payload. The routing key is processed to identify a plurality of said inter-connected elements, and data is transmitted to said identified plurality of inter-connected elements.

Abstract: A memory controller includes ports and corresponding tables. Each port is receptive to one or more memory modules. Each table includes entries mapping memory addresses to the memory modules. Each entry corresponds to no more than one of the memory modules. The tables support asymmetric population of the memory modules within the ports; each port is capable of having a different number of memory modules relative to the other ports. The tables impose no restrictions on where the memory modules are to be inserted within the ports, both number-wise and position-wise. The tables are independently configurable; the configuration of each table is modifiable independently of the configurations of the other tables. Each table is dynamically configurable. The entries of a table are modifiable to reflect changes in the number and type of the memory modules connected, without restarting or temporarily halting the computer system containing the memory controller.

Abstract: A method for facilitating fast reconstruction of metadata structures on a memory storage device includes writing a plurality of checkpoints holding a root of metadata structures in an increasing order of timestamps to a plurality of blocks respectively on the memory storage device utilizing a memory controller, where each checkpoint is associated with a timestamp, and wherein the last-written checkpoint contains a root to the latest metadata information from where metadata structures are reconstructed.

Abstract: Provided is a memory access device including multiple processors accessing a specific memory. The memory access device includes first and second processors, first and second transaction controllers, a memory access switch, and a memory controller. The first and second transaction controllers are connected respectively to the first and second processors. The memory access switch is connected to the first and second transaction controllers. The memory controller is connected to the memory access switch to control a memory device. Herein, if the first and second processors simultaneously access the memory device, the second processor stores an address or data in the second transaction controller while the first processor is accessing the memory device.

Abstract: A method for indicating storage capacity is applied in a storage device. The storage device includes a main storage unit, a capacity indicator, a driver, and a secondary storage unit. The second storage unit stores a preset storage capacity value and a drive table recording relationship between storage capacity difference ranges and rotation angles of the driver. The method includes: periodically obtaining a storage capacity value from a computer connected to the storage device; computing a difference between the obtained storage capacity value and the preset storage capacity value; determining the storage capacity difference range the difference falls within and the rotation angle the determined storage capacity difference range corresponds to in the drive table; and controlling the driver to rotate the determined rotation angle to drive the capacity indicator to indicate the obtained storage capacity value. A related storage device is also provided.

Abstract: A plurality of catalogs are maintained, and wherein each catalog of the plurality of catalogs includes data sets and attributes of the data sets. An indication that a new data set is to be defined is received. A selected catalog is determined from the plurality of catalogs, wherein the selected catalog is suitable for including the new data set and attributes of the new data set. An entry that indicates a data set name corresponding to the new data set and an index to the selected catalog is inserted in a group table.

Abstract: Certain aspects of a method and system for host bus adapter assisted storage virtualization are disclosed. Aspects of one method may include loading storage virtualization functionality into one or more of: a storage driver, a network driver, a network interface card (NIC), and a host bus adapter. A SCSI request may be translated to obtain physical target information utilizing a translation table located on one or more of: the storage driver, the network driver, the NIC and the host bus adapter. At least a portion of a plurality of the translated SCSI requests may be cached on the host bus adapter or the NIC.

Abstract: A flash memory storage system including a flash memory chip, a connector, and a flash memory controller is provided. The flash memory controller configures a plurality of logical addresses and maps the logical addresses to a part of the physical addresses in the flash memory chip, and a host system uses a file system to access the logical addresses. Besides, the flash memory controller identifies a deleted logical address among the logical addresses and marks data in the physical address mapped to the deleted logical address as invalid data.

Abstract: In one embodiment, in response to receiving a topology change notification at a network bridge having ports identified as either a network port or an edge port, address learning may be disabled on the network bridge. Once address learning is disabled, an association of all entries of a forwarding table of the network bridge having addresses previously forwarded on a particular network port of the network bridge may be changed to forward those addresses on all network ports of the network bridge (e.g., flooding the frames not addressed to edge ports on all network ports only). Subsequently, address learning may be enabled on the network bridge, thus repopulating the network port entries of the forwarding table in response to the topology change.

Abstract: Assuring recovery from failure of a storage server in a distributed column chunk data store of operably coupled storage servers, includes: partitioning a data table into chunks; implementing a distribution scheme with a specified level of redundancy for recovery of one or more failed servers among multiple storage servers; distributing the column chunks according to the distribution scheme; calculating column chunk parity; storing the calculated column chunk parity; managing metadata for the column chunk data store; and updating the metadata for distributing the column chunks among remaining storage servers upon receiving an indication to remove a storage serve.

Abstract: Methods, systems, and computer program products for controlling information read/write processing. The method includes assigning a plurality of division areas to a shared storage area for storing a shared object: specifying a division area used for read/write processing in accordance with user identification information for identifying a user; and executing the read processing for reading information from a specified division area and the write processing for writing information to the specified division area. The shared object is shared among a plurality of processes.

Abstract: Machine-readable media, methods, apparatus and system for managing sectors of a non-volatile memory are described. In some embodiments, a plurality of file segments may be written to a plurality of memory sectors (501), each memory sector of the plurality of memory sectors for each file segment of the plurality of file segments. Then, a plurality of flags may be searched from a first section of a sector table (502), each flag of the plurality of flags corresponding to the each file segment. A section may be selected from a second section and a third section of the sector table, wherein the section may be indicated by the plurality of flags (505,507). A plurality of physical addresses for the plurality of memory sectors may be written to the section (506,508).

Abstract: A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random access memories (RAMs), multiplexers, and pointers that allow static or dynamic bandwidth configuration as function of instruments examining the system traffic using queues. The interface allows many initiators having many logical threads to share and use many physical threads in different queue modules.