Addressing Cache Memories Patents (Class 711/3)
  • Patent number: 7266651
    Abstract: A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address and a number of bits of a different portion of the current address. The current address corresponds to a current location in the memory. In addition, the method includes performing a data swap on data stored at the current location with data stored at the new location.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: September 4, 2007
    Assignee: Sun Microsystems, Inc.
    Inventor: Robert E. Cypher
  • Patent number: 7254680
    Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: August 7, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
  • Patent number: 7246202
    Abstract: In a computer system that concurrently executes a plurality of tasks, a cache controller eliminates the possibility of the hit rate of one task dropping due to execution of another task. A region managing unit manages a plurality of regions in a cache memory in correspondence with a plurality of tasks. An address receiving unit receives, from a microprocessor, an address of a location in a main memory at which data to be accessed to execute one of the plurality of tasks is stored. A caching unit acquires, if the data to be accessed is not stored in the cache memory, a data block including the data from the main memory, and stores the acquired data block into a region in the cache memory corresponding to the task.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: July 17, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hiroyuki Morishita, Tokuzo Kiyohara
  • Patent number: 7243192
    Abstract: A single memory element, which may consist of general purpose SRAM chips, implements both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose RAM used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose RAM before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides in the cache memory. The comparison may also be performed concurrently by a system controller device, which may abort the main memory access if a cache hit is detected.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: July 10, 2007
    Assignee: PMC-Sierra, Inc.
    Inventors: Michael DeMar Taylor, John R. Kinsel, Tom Riordan
  • Patent number: 7240143
    Abstract: A low-latency storage memory system is built from multiple memory units such as high-density random access memory. Multiple access ports provide access to memory units and send the resultant data out interface ports. The memory units communicate with the access ports through an interconnected mesh to allow any access port to access any memory unit. An address virtualization mechanism using address translators allows any access port of the memory storage system to access requested data as abstract objects without regard for the physical memory unit that the data is located in, or the absolute memory addresses within that memory unit.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: July 3, 2007
    Assignee: Broadbus Technologies, Inc.
    Inventors: Robert G. Scheffler, Michael A. Kahn, Frank J. Stifter
  • Publication number: 20070150640
    Abstract: An integrated circuit 2 is provided with a cache memory 6 and a cache controller 10 coupled to the cache memory 6 via a cache memory interface 8. The cache controller supports different cache memory sizes. The cache memory 6 includes masking logic 14 responsive to cache memory size signals to form masked address values for use in accessing the cache memory 6. The cache controller 10 can be part of a processor core 4 which may be hardened in its design and yet able to cope with variable cache memory sizes since the masking logic 14 is provided within the cache memory 6 outside of the hardened periphery of the processor core 4.
    Type: Application
    Filed: December 6, 2006
    Publication date: June 28, 2007
    Applicant: ARM LIMITED
    Inventors: Florent Begon, Vladimir Vasekin, Andrew Christophe Rose, Nicolas Chaussade
  • Patent number: 7213126
    Abstract: A processor includes a trace cache memory coupled to a trace generator. The trace generator may be configured to generate a plurality of traces each including one or more operations that may be decoded from one or more instructions. Each of the operations may be associated with a respective address. The trace cache memory is coupled to the trace generator and includes a plurality of entries each configured to store one of the traces. The trace generator may be further configured to restrict each of the traces to include only operations having respective addresses that fall within one or more predetermined ranges of contiguous addresses.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: May 1, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gregory William Smaus, Raghuram S. Tupuri, Gerald D. Zuraski, Jr.
  • Patent number: 7209989
    Abstract: Method and apparatus relating to an acknowledgement mechanism in an interconnected subsystem architecture. After a data message is transmitted, the transmitting device may transmit an acknowledge message on a channel undefined by the inter-subsystem communication protocol associated with the interconnection architecture. The undefined channel may be generated using a device-specific identifier on a channel defined to be a broadcast channel. The receiving device may acknowledge the transfer by switching a sideband control signal line.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: April 24, 2007
    Assignee: Intel Corporation
    Inventor: Peter D. Mueller
  • Patent number: 7203790
    Abstract: Caches are associated with processors, such multiple caches may be associated with multiple processors. This association may be different for different main memory address ranges. The techniques of the invention are flexible, as a system designer can choose how the caches are associated with processors and main memory banks, and the association between caches, processors, and main memory banks may be changed while the multiprocessor system is operating. Cache coherence may or may not be maintained. An effective address in an illustrative embodiment comprises an interest group and an associated address. The interest group is an index into a cache vector table and an entry into the cache vector table and the associated address is used to select one of the caches. This selection can be pseudo-random. Alternatively, in some applications, the cache vector table may be eliminated, with the interest group directly encoding the subset of caches to use.
    Type: Grant
    Filed: August 5, 2005
    Date of Patent: April 10, 2007
    Assignee: International Business Machines Corporation
    Inventors: Monty Montague Denneau, Peter Heiner Hochschild, Henry Stanley Warren, Jr.
  • Patent number: 7181568
    Abstract: The disclosure includes a description of a content addressable memory (CAM) that includes at least one tag input and at least one random access memory. The CAM also includes circuitry to perform multiple read operations of the at least one random access memory with multiple, different ones of the read operations specifying an address based on different subsets of tag bits. The circuitry includes digital logic circuitry coupled to the at least one random access memory to determine whether a lookup tag matches a subset of the different subsets of tag bits.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: February 20, 2007
    Assignee: Intel Corporation
    Inventors: Mark B. Rosenbluth, Gilbert Wolrich
  • Patent number: 7177987
    Abstract: Systems and method are disclosed for providing responses for different cache coherency protocols. One embodiment may comprise a system that includes a first node employing a first cache coherency protocol. A detector associated with the first node detects a condition based on responses provided by the first node to requests provided according to a second cache coherency protocol, the second cache coherency protocol being different from the first cache coherency protocol. The first node provides a response to a given one of the requests to the first node that varies based on the condition detected by the detector.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: February 13, 2007
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Stephen R. Van Doren, Gregory Edward Tierney, Simon C. Steely, Jr.
  • Patent number: 7177986
    Abstract: A cache is configured to receive direct access transactions. Each direct access transaction explicitly specifies a cache storage entry to be accessed in response to the transaction. The cache may access the cache storage entry (bypassing the normal tag comparisons and hit determination used for memory transactions) and either read the data from the cache storage entry (for read transactions) or write data from the transaction to the cache storage entry (for write transactions). The direct access transactions may, for example, be used to perform testing of the cache memory. As another example, direct access transactions may be used to perform a reset of the cache (by writing known data to each cache entry). In embodiments employing error checking and correction (ECC) mechanisms, direct access write transactions could also be used to recover from uncorrectable ECC errors, by overwriting the failing data to eliminate the errant data.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: February 13, 2007
    Assignee: Broadcom Corporation
    Inventors: Joseph B. Rowlands, Michael P. Dickman
  • Patent number: 7174405
    Abstract: A method and system for updating registers by performing an atomic read-modify-write operations initiated by a host over a host/daughtercard bus. A field in the write command determines whether data included in the write command is written to a targeted register or used as a mask to set or clear selected bits in a word held in the targeted register.
    Type: Grant
    Filed: June 6, 2003
    Date of Patent: February 6, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Leo Dumov, Eddie B. Collins, Jr.
  • Patent number: 7171540
    Abstract: One embodiment of the present invention provides an object-addressed memory hierarchy that is able to access objects stored outside of main memory. During operation, the system receives a request to access an object, wherein the request includes an object identifier for the object that is used to reference the object within the object-addressed memory hierarchy. Next, the system uses the object identifier to retrieve an object table entry associated with the object. The system then examines a valid bit within the object table entry. If the valid bit indicates the object is located in main memory, the system uses a physical address in the object table entry to access the object in main memory. On the other hand, if the valid bit indicates that the object is not located in main memory, the system relocates the object into memory from a location outside of memory, and then accesses the object in main memory.
    Type: Grant
    Filed: October 31, 2003
    Date of Patent: January 30, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Matthew L. Seidl, Gregory M. Wright, Mario I. Wolczko
  • Patent number: 7165151
    Abstract: To enhance the speed of first access (read access different in word line from the previous access) to a multi-bank memory, multi-bank memory macro structures are used. Data are held in a sense amplifier for every memory bank. When access is hit to the held data, data latched by the sense amplifier are output to thereby enhance the speed of first access to the memory macro structures. Namely, each memory bank is made to function as a sense amplifier cache. To enhance the hit ratio of such a sense amplifier cache more greatly, an access controller self-prefetches the next address (an address to which a predetermined offset has been added) after access to a memory macro structure so that data in the self-prefetched address are preread by a sense amplifier in another memory bank.
    Type: Grant
    Filed: December 14, 2004
    Date of Patent: January 16, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Kazushige Ayukawa, Seiji Miura, Jun Satoh, Takao Watanabe, Kazumasa Yanagisawa, Yusuke Kanno, Hiroyuki Mizuno
  • Patent number: 7162589
    Abstract: According to the present invention, methods and apparatus are provided for increasing the efficiency of data access in a multiple processor, multiple cluster system. Mechanisms for transmitting memory cancels to memory controllers in the various clusters of a multiple cluster system are provided. In one example, memory cancels are transmitted between clusters when it is determined that a memory line associated with a probe is dirty. The memory cancel directs the memory controller to no longer proceed with a data fetch from main memory. In another example, memory cancels are transmitted at a home cluster based on information in a coherence directory in order to more quickly end a data fetch.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: January 9, 2007
    Assignee: Newisys, Inc.
    Inventors: David B. Glasco, Rajesh Kota
  • Patent number: 7151544
    Abstract: Cache access is optimized through identifying redundant accesses (read-requests made to identical system memory addresses), and issuing a single cache data request for each group of redundant accesses. One embodiment of the invention is a graphics system comprising a system memory that stores texture data, coupled to a texture cache that is coupled to one or more texture pipes. Each pipe processes information for a respective spatial bin. A cache preprocessor receives read-requests for texels from the texture pipes and generates a control code corresponding to each read-request, indicating whether the read-request is a redundant access, and linking redundant accesses to a single cache data request. The cache preprocessor provides the control codes and the read-requests to a cache arbiter, which issues the codes and the cache data requests to the texture cache.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: December 19, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Brian D. Emberling
  • Patent number: 7146468
    Abstract: A cache memory that completes an in-flight operation with another cache that collides with a snoop operation, rather than canceling the in-flight operation. Operations to the cache comprise a query pass and one or more finish passes. When the cache detects a snoop query intervening between the query pass and a finish pass of the in-flight operation, the cache generates a more up-to-date status for the snoop query that takes into account the tag status to which the in-flight finish pass will update the implicated cache line. This is necessary because otherwise the snoop query might not see the affect of the in-flight finish pass status update. This allows the in-flight finish pass to complete instead of being cancelled and the snoop finish pass to correctly update the status after the in-flight finish pass, and to provide modified data from the cache line to the externally snooped transaction.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: December 5, 2006
    Assignee: IP-First, LLC.
    Inventor: James N. Hardage, Jr.
  • Patent number: 7143239
    Abstract: A cache structure comprising a plurality of tag arrays and a plurality of data arrays, the tag arrays each configured to point to lines of data in multiple ones of the plurality of data arrays, wherein multiple tag arrays are searched in parallel for data that may be contained in the data arrays.
    Type: Grant
    Filed: August 7, 2003
    Date of Patent: November 28, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Eric DeLan
  • Patent number: 7136969
    Abstract: Described is a technique for maintaining local cache coherency between endpoints using the connecting message fabric. Processors in a data storage system communicate using the message fabric. Each processor is an endpoint having its own local cache storage in which portions of global memory may be locally cached. A write through caching technique is described. Each local cache line of data of each processor is either in an invalid or a shared state. When a write to global memory is performed by a processor (write miss or a write hit), the following are performed atomically: the global memory is updated, other processor's local cache lines of the data are invalidated, verification of invalidation is received by the processor, and the processor's local copy is updated. Other processors' cache lines are invalidated by transmission of an invalidate command by the processor. A processor updates its local cache lines upon the next read miss or write miss of the updated cacheable global memory.
    Type: Grant
    Filed: June 17, 2003
    Date of Patent: November 14, 2006
    Assignee: EMC Corporation
    Inventors: Brett D. Niver, Steven R. Chalmer, Steven T. McClure
  • Patent number: 7130957
    Abstract: A storage system includes a cache and a collection of metadata, organized by their associations with regard to the data they represent. In one embodiment, the cache stores data blocks in a first plurality of locations. A first metadata storage stores metadata including block addresses of data blocks within the cache. A second metadata storage includes a second plurality of locations, each for storing metadata including a block address identifying a corresponding data block within the cache. The metadata stored within the second metadata storage also includes a first pointer to the corresponding data block. In addition, at least one of the second locations may store a second pointer to another of the second locations that stores metadata corresponding to a related data block. The cache and the first metadata storage are non-volatile storages; however, the second metadata storage may be a volatile storage.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: October 31, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Raghavendra J. Rao
  • Patent number: 7130968
    Abstract: A single memory element, which may consist of general purpose SRAM chips, is used to implement both tag and data cache memory functions, resulting in an efficient, low cost implementation of high speed external cache memory. In one embodiment, a bank of general purpose random access memory used by a microprocessor as an external cache memory stores both cache tags and cache data in separate memory locations. During a read operation, the microprocessor retrieves a cache tag from the bank of general purpose random access memory before retrieving corresponding cache data therefrom, and compares the cache tag to a memory address to assess whether requested data resides within the cache memory. The microprocessor preferably accesses the bank of general purpose random access memory using a memory mapping function which maps the memory address into a cache tag address and a cache data address.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: October 31, 2006
    Assignee: PMC-Sierra, Inc.
    Inventors: Michael DeMar Taylor, John R. Kinsel, Tom Riordan
  • Patent number: 7130956
    Abstract: A storage system including hierarchical cache metadata storages includes a cache, a first metadata storage, and a second metadata storage. In one embodiment, the cache may store a plurality of data blocks in a first plurality of locations. The first metadata storage may include a plurality of entries that stores metadata including block addresses of data blocks within the cache. The second metadata storage may include a second plurality of locations for storing metadata including the block addresses identifying the data blocks within the cache. The metadata stored within the second metadata storage may also include pointers to the data blocks within the cache. The cache and the first metadata storage are non-volatile storages. However, the second metadata storage may be a volatile storage.
    Type: Grant
    Filed: February 10, 2004
    Date of Patent: October 31, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Raghavendra J. Rao
  • Patent number: 7124236
    Abstract: A microprocessor including a level two cache memory including asynchronously accessible cache blocks. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a plurality of storage blocks, each configured to store a plurality of data units. Each of the plurality of storage blocks may be accessed asynchronously. In addition, the cache subsystem includes a plurality of tag units which are coupled to the plurality of storage blocks. Each of the tag units may be configured to store a plurality of tags each including an address tag value which corresponds to a given unit of data stored within the plurality of storage blocks. Each of the plurality of tag units may be accessed synchronously.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: October 17, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Teik-Chung Tan, Mitchell Alsup, Jerry D. Moench
  • Patent number: 7120152
    Abstract: A method of routing a packet in a routing device having a main processor that includes a main cache table and an instant cache table is disclosed. The instant cache stores a recent address and a recent interface associated with the most recent packet transmission process made by the routing device. The method includes the steps of receiving a packet that includes its destination address, checking whether the destination address belongs to the routing device, checking whether the destination address is identical to the recent address if the destination address does not belong to the routing device, and transmitting the packet to the recent interface if the destination address is identical to the recent address. As a result, the core information related to the routing path determination is stored not only in the routing table of the protocol layer but also in the main and instant cache tables included in the main processor.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: October 10, 2006
    Assignee: LG Electronics Inc.
    Inventor: Sung Uk Park
  • Patent number: 7117290
    Abstract: A processor comprises a cache, a first TLB, and a tag circuit. The cache comprises a data memory storing a plurality of cache lines and a tag memory storing a plurality of tags. Each of the tags corresponds to a respective one of the cache lines. The first TLB stores a plurality of page portions of virtual addresses identifying a plurality of virtual pages for which physical address translations are stored in the first TLB. The tag circuit is configured to identify one or more of the plurality of cache lines that are stored in the cache and are within the plurality of virtual pages. In response to a hit by a first virtual address in the first TLB and a hit by the first virtual address in the tag circuit, the tag circuit is configured to prevent a read of the tag memory in the cache.
    Type: Grant
    Filed: September 3, 2003
    Date of Patent: October 3, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gene W. Shen, S. Craig Nelson
  • Patent number: 7089397
    Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: August 8, 2006
    Assignee: Transmeta Corporation
    Inventors: H. Peter Anvin, Guillermo J. Rozas, Alexander Klaiber, John P. Banning
  • Patent number: 7089376
    Abstract: In a system having a plurality of snooping masters coupled to a Bus Macro, a snoop filtering device and method are provided in at least one of the plurality of snooping masters. The snoop filtering device and method parse a snoop request issued by one of the plurality of snooping masters and return an Immediate Response if parsing indicates the requested data cannot possibly be contained in a responding snooping master. If parsing indicates otherwise the at least one plurality of snoop masters searches its resources and returns the requested data if marked updated.
    Type: Grant
    Filed: May 21, 2003
    Date of Patent: August 8, 2006
    Assignee: International Business Machines Corporation
    Inventors: James N. Dieffenderfer, Bernard C. Drerup, Jaya P. Ganasan, Richard G. Hofmann, Thomas A. Sartorius, Thomas P. Speier, Barry J. Wolford
  • Patent number: 7085885
    Abstract: A cache memory that notifies other functional blocks in the microprocessor that a miss has occurred potentially N clocks sooner than the conventional method, where N is the number of stages in the cache pipeline. The multiple pass cache receives a plurality of busy indicators from resources needed to complete various transaction types. The cache distinguishes between a first set of resources needed to complete a transaction when its cache line address hits in the cache and a second set of resources needed to complete the transaction type when the address misses in the cache. If none of the second set of resources for the type of the transaction type is busy on a miss, then the cache immediately signals a miss rather than retrying the transaction by sending it back through the cache pipeline and causing N additional clock cycles to occur before signaling the miss.
    Type: Grant
    Filed: October 7, 2002
    Date of Patent: August 1, 2006
    Inventor: James N. Hardage, Jr.
  • Patent number: 7086053
    Abstract: Methods and apparatus for enabling inconsistent or unsafe threads to efficiently reach a consistent or safe state when a requesting thread requests a consistent state are disclosed. According to one aspect of the present invention, a method for requesting a consistent state in a multi-threaded computing environment using a first thread includes acquiring a consistent state lock using the first thread, and identifying substantially all threads in the environment that are inconsistent. The state of the inconsistent threads is altered to a consistent state, and the first thread is notified when the states of the previously inconsistent threads have been altered to be consistent. Once the first thread is notified, the first thread releases the consistent state lock. In one embodiment, the method also includes performing a garbage collection after releasing the consistent state lock using the first thread.
    Type: Grant
    Filed: April 17, 2001
    Date of Patent: August 1, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Dean R. E. Long, Nedim Fresko
  • Patent number: 7080213
    Abstract: A system and method for reducing shared memory write overhead in multiprocessor system. In one embodiment, a multiprocessing system implements a method comprising storing an indication of obtained store permission corresponding to a particular address in a store buffer. The indication may be, for example, the address of a cache line for which a write permission has been obtained. Obtaining the write permission may include locking and modifying an MTAG or other coherence state entry. The method further comprises determining whether the indication of obtained store permission corresponds to an address of a write operation to be performed. In response to the indication corresponding to the address of the write operation to be performed, the write operation is performed without invoking corresponding global coherence operations.
    Type: Grant
    Filed: December 16, 2002
    Date of Patent: July 18, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Oskar Grenholm, Zoran Radovic, Erik E. Hagersten
  • Patent number: 7076609
    Abstract: Cache sharing for a chip multiprocessor. In one embodiment, a disclosed apparatus includes multiple processor cores, each having an associated cache. A control mechanism is provided to allow sharing between caches that are associated with individual processor cores.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: July 11, 2006
    Assignee: Intel Corporation
    Inventors: Vivek Garg, Jagannath Keshava
  • Patent number: 7072986
    Abstract: A management display method according to each type of interfaces and devices is provided in an environment where host computers are interconnected with storage apparatuses through plural types of interfaces. The management host computer includes a display apparatus and allows a user to select a physical view for displaying a physical topology between each host and storage subsystems or a logical view for displaying a connecting relation between the devices of the storage subsystem and each host computer. The management host computer operates to collect the information of the Fibre channel interface and the Ethernet interface and the information about an access limitation of each device, included in each host computer and storage subsystem and then to display the connecting relation according to the display method (view) selected by the user, based on the collected information.
    Type: Grant
    Filed: February 8, 2002
    Date of Patent: July 4, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Manabu Kitamura, Kenichi Takamoto
  • Patent number: 7073026
    Abstract: A microprocessor including a level two cache memory which supports multiple accesses per cycle. The microprocessor includes an execution unit coupled to a cache memory subsystem which includes a cache memory coupled to a plurality of buses. The cache memory includes a plurality of independently accessible storage blocks. The buses may be coupled to convey a plurality of cache access requests to each of the storage blocks. In response to the plurality of cache access requests being conveyed on the plurality of cache buses, different ones of the storage blocks are concurrently accessible.
    Type: Grant
    Filed: November 26, 2002
    Date of Patent: July 4, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Mitchell Alsup
  • Patent number: 7069380
    Abstract: In order to manage the various types of attribute information within the storage-device system, the storage-device system includes the following databases within a file-access controlling memory: a database for managing index information for managing contents of the files, and an index retrieval program, a database for managing the attribute information on the files, and a database for managing storage positions of blocks configuring a file. When the storage-device system receives an access request to a file, the utilization of these databases allows the storage-device system to make the access to the access-target file.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: June 27, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Junji Ogawa, Naoto Matsunami, Masaaki Iwasaki, Koji Sonoda, Kenichi Tsukiji
  • Patent number: 7069387
    Abstract: A method for optimizing a cache memory used for multitexturing in a graphics system is implemented. The graphics system comprises a texture memory, which stores texture data comprised in texture maps, coupled to a texture cache memory. Active texture maps for an individual primitive, for example a triangle, are identified, and the texture cache memory is divided into partitions. In one embodiment, the number of texture cache memory partitions equals the number of active texture maps. Each texture cache memory partition corresponds to a respective single active texture map, and is operated as a direct mapped cache for its corresponding respective single active texture map. In one embodiment, each texture cache memory partition is further operated as an associative cache for the texture data comprised in the partition's corresponding respective single active texture map. The cache memory is dynamically re-configured for each primitive.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: June 27, 2006
    Assignee: Sun Microsystems, Inc.
    Inventor: Brian D. Emberling
  • Patent number: 7058852
    Abstract: The present invention discloses a method and system for providing defect management of a bulk data storage media wherein logical addresses of media data blocks are continuously slipped to omit all media data blocks determined to be defective at the time of an initial media format. Thereafter, selectable parameters are utilized to define a logical zone including both a user data area and corresponding replacement data area on the media such that proper selection of the parameters provides defect management optimized for a particular use of the media.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: June 6, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: J. Robert Sims, III, Kyle Way
  • Patent number: 7058784
    Abstract: A method for managing the access procedure for large block flash memory by employing a page cache block, so as to reduce the occurrence of swap operation is proposed. At least one block of the nonvolatile memory is used as a page cache block. When a host requests to write a data to storage device, the last page of the data is written into one available page of the page cache block by the controller. A block structure is defined in the controller having a data block for storing original data, a writing block for temporary data storage in the access operation, and a page cache block for storing the last one page data to be written.
    Type: Grant
    Filed: July 4, 2003
    Date of Patent: June 6, 2006
    Assignee: Solid State System Co., Ltd.
    Inventor: Chih-Hung Wang
  • Patent number: 7047364
    Abstract: Management of accessing data in a main memory and a cache memory includes, for each unit of data transferred from a first processor to a second processor, filling a cache set of the cache memory with data associated with addresses in the main memory that correspond to the cache set after the first processor writes a unit of data to addresses that correspond to the cache set. For each unit of data transferred from the second processor to the first processor, filling the cache set with data associated with addresses in the main memory that correspond to the cache set before the first processor reads a unit of data written by the second processor to addresses that correspond to the cache set. The data used to fill the cache set are associated with addresses that are different from the addresses associated with the unit of data.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: May 16, 2006
    Assignee: Intel Corporation
    Inventor: Mehdi M. Hassane
  • Patent number: 7039751
    Abstract: A plurality of cache addressing functions are stored in main memory. A processor which executes a program selects one of the stored cache addressing functions for use in a caching operation during execution of a program by the processor.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: May 2, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Ole Bentz
  • Patent number: 7039761
    Abstract: A system for performing caching procedures in an electronic network may include a user device that communicates with a server device in the electronic network for transmitting message information to a selected buddy device in the electronic network. A messaging application of the user device may temporarily store the message information into a cache device as a cached message until a successful transmission of the cached message to the buddy device becomes possible through the server device and over the electronic network.
    Type: Grant
    Filed: August 11, 2003
    Date of Patent: May 2, 2006
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Annie Wang, Steven Kennedy, Sho San Kou
  • Patent number: 7032067
    Abstract: This invention provides a system and method for implementing a middleware caching arrangement to minimize device contention, network performance and synchronization issues associated with enterprise security token usage. The invention comprises a token API mapped to a cache API. Logic associated with the token API preferentially retrieves information from a memory cache managed by the cache API. Mechanisms are included to periodically purge the memory cache of unused information.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: April 18, 2006
    Assignee: Activcard
    Inventor: Yves Massard
  • Patent number: 7032123
    Abstract: The present invention provides a method and apparatus for error recovery in a system. The apparatus comprises a directory cache adapted to store at least one entry and a control unit. The control unit is adapted to determine if at least one uncorrectable error exists in the directory cache and to place the directory cache offline in response to determining that the error is uncorrectable. The method comprises detecting an error in data stored in a storage device in the system, and determining if the detected error is correctable. The method further comprises making at least a portion of the storage device unavailable to one or more resources in the system in response to determining that the error is uncorrectable.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: April 18, 2006
    Assignee: Sun Microsystems, Inc.
    Inventors: Donald Kane, Daniel P. Drogichen
  • Patent number: 7027063
    Abstract: A method of storing a texel in a texel cache comprising reading a t coordinate of the texel, the t coordinate comprising a plurality of bits, reading a s coordinate of the texel, the s coordinate comprising a plurality of bits, forming an offset by concatenating bits of the t coordinate with bits of the s coordinate and forming an index by concatenating bits of the t coordinate with bits of the s coordinate and at least one bit of a level of detail is discussed.
    Type: Grant
    Filed: May 6, 2005
    Date of Patent: April 11, 2006
    Assignee: NVIDIA Corporation
    Inventor: Alexander L. Minkin
  • Patent number: 7024452
    Abstract: A method and system for file-system based caching can be used to improve efficiency and security at network sites. In one set of embodiments, the delivery of content and storing content component(s) formed during generation of the content may be performed by different software components. Content that changes at a relatively high frequency or is likely to be regenerated between requests may not have some or all of its corresponding files cached. Additionally, extra white space may be removed before storing to reduce the file size. File mapping may be performed to ensure that a directory within the cache will have an optimal number of files. Security at the network site may be increased by using an internally generated filename that is not used or seen by the client computer. Many variations may be used is achieving any one or more of the advantages described herein.
    Type: Grant
    Filed: July 15, 2002
    Date of Patent: April 4, 2006
    Assignee: Vignette Corporation
    Inventors: Conleth S. O'Connell, Jr., Maxwell J. Berenson, N. Issac Rajkumar
  • Patent number: 7023741
    Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: April 4, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
  • Patent number: 7007031
    Abstract: System and method of data unit management in a decoding system employing a decoding pipeline. Each incoming data unit is assigned a memory element and is stored in the assigned memory element. Each decoding module gets the data to be operated on, as well as the control data, for a given data unit from the assigned memory element. Each decoding module, after performing its decoding operations on the data unit, deposits the newly processed data back into the same memory element. In one embodiment, the assigned memory locations comprise a header portion for holding the control data corresponding to the data unit and a data portion for holding the substantive data of the data unit. The header information is written to the header portion of the assigned memory element once and accessed by the various decoding modules throughout the decoding pipeline as needed. The data portion of memory is used/shared by multiple decoding modules.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: February 28, 2006
    Assignee: Broadcom Corporation
    Inventors: Alexander G. MacInnis, Jose′ R. Alvarez, Sheng Zhong, Xiaodong Xie, Vivian Hsiun
  • Patent number: 6990551
    Abstract: A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer to form an adjusted-linear address. The page directory base pointer is unique to a process and combining it with a portion of the linear address produces an adjusted-linear address that provides a high probability of no aliasing. A portion of the adjusted-linear address is used to search an adjusted-linear-addressed cache memory for a data block specified by the linear address. If the data block does not reside in the adjusted-linear-addressed cache memory, then a replacement policy selects one of the cache lines in the adjusted-linear-addressed cache memory and replaces the data block of the selected cache line with a data block located at a physical address produced from translating the linear address.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: January 24, 2006
    Assignee: Intel Corporation
    Inventors: Herbert H. J. Hum, Stephan J. Jourdan, Per H. Hammarlund
  • Patent number: 6977657
    Abstract: A data processing system has main memory and one or more caches. Data from main memory is cached while mitigating the effects of address pattern dependency. Main memory physical addresses are translated into main memory virtual address under the control of an operating system. The translation occurs on a page-by-page basis such that some of the virtual address bits are the same as some of the physical address bits. A portion of the address bits that are the same are selected and cache offset values are generated from the selected portion. Data is written to the cache at offset positions derived from the cache offset values.
    Type: Grant
    Filed: August 8, 2002
    Date of Patent: December 20, 2005
    Assignee: Autodesk Canada Co.
    Inventor: Benoit Belley
  • Patent number: 6976117
    Abstract: A processor system having cache array for storing virtual tag information and physical tag information and corresponding comparators associated with the array to determine cache-hits. Information from the virtual tag array and the physical tag array may be accessed together.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: December 13, 2005
    Assignee: Intel Corporation
    Inventors: Lawrence T. Clark, Dan W. Patterson, Stephen J. Strazdus