Addressing Cache Memories Patents (Class 711/3)
  • Patent number: 7451261
    Abstract: Embodiments of the invention improve the cache hit ratio of read data. A hard disk drive (HDD) according to an embodiment of the present invention determines whether the read buffer should be used in its entirety or the partial continuous space should be used to read read-data from the magnetic disk. When the HDD determines use of the partial continuous space, the HDD specifies the sub-buffer which is a continuous space wherein the leading-end position and the trailing-end position are coupled to each other, and executes data writing to the sub-buffer in parallel with data reading from the sub-buffer and transmission thereof to the host. The sub-buffer capacity coincides with the data length of the back data.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: November 11, 2008
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Takahiro Saito, Takayuki Yamaguchi, Atsushi Kanamaru, Hiromi Kobayashi
  • Patent number: 7451248
    Abstract: A method and apparatus for invalidating cache lines during direct memory access (DMA) write operations are disclosed. Initially, a multi-cache line DMA request is issued by a peripheral device. The multi-cache line DMA request is snooped by a cache memory. A determination is then made as to whether or not the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed. In response to a determination that the cache memory includes a copy of data stored in the system memory locations to which the multi-cache line DMA request are directed, multiple cache lines within the cache memory are consecutively invalidated.
    Type: Grant
    Filed: February 9, 2005
    Date of Patent: November 11, 2008
    Assignee: International Business Machines Corporation
    Inventors: George W. Daly, Jr., James S. Fields, Jr.
  • Patent number: 7451271
    Abstract: A virtually indexed, physically-tagged cache is combined with one or more virtually-tagged fill-buffers.
    Type: Grant
    Filed: April 5, 2004
    Date of Patent: November 11, 2008
    Assignee: Marvell International Ltd.
    Inventor: Dennis M. O'Connor
  • Patent number: 7444457
    Abstract: Systems and methods of processing addresses provide for receiving a full linear address of an instruction and reducing a size of the full linear address to obtain a reduced linear address. A data block can be retrieved from a data array if the reduced linear address corresponds to a tag in a tag array, where the tag array is associated with the data array. The reduced linear address enables the tag array to either be smaller in size or achieve enhanced performance. The data array may be a prediction array of a branch predictor or a cache array of a cache.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: October 28, 2008
    Assignee: Intel Corporation
    Inventors: Stephan J. Jourdan, Chris E. Yunker, Pierre Michaud
  • Publication number: 20080263257
    Abstract: A dual-mode prefetch mechanism for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags for identifying the data stored in the data array; a set of checkpoint tags for storing data identification; a cache controller including prefetch logic, the prefetch logic including a checkpoint prefetch controller and a checkpoint prefetch operator.
    Type: Application
    Filed: April 17, 2007
    Publication date: October 23, 2008
    Applicant: International Business Machines Corporation
    Inventors: Harold Wade Cain III, Jong-Deok Choi
  • Patent number: 7441074
    Abstract: Methods and apparatus are disclosed for distributing entries among lookup units and selectively enabling less than all of the lookup units when performing a lookup operation. Each of the lookup units is assigned a subset of the possible values of the entries and is programmed with the corresponding entries. In performing a lookup operation on a lookup word, only the lookup units possibly containing a matching entry are enabled which saves power and dissipates less heat. A lookup operation is then performed in the enabled lookup units to generate the lookup result. A lookup unit may correspond to an associative memory device, an associative memory bank, sets of entries within one or more associative memory devices or banks, a lookup control and a memory device, and/or any other lookup mechanism. In one implementation, the partitioning of elements is based on a Patricia tree representation of the possible entries.
    Type: Grant
    Filed: August 10, 2002
    Date of Patent: October 21, 2008
    Assignee: Cisco Technology, Inc.
    Inventors: Rina Panigrahy, Samar Sharma
  • Publication number: 20080244152
    Abstract: A specification of a configurable processor is generated by generating (1) specifications of first and second stream memory interfaces to be operable to access data in accordance with first and second stream descriptors, and (2) a specification of an interim data storage device (buffer) to be accessed by the first and second stream memory interfaces and to be operable to receive data from a first computational module via the first stream memory interface and to transfer data to a second computational module via the second stream memory interface. The specifications are output and may be used to configure a configurable processor.
    Type: Application
    Filed: March 30, 2007
    Publication date: October 2, 2008
    Applicant: MOTOROLA, INC.
    Inventors: Sek M. Chai, Nikos Bellas, Malcolm R. Dwyer, Daniel A. Linzmeier
  • Publication number: 20080244153
    Abstract: Cache systems, computer systems and methods thereof are disclosed. A buffer buffers first data from a main memory prior to writing to the cache memory. In response to a cache hit, a word from the cache memory is read. In response to a cache miss, the first data is written from the buffer to the cache memory. When the cache hit occurs before all first data is written from the buffer to the cache memory, the reading is executed and the writing is paused.
    Type: Application
    Filed: April 2, 2007
    Publication date: October 2, 2008
    Applicant: MEDIATEK INC.
    Inventor: Tauli Huang
  • Publication number: 20080222343
    Abstract: A method is provided for pre-fetching data into a cache memory. A first cache-line address of each of a number of data requests from at least one processor is stored. A second cache-line address of a next data request from the processor is compared to the first cache-line addresses. If the second cache-line address is adjacent to one of the first cache-line addresses, data associated with a third cache-line address adjacent to the second cache-line address is pre-fetched into the cache memory, if not already present in the cache memory.
    Type: Application
    Filed: March 8, 2007
    Publication date: September 11, 2008
    Inventors: Judson E. Veazey, Blaine D. Gaither
  • Patent number: 7424587
    Abstract: A method for writing data to a solid-state disk having a first portion of solid-state memory of a volatile nature and a second portion of solid-state memory of a non-volatile nature, and a controller for controlling data operations to the memory includes acts of (a) receiving at the controller, write data for writing to an assigned address in non-volatile memory; (b) determining at the controller if there is existing data associated with a write address in volatile memory, the write address referencing the assigned address in volatile memory; and (c) upon finding data in volatile memory held for the assigned write address or not at act (b), writing the data into the volatile memory at a predestinated write address in volatile memory.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: September 9, 2008
    Assignee: Dataram, Inc.
    Inventors: Jason Caulkins, Michael Richard Beyer
  • Patent number: 7418583
    Abstract: A detector detects at least one kind of dependence in address between instructions executed by at least a processor, the detector being adopted to detect a possibility of presence of the at least one kind of dependence, wherein if the at least one kind of dependence is present in fact, then the detector detects a possibility of presence of the at least one kind of dependence, and if the at least one kind of dependence is not present in fact, then the detector may detect a pseudo presence of the at least one kind of dependence. The detector has an execution history storing unit with a plurality of entries and an address converter for converting an address of a memory access instruction into an entry number, where different addresses may be converted into entry numbers that are the same.
    Type: Grant
    Filed: May 11, 2005
    Date of Patent: August 26, 2008
    Assignee: NEC Corporation
    Inventors: Atsufumi Shibayama, Satoshi Matsushita, Sunao Torii, Naoki Nishi
  • Patent number: 7412569
    Abstract: Briefly, a system and a method to efficiently track changes in memory or storage areas, for example, in cache memories of computers and electronic systems. A method in accordance with an exemplary embodiment of the invention includes, for example, updating a tracking list with an address and/or a corresponding address to be updated of a changed entry in an intermediate memory. A system in accordance with an exemplary embodiment of the invention may include, for example, a tracking unit to track the locations of potential data discrepancies between a reference memory and an intermediate memory.
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Alon Naveh, Abraham Mendelson
  • Patent number: 7412568
    Abstract: Methods, apparatus, and systems are provided for caching. A caching process is automatically modified in response to update eligibility and an interference relation for a plurality of threads. Data is read into a cache, and a reference to the data is provided to a plurality of threads. An initial thread receives a signal from a last thread once the last thread has the reference to the data. The initial thread, in response to the signal, modifies the data and updates changes to the data within the cache and then sends another signal to a next thread, indicating that the next thread may now perform a volatile operation on the data within the cache.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: August 12, 2008
    Assignee: Intel Corporation
    Inventors: Jinquan Dai, Long Li
  • Patent number: 7406566
    Abstract: A cache architecture to increase communication throughput and reduce stalls due to coherence protocol dependencies, while reducing power within an integrated circuit. More particularly, embodiments of the invention include a plurality of cache agents that each communication with the same protocol agent, which may or may not be integrated within any one of the cache agents. Embodiments of the invention also include protocol agents capable of storing multiple sets of data from different sets of cache agents within the same clock cycle.
    Type: Grant
    Filed: June 3, 2005
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventor: Benjamin Tsien
  • Patent number: 7406569
    Abstract: Typical cache architecture provides a single cache way prediction memory for use in predicting a cache way for both sequential and non-sequential instructions contained within a program stream. Unfortunately, one of the drawbacks of the prior art cache way prediction scheme lies in its efficiency when dealing with instructions that vary the PC in a non-sequential manner, such as branch instructions including jump instructions. To facilitate caching of non-sequential instructions an additional cache way prediction memory is provided to deal with the non-sequential instructions. Thus during program execution a decision circuit determines whether to use a sequential cache way prediction array or a non sequential cache way prediction array in dependence upon the type of instruction. Advantageously the improved cache way prediction scheme provides an increased cache hit percentage when used with non-sequential instructions.
    Type: Grant
    Filed: August 12, 2002
    Date of Patent: July 29, 2008
    Assignee: NXP B.V.
    Inventor: Jan-Willem van de Waerdt
  • Patent number: 7404044
    Abstract: A system and method are provided for increasing the number of processors on a single integrated circuit to a number that is larger than would typically be possible to coordinate on a single bus. In an embodiment of the present invention a two-level memory coherency scheme is implemented for use by multiple processors operably coupled to multiple buses in the same integrated circuit. A control device, such as node controller, is used to control traffic between the two coherency levels. In an embodiment of the invention the first level of coherency is implemented using a “snoopy” protocol and the second level of coherency is a directory-based coherency scheme.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: July 22, 2008
    Assignee: Broadcom Corporation
    Inventor: Laurent Moll
  • Patent number: 7401184
    Abstract: In general, in one aspect, the disclosure describes a method that includes generating multiple cache line accesses to multiple respective cache lines of a cache as required to satisfy an access to data specified by a single instruction of a processing element specifying an access to data.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: July 15, 2008
    Assignee: Intel Corporation
    Inventors: Mason B. Cabot, Frank T. Hady, Mark B. Rosenbluth
  • Patent number: 7395380
    Abstract: A method and structure for snooping cache memories of several snooping masters connected to a bus macro, wherein each non-originating snooping master has cache memory, and wherein some, but less than all the cache memories, may have the data requested by an originating snooping master and wherein the needed data in a non-originating snooping master is marked as updated, and wherein a main memory having addresses for all data is connected to the bus macro. Only those non-originating snooping masters which may have the requested data are queried. All the non-originating snooping masters that have been queried reply. If a non-originating snooping master has the requested data marked as updated, that non-originating snooping master returns the updated data to the originating snooping master and possibly to the main memory. If none of the non-originating snooping masters has the requested data marked as updated, then the requested data is read from main memory.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: July 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: James N. Dieffenderfer, Bernard C. Drerup, Jaya P. Ganasan, Richard G. Hofmann, Thomas A. Sartorius, Thomas P. Speier, Barry J. Wolford
  • Patent number: 7389385
    Abstract: Methods and apparatus to insert prefetch instructions based on garbage collector analysis and compiler analysis are disclosed. In an example method, one or more batches of samples associated with cache misses from a performance monitoring unit in a processor system are received. One or more samples from the one or more batches of samples based on delinquent information are selected. A performance impact indicator associated with the one or more samples is generated. Based on the performance indicator, at least one of a garbage collector analysis and a compiler analysis is initiated to identify one or more delinquent paths. Based on the at least one of the garbage collector analysis and the compiler analysis, one or more prefetch points to insert prefetch instructions are identified.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: June 17, 2008
    Assignee: Intel Corporation
    Inventors: Mauricio J. Serrano, Sreenivas Subramoney, Richard L. Hudson, Ali-Reza Adl-Tabatabai
  • Patent number: 7386596
    Abstract: The present invention provides improved techniques for managing storage resources, such as disk drives, I/O ports, and the like in a network based storage system according to a user position within the network. Embodiments according to the present invention can provide a relatively high performance storage access environment for the mobile users moving around a wide area. For example, in one applicable environment, there are several data centers in the wide area, and each data center has a local storage system that is connected to the other storage systems through a network. Copies of a user's volume can be made in some of the storage systems. A remote copy function is utilized for making real time copies of the user's volume.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: June 10, 2008
    Assignee: Fuji Xerox, Co., Ltd.
    Inventors: Akira Yamamoto, Naoko Iwami
  • Patent number: 7380047
    Abstract: A memory system and method includes a cache having a filtered portion and an unfiltered portion. The unfiltered portion is divided into block sized components, and the filtered portion is divided into sub-block sized components. Blocks evicted from the unfiltered portion have selected sub-blocks thereof cached in the filtered portion for servicing requests.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: May 27, 2008
    Assignee: International Business Machines Corporation
    Inventors: Philip George Emma, Allan Mark Hartstein, Thomas Roberts Puzak, Moinuddin Khalil Ahmed Qureshi
  • Patent number: 7380098
    Abstract: A method for caching attribute data for matching attributes with physical addresses. The method includes storing a plurality of attribute entries in a memory, wherein the memory is configured to provide at least one attribute entry when accessed with a physical address, and wherein the attribute entry provided describes characteristics of the physical address.
    Type: Grant
    Filed: June 16, 2006
    Date of Patent: May 27, 2008
    Assignee: TRANSMETA Corporation
    Inventors: H. Peter Anvin, Guillermo J. Rozas, Alexander Klaiber, John P. Banning
  • Patent number: 7373466
    Abstract: A method and apparatus for filtering memory probe activity for writes in a distributed shared memory computer. In one embodiment, the method may include assigning an uncached directory state to a cache data block in response to evicting the cache data block. In another embodiment, the method may include assigning a remote directory state to a cache data block in response to evicting the cache data block and storing it in a remote cache. In a third embodiment, the method may include assigning a pairwise-shared directory state in response to a second processor node initiating a load operation to a cache data block in a modified cache state in a first processor node. In a fourth embodiment, the method may include assigning a migratory directory state in response to a processor node initiating a store operation to a cache data block in a pairwise-shared cache state.
    Type: Grant
    Filed: April 7, 2004
    Date of Patent: May 13, 2008
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Patrick N. Conway
  • Patent number: 7366801
    Abstract: Disclosed is a technique for buffering work requests. It is determined that a work request is about to be placed into an in-memory structure. When the in-memory structure is not capable of storing the work request, a work request ordering identifier for the work request is stored into an overflow structure. When the in-memory structure is capable of storing the work request, a recovery stub is generated for the work request ordering identifier, and the recovery stub is stored into the in-memory structure.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: April 29, 2008
    Assignee: International Business Machines Corporation
    Inventors: Ramani Mathrubutham, Adwait Sathye, Chendong Zou
  • Patent number: 7366819
    Abstract: A cache unit multiple memory towers, which can be independently addressed. Cache lines are divided among multiple towers. Furthermore, physical lines of the memory towers are shared by multiple cache lines. Because each tower can be addressed independently and the cache lines are split among the towers, unaligned cache access can be performed. Furthermore, power can be conserved because not all the memory towers of the cache unit needs to be activated during some memory access operations.
    Type: Grant
    Filed: February 11, 2004
    Date of Patent: April 29, 2008
    Assignee: Infineon Technologies AG
    Inventor: Klaus J. Oberlaender
  • Patent number: 7366820
    Abstract: A circuit for driving and controlling a second cache that is incorporated in a processor and comprises a plurality of RAM. The circuit comprises a second-cache control unit 1A and a chip-enable control unit 61. The second-cache control unit 1A receives an access request for an access to the second cache and designates some of the RAMs, which need not operate, in accordance with the type or address of the access request, or both. The chip-enable control unit 61 outputs an intra-macro stop-instructing signal to the RAMs that have been designated by the second-cache control unit 1A.
    Type: Grant
    Filed: November 30, 2004
    Date of Patent: April 29, 2008
    Assignee: Fujitsu Limited
    Inventors: Mie Tonosaki, Tomoyuki Okawa
  • Patent number: 7355601
    Abstract: A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: April 8, 2008
    Assignees: International Business Machines Corporation, Microsoft Corporation
    Inventors: Jeffrey A. Andrews, Nicholas R. Baker, J. Andrew Goossen, Russell D. Hoover, Eric O. Mejdrich, Sandra S. Woodward
  • Patent number: 7356627
    Abstract: A data handling device capable of operating in a system in which two or more devices are connected by a data bus for the transmission of communications therebetween, the data bus having two or more data lines and the device having: two or more data bus connectors, each for connection to a respective data line of the data bus; an identity acquisition unit capable of functioning in a first mode of operation of the device to receive data transmitted over the data bus and in response to the order in which the bits of one or more data words of a predetermined form are received on the data bus connectors during the first mode of operation determine an identity for the device and store the identity in an identity store of the device; and a data handling unit capable of functioning in a second mode of operation of the device to handle communications transmitted over the bus and that specify the identity stored in the data store as a destination.
    Type: Grant
    Filed: July 10, 2003
    Date of Patent: April 8, 2008
    Assignee: Nokia Corporation
    Inventors: Anssi Haverinen, Pekka Karppinen, Antti Latva-aho, Neil Webb
  • Publication number: 20080082720
    Abstract: A data processing system having debugging circuitry and a method for operating the data processing system is provided. In the system, a processor has a cache memory and is coupled to a system bus. An instruction is received which indicates an effective address. The instruction is executed and it is determined if the effective address results in a hit or a miss in the cache. If the effective address results in a hit, data associated with the effective address is provided from the cache to the system bus without modifying a state of the cache. The instruction allows real-time debugging circuits to be able to view the current value of one or more variables in memory that may be hidden from access due to cache hierarchy without modifying the value or impacting the current state of the cache.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Inventor: William C. Moyer
  • Publication number: 20080082721
    Abstract: A virtual hint based data cache way prediction scheme, and applications thereof. In an embodiment, a processor retrieves data from a data cache based on a virtual hint value or an alias way prediction value and forwards the data to dependent instructions before a physical address for the data is available. After the physical address is available, the physical address is compared to a physical address tag value for the forwarded data to verify that the forwarded data is the correct data. If the forwarded data is the correct data, a hit signal is generated. If the forwarded data is not the correct data, a miss signal is generated. Any instructions that operate on incorrect data are invalidated and/or replayed.
    Type: Application
    Filed: October 11, 2006
    Publication date: April 3, 2008
    Applicant: MIPS Technologies, Inc.
    Inventors: Meng-Bing Yu, Era K. Nangia, Michael Ni, Vidya Rajagopalan
  • Patent number: 7353326
    Abstract: A flash memory device comprises a non-volatile memory core operatively connected to first and second buffer memories through a page buffer. The device further comprises a first register adapted to receive command and address information from a host system, a copy circuit adapted to copy the command and address information from the first register to a second register within a control logic circuit. The device alternately transfers information to the first and second buffer memories during a cache read operation comprising a plurality of data read operations.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: April 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Duk Cho, Young-Joon Choi, Tae-Gyun Kim
  • Patent number: 7353221
    Abstract: The invention relates to a method for the automatic retrieval of engineering data from installations. The engineering and runtime objects are described by a uniform object model. This allows the correspondence between engineering objects and runtime objects to be determined at object level and no information is lost as a result of the mapping. In addition, a direct communication between engineering and runtime objects can take place, which can be utilized when the method is carried out.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: April 1, 2008
    Assignee: Siemens Aktiengesellschaft
    Inventors: Norbert Becker, Georg Biehler, Matthias Diezel, Albrecht Donner, Dieter Eckardt, Manfred Krämer, Dirk Langkafel, Ralf Leins, Ronald Lange, Karsten Schneider, Helmut Windl
  • Patent number: 7350016
    Abstract: A high speed DRAM cache architecture. One disclosed embodiment includes a multiplexed bus interface to interface with a multiplexed bus. A cache control circuit drives a row address portion of an address on the multiplexed bus interface and a command to open a memory page containing data for a plurality of ways. The cache control circuit subsequently drives a column address including at least a way indicator to the multiplexed bus interface.
    Type: Grant
    Filed: January 10, 2006
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventors: Kuljit S. Bains, Herbert Hum, John Halbert
  • Patent number: 7349942
    Abstract: A file-mapping method and system can better manage the number of items (i.e., files, subdirectories, or a combination of them) within any single directory within a storage medium. The method and system can be used to limit the number of items within the directory, direct content and content components to different directories, and provide an internally recognizable name for the filename. When searching the storage medium, time is not wasted searching what appears to be a seemingly endless list of filenames or subdirectory names within any single directory. A client computer can have requests for content fulfilled quicker, and the network site can reduce the load on hardware or software components. While the method and system can be used for nearly any storage media, the method and system are well suited for cache memories used with web servers.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: March 25, 2008
    Assignee: Vignette Corporation
    Inventors: Conleth S. O'Connell, Jr., Eric R. White, N. Isaac Rajkumar
  • Publication number: 20080065809
    Abstract: Process, cache memory, computer product and system for loading data associated with a requested address in a software cache. The process includes loading address tags associated with a set in a cache directory using a Single Instruction Multiple Data (SIMD) operation, determining a position of the requested address in the set using a SIMD comparison, and determining an actual data value associated with the position of the requested address in the set.
    Type: Application
    Filed: September 7, 2006
    Publication date: March 13, 2008
    Inventor: Alexandre E. Eichenberger
  • Publication number: 20080065810
    Abstract: A system and method for recording trace data while conserving cache resources includes generating trace data and creating a cache line containing the trace data. The cache line is assigned a tag which corresponds to an intermediate address designated for processing the trace data. The cache line also contains embedded therein an actual address in memory for storing the trace data, which may include either a real address or a virtual address. The cache line may be received at the intermediate address and parsed to read the actual address. The trace data may then be written to a location in memory corresponding to the actual address. By routing trace data through a designated intermediate address, CPU cache may be conserved for other more important or more frequently accessed data.
    Type: Application
    Filed: September 8, 2006
    Publication date: March 13, 2008
    Inventors: Carol Spanel, Andrew Dale Walls
  • Patent number: 7340562
    Abstract: A distributed data cache includes a number of cache memory units or register files each having a number of cache lines. Data buses are connected with the cache memory units. Each data bus is connected with a different cache line from each cache memory unit. A number of data address generators are connected with a memory unit and the data buses. The data address generators retrieve data values from the memory unit and communicate the data values to the data buses without latency. The data address generators are adapted to simultaneously communicate each of the data values to a different data bus without latency. The cache memory units are adapted to simultaneously load data values from the data buses, with each data value loaded into a different cache line without latency.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: March 4, 2008
    Assignee: NVIDIA Corporation
    Inventor: Amit Ramchandran
  • Patent number: 7334088
    Abstract: A computer system and a method for enhancing the cache prefetch behavior. A computer system including a processor, a main memory, a prefetch controller, a cache memory, a prefetch buffer, and a main memory, wherein each page in the main memory has associated with it a tag, which is used for controling the prefetching of a variable subset of lines from this page as well as lines from at least one other page. And, coupled to the processor is a prefetch controller, wherein the prefetch controller responds to the processor determining a fault (or miss) occurred to a line of data by fetching a corresponding line of data with the corresponding tag, with the corresponding tag to be stored in the prefetch buffer, and sending the corresponding line of data to the cache memory.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: February 19, 2008
    Assignee: International Business Machines Corporation
    Inventor: Peter Franaszek
  • Patent number: 7330961
    Abstract: A cache control method controls data sharing conditions in a processor system having multi-level caches that are in an inclusion relationship. The cache control method indexes an upper level cache by a real address and indexes a lower level cache by a virtual address, and prevents a real address that is referred by a plurality of different virtual addresses from being registered a plurality of times within the same cache. A plurality of virtual addresses are registrable within the upper level cache, so as to relax the data sharing conditions.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: February 12, 2008
    Assignee: Fujitsu Limited
    Inventors: Hideki Sakata, Tatsumi Nakada, Eiki Ito, Akira Nodomi
  • Publication number: 20080028152
    Abstract: Caching techniques for storing instructions, constant values, and other types of data for multiple software programs are described. A cache provides storage for multiple programs and is partitioned into multiple tiles. Each tile is assignable to one program. Each program may be assigned any number of tiles based on the program's cache usage, the available tiles, and/or other factors. A cache controller identifies the tiles assigned to the programs and generates cache addresses for accessing the cache. The cache may be partitioned into physical tiles. The cache controller may assign logical tiles to the programs and may map the logical tiles to the physical tiles within the cache. The use of logical and physical tiles may simplify assignment and management of the tiles.
    Type: Application
    Filed: July 25, 2006
    Publication date: January 31, 2008
    Inventors: Yun Du, Guofang Jiao, Chun Yu, De Dzwo Hsu
  • Patent number: 7318114
    Abstract: In one embodiment, a system includes a plurality of memory controllers each coupled between a processor and a respective memory. Each memory controller includes a plurality of decoders. Each decoder of a given memory controller may be independently configurable to match on a respective value of a subset of address bits such as the low-order cache line address bits, for example, received in a memory request. In one specific implementation, the number of decoders included on a given memory controller may correspond to the number of ways in which the memory is interleaved.
    Type: Grant
    Filed: October 29, 2004
    Date of Patent: January 8, 2008
    Assignee: Sun Microsystems, Inc.
    Inventor: Robert E. Cypher
  • Patent number: 7318076
    Abstract: A comprehensive Memory-Resident Database Management System architecture and implementation is disclosed where a) all data storage in database is in memory, b) all database management functionality is in memory except backup and recovery storage based on hard disk, c) all database objects including tables, views, triggers, procedures, functions . . . are in memory, d) all data security is at memory level, e) all data indexed, sorted and searched based on the selected search algorithms are in memory, f) all logging functionality to refresh in-between transactions reside in memory. Therefore, the processing speed of database query will take advantage of speed of RAM (Random Access Memory) without sacrifice any speed losing on Hard disk I/O. Not only the whole database is running in RAM, but also all or pre-selected database table columns are default to be indexed. All internal processing of database query is based on indexed columns.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: January 8, 2008
    Assignee: Intelitrac, Inc.
    Inventors: Tianlong Chen, Jonathan Vu
  • Patent number: 7313667
    Abstract: Fields of entries are mapped into new values with these mapped values combined into mapped entries for use in lookup operations typically for packet processing. One implementation identifies a list including multiple items each having a first field and a second field. The unique first and second fields of each item are respectively mapped to mapped first and second fields. A first associative memory is programmed with the unique first fields, and a first stage memory is programmed with the mapped first fields at corresponding locations. A second associative memory is programmed with the unique second fields, a second stage memory is programmed with the mapped second fields at corresponding locations. A second stage associative memory is then programmed, using the mapped first and second fields, with entries corresponding to one or more of the original multiple items.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: December 25, 2007
    Assignee: Cisco Technology, Inc.
    Inventors: Venkateshwar Rao Pullela, Dileep Kumar Devireddy, Shyamsundar Rao Pullela
  • Patent number: 7308536
    Abstract: A method for informing a processor of a selected order of transmission of data to the processor. The method comprises the steps of coupling system components via a data bus to the processor to effectuate data transfer, determining at the system component logic the order in which to transmit data to the processor, and issuing to the data bus a selected order bit concurrent with the data, wherein the selected order bit alerts the processor of the order and the data is transmitted in that order. In a preferred embodiment, the system component is the cache and the method may involve receiving at the cache a preference of ordering for a read address/request from the processor. The preference order logic of the cache controller or a preference order logic component evaluates the preference of ordering desired by comparing the processor preference with other preferences, including cache order preference.
    Type: Grant
    Filed: January 22, 2005
    Date of Patent: December 11, 2007
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Arimilli, Vicente Enrique Chung, Guy Lynn Guthrie, Jody Bern Joyner
  • Patent number: 7293139
    Abstract: To correctly generate LAs even when out-of-order occurs. In a disk array system according to the present invention, a control unit includes: a host input/output unit that exchanges data and a control signal with a host connected to a disk array system; a disk input/output unit that exchanges data and a control signal with a disk; a cache memory that temporarily stores the data during transfer between the host input/output unit and the disk input/output unit in units of segments that are each formed by a plurality of blocks having a predetermined size; an MPU that controls an operation of the control unit by executing a control program; and a cache controller that controls input/output of the data into/from the cache memory, and the host input/output unit transfers, to the cache controller, transfer information containing the guarantee codes of the first blocks of the segments relating to the data transfer.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: November 6, 2007
    Assignee: Hitachi, Ltd.
    Inventors: Akira Nishimoto, Naoto Matsunami, Masahiko Sato, Hidemi Baba
  • Patent number: 7290116
    Abstract: An apparatus and method for mapping memory addresses to reduce or avoid conflicting memory accesses in memory systems such as cache memories is described in connection with a multithreaded multiprocessor chip. A CMT processor reduces the probability of hot-spots in cache operations by hashing certain bits of a physical cache address to form a hashed cache address. By using exclusive OR functionality to hash the index bits, an efficient address transformation is achieved for indexing into an L2 cache memory.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: October 30, 2007
    Assignee: Sun Microsystems, Inc.
    Inventors: Greg F. Grohoski, Manish Shah, John D. Davis, Ashley Saulsbury, Cong Fu, Venkatesh Iyengar, Jenn-Yuan Tsai, Jeff Gibson
  • Publication number: 20070250666
    Abstract: An instruction cache system having a virtually tagged instruction cache which, from a software program perspective, operates as if it were a physically tagged instruction cache is disclosed. The instruction cache system also includes a means for address translation which is responsive to an address translation invalidate instruction and a control logic circuit. The control logic circuit is configured to invalidate an entry in the virtually tagged instruction cache in response to the address translation invalidate instruction.
    Type: Application
    Filed: August 31, 2006
    Publication date: October 25, 2007
    Inventors: Thomas Andrew Sartorius, Rodney Wayne Smith, Daren Eugene Streett
  • Patent number: 7269663
    Abstract: Apparatus and methods are provided for a Network Address Translation (NAT)-aware unified cache. According to one embodiment, multiple packet-processing applications distributed among one or more processors of a network device share one or more unified caches without requiring a cache synchronization protocol. When a packet is received at the network device, a first packet-processing application, such as NAT or another application that modifies part of the packet header upon which a cache lookup key is based, tags the packet with a cache lookup key based upon the original contents of the packet header. Then, other packet-processing applications attempting to access the cache entry from the unified cache subsequent to the tagging by the first packet-processing application use the tag (the cache lookup key generated by the first packet-processing application) rather than determining the cache lookup key based upon the current contents of the packet header.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: September 11, 2007
    Assignee: Intel Corporation
    Inventors: Niels Beier, Jacob M. Christensen, Kjeld B. Egevang
  • Patent number: 7269825
    Abstract: A method and system to provide improved operation of a software emulated platform through the use of a relative address translation cache containing a plurality of cache sets. Each address translation contained within the relative address translation cache contains a Base Descriptor Register selection, a relative address limit check, an access privilege check, generation of an absolute address and a real address, and breakpoint discovery.
    Type: Grant
    Filed: December 27, 2002
    Date of Patent: September 11, 2007
    Assignee: Unisys Corporation
    Inventor: James W. Adcock
  • Patent number: 7266651
    Abstract: A method for in-place interleaving and de-interleaving of a memory includes, in one embodiment, generating a new address corresponding to a new location in the memory by performing a bit-wise XOR operation on a number of bits of a first portion of a current address and a number of bits of a different portion of the current address. The current address corresponds to a current location in the memory. In addition, the method includes performing a data swap on data stored at the current location with data stored at the new location.
    Type: Grant
    Filed: September 7, 2004
    Date of Patent: September 4, 2007
    Assignee: Sun Microsystems, Inc.
    Inventor: Robert E. Cypher