For Multiple Memory Modules (e.g., Banks, Interleaved Memory) Patents (Class 711/5)
  • Patent number: 11070512
    Abstract: Embodiments for server port virtualization for guest logical unit number (LUN) masking in a host direct attach configuration using a storage adapter in a computing environment by a processor. An F switch port is simulated by an N storage port to enable either N-port virtualization (NPV) or N-port identification (ID) virtualization (NPIV) in the host direct attach configuration by directly attaching the N server port to the N storage port. A domain name system (DNS) operation is performed to cause each virtualized N-port ID to be mapped to fiber channel (FC) IDs in domain format of domain, area, port.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Min Fang, Qing Wang, Wei Yin, Jiang Yu
  • Patent number: 11062741
    Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jun Yoon, Hyun Seung Kim
  • Patent number: 11055003
    Abstract: Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator to increase the efficiency of the host and/or accelerator.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Honglin Sun, Richard C. Murphy, Glen E. Hush
  • Patent number: 11049530
    Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jun Yoon, Hyun Seung Kim
  • Patent number: 11023371
    Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10999568
    Abstract: In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus thereof for receiving a first command via a first interface that is addressable by a first address and receiving a second command via a second interface that is addressable by a second address.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 4, 2021
    Assignee: Nokia Technologies Oy
    Inventor: Mikko Muukki
  • Patent number: 10978115
    Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Daniel C. Skinner
  • Patent number: 10922221
    Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Edward C. McGlaughlin, Joseph M. Jeddeloh
  • Patent number: 10891225
    Abstract: An example method can include, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory. The deterministic garbage collection operation performed on the memory can result in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey L. McVay, Daniel J. Hubbard, Robert W. Strong, Michael B. Danielson, Jonathan Tanguy
  • Patent number: 10852921
    Abstract: A system and method facilitated on the Internet wherein users connected to the Internet via a system comprised of, a computer driven mobile GPS and/or AGPS enabled device, or, a stationary or portable computing device capable of connecting to the Internet, a corresponding mobile application and/or website portal with user account access, and an Application Programming Interface (API) for the user to interact with a user centric secure online database, engage with a method of constructing, saving, and sharing user defined specific geographic point location identity data sets or files exclusively that is not designed as a social interaction community involving tracking or proximity sensing of the user device. A system and method that is designed and intended for the purposes of constructing, saving, modifying, and sharing user defined geographic location identity data sets or files exclusively and absent requirements of engaging in actively tracking user devices.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: December 1, 2020
    Assignee: Latloc, LLC
    Inventor: Scott Kennedy
  • Patent number: 10854248
    Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Young Jun Yoon, Hyun Seung Kim
  • Patent number: 10839878
    Abstract: A processing device of a system receives a request to access a selected sector in a memory component. The selected sector is associated with a sector number. The processing device determines a virtual block corresponding to the selected sector. The virtual block is associated with a misalignment factor and a misalignment counter. The processing device determines if the misalignment counter satisfies a threshold criterion. In response to the misalignment counter satisfying the threshold criterion, the processing device generates an updated sector number by shifting the sector number by the misalignment factor and performs the access to the selected sector using the updated sector number. In response to the misalignment counter not satisfying the threshold criterion, the processing device updates the misalignment counter and performs the access to the selected sector using the sector number.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Luca Porzio, Marco Di Pasqua, Paolo Papa
  • Patent number: 10817201
    Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick, Frank T. Hady
  • Patent number: 10778552
    Abstract: A system or method for identifying latency contributors in a data storage network, that may include creating a historical workload fingerprint model for a data storage network from training data, along with monitoring and classifying a current sample data from the data storage network into a cluster, current workload fingerprint, and current workload type. The method may further include assigning a score to the current sample data based on the historical workload fingerprint model and correlating measured latency values from the current sample data to historically measured latency related factors to create a latency score chart that identifies factors causing latency in the data storage network for the current sample data.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: September 15, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Mayukh Dutta, Manoj Srivatsav, John J. Sengenberger
  • Patent number: 10761851
    Abstract: The present disclosure provides a memory apparatus comprising a first set of storage blocks operating as a set of read storage blocks in a first computation layer and as a set of write storage blocks in a second computation layer, where the second computation layer follows the first computation layer. The memory apparatus also comprises a second set of storage blocks operating as a set of write storage blocks in the first computation layer and as a set of read storage blocks in the second computation layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 1, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Liang Han, Xiaowei Jiang, Jian Chen
  • Patent number: 10763894
    Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Sudhir K. Satpathy, Sanu K. Mathew
  • Patent number: 10747452
    Abstract: A computer-implemented method of storing data on a storage device can receive an I/O request to read data from or write data to a data storage device. The data can be stored in special sectors as allocated sectors and regular sectors as a log-structured array (LSA). If the I/O request is to read data from the storage device, a determination can be made as to whether the data to be read is stored as a special sector, which can be read from the LSA, or as a regular sector, which can be can be read from the allocated sectors. If the I/O request is to write data to the storage device, a determination can be made as to whether the data to be written is stored as a special sector, to the LSA or as a regular sector, to the allocated sectors.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ben Sasson, Christopher B. E. Beeken, Joanna K. Brown, Florent Rostagni
  • Patent number: 10741266
    Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
  • Patent number: 10725781
    Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method includes generating a prior read command data structure and receiving a current read command. The method may include retrieving from the prior read command data structure a predicted next read command based on the received current read command, and pre-fetching data associated with the predicted next read command. The method may further include that after pre-fetching the data associate with the predicted next read command and prior to receiving a next read command, retrieving from the prior read command data structure a second predicted next read command based on the predicted next read command, and pre-fetching data associated with the second predicted next read command.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dudy Avraham, Ariel Navon, Shay Benisty, Karin Inbar
  • Patent number: 10684980
    Abstract: A system and method for multi-channel communication with dual in-line memory modules (“DIMMs”) is disclosed. The system retrieves information characterizing a plurality of memory channels, each of each is configurable to facilitate data communication between a DIMM and a memory controller with associated memory channel interfaces. Based on the retrieved information, one of the memory channels is designated as the active memory channel, granting the designated memory channel the ability to issue memory requests or transactions to the DIMM. On a periodic or as-needed basis (e.g., when the active memory channel is stalled or nearly stalled), the system determines whether to designate a different of the memory channels as the active memory channel, thereby enabling the newly-designated active memory channel the ability to issue memory requests or transactions to the DIMM. In some embodiments, only one of the memory channels is active at a time for communication with each DIMM.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 16, 2020
    Assignee: Facebook, Inc.
    Inventors: Narsing Vijayrao, Jay Parikh
  • Patent number: 10678459
    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: June 9, 2020
    Assignee: Rambus Inc.
    Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
  • Patent number: 10672441
    Abstract: Method and devices include a shifter that is configured to receive a write command for a memory device and is configured to produce multiple shifted write commands from the write command. Multiple flip-flops that are configured to receive a subset of the multiple shifted write commands from the shifter. The multiple flip-flops also are configured to output an indicator of whether subsequent write commands of the subset of write commands is asserted when the write command has completed shifting through the shifter as a write start signal.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Liang Chen, David R. Brown
  • Patent number: 10629245
    Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: April 21, 2020
    Assignee: Micro Technology, Inc.
    Inventors: Dean D. Gans, Daniel C. Skinner
  • Patent number: 10620954
    Abstract: A method and apparatus are provided for dynamically determining when an operation, specified by one or more instructions in a data processing system, is suitable for accelerated execution. Data indicators are maintained, for data registers of the system, that indicate when data-flow from a register derives from a restricted source. In addition, instruction predicates are provided for instructions to indicate which instructions are capable of accelerated execution. From the data indicators and the instruction predicates, the microarchitecture of the data processing system determines, dynamically, when the operation is a thread-restricted function and suitable for accelerated execution in a hardware accelerator. The thread-restricted function may be executed on a hardware processor, such as a vector, neuromorphic or other processor.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Arm Limited
    Inventors: Jonathan Curtis Beard, Curtis Glenn Dunham, Alejandro Rico Carro
  • Patent number: 10613977
    Abstract: Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, the integrated circuit device can include a target port operable to receive transactions from master ports. The target port can be configured with a multicast address range that is associated with a plurality of indices corresponding to memory banks of the device. When the target port receives a write transaction that has an address that is within the multicast address range, the target port can determine an index from the plurality of indices, and can use the index to determine a second address, which combines the index and the offset value with the address. The target port can then use the second address to write the data to the memory.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Randy Renfu Huang
  • Patent number: 10606484
    Abstract: At least one aspect is directed to a NAND flash storage device including a plurality of NAND flash chips and a controller. The controller is configured to receive data over an input/output (I/O) bus and write the received data to a first NAND flash chip of the plurality of NAND flash chips and a second NAND flash chip of the plurality of NAND flash chips. The write operations to each NAND flash chip do not overlap in time. The controller is configured to read data from whichever of the first NAND flash chip or the second NAND flash chip is not currently executing a write operation such that read operations are not queued behind write operations.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 31, 2020
    Assignee: Google LLC
    Inventor: Monish Shah
  • Patent number: 10592109
    Abstract: A method for execution by a dispersed storage and task (DST) client module includes determining a storage unit performance level for storage units of a set of storage units. Storage resources of the set of storage units are temporarily selected based on the storage unit performance levels to produce identities of candidate primary storage slots. Identities of candidate primary storage slots are exchanged with another DST client module. Selection of primary storage slots of the candidate primary storage slots is coordinated with the other non-transitory computer readable storage medium to produce identities of selected primary storage slots. Data stored in the set of storage units is accessed using the selected primary storage slots.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: March 17, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Ravi V. Khadiwala, Jason K. Resch
  • Patent number: 10552319
    Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Grzegorz Jereczek, Pawel Lebioda, Maciej Maciejewski, Pawel Makowski, Piotr Pelplinski, Jakub Radtke, Aleksandra Wisz
  • Patent number: 10521342
    Abstract: System and methods for address decoding prioritization. An example processing system may comprise: a plurality of base address registers, wherein each base address registers specifies an address range and a decoding priority associated with the address range; and an address decoding circuit coupled to the plurality of base address registers, the address decoding circuit to: receive a memory address identified by a memory access transaction, and produce a decoded address by decoding the memory address using the plurality of base address registers in an order of respective decoding priorities.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventor: Rodrigo R. Branco
  • Patent number: 10514860
    Abstract: A memory device includes a memory unit comprising one or more storage regions, and a control logic suitable for generating status information representing individualized states for the one or more storage regions.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 24, 2019
    Assignee: SK hynix Inc.
    Inventor: Yoon-Jo Oh
  • Patent number: 10509571
    Abstract: A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks. The first block among the blocks has a minimal erase count in the blocks. When determining that a difference between an average erase count of the blocks and the minimal erase count exceeds a cold-data threshold, the controller selects the first block to be a source block. When a data migration of a data-moving process is executed, the controller moves the data of the source block to a target block.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: December 17, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Zhongyi Gao, Xiaoyu Yang
  • Patent number: 10497089
    Abstract: A convolutional neural network (CNN) for an image processing system comprises an image cache responsive to a request to read a block of N×M pixels extending from a specified location within an input map to provide a block of N×M pixels at an output port. A convolution engine reads blocks of pixels from the output port, combines blocks of pixels with a corresponding set of weights to provide a product, and subjects the product to an activation function to provide an output pixel value. The image cache comprises a plurality of interleaved memories capable of simultaneously providing the N×M pixels at the output port in a single clock cycle. A controller provides a set of weights to the convolution engine before processing an input map, causes the convolution engine to scan across the input map by incrementing a specified location for successive blocks of pixels and generates an output map within the image cache by writing output pixel values to successive locations within the image cache.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: December 3, 2019
    Assignee: FotoNation Limited
    Inventors: Mihai Constantine Munteanu, Alexandru Caliman, Corneliu Zaharia, Dragos Dinu
  • Patent number: 10452532
    Abstract: The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory, wherein performing the deterministic garbage collection operation results in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: October 22, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey L. McVay, Daniel J. Hubbard, Robert W. Strong, Michael B. Danielson, Jonathan Tanguy
  • Patent number: 10424351
    Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: September 24, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Daniel C. Skinner
  • Patent number: 10380812
    Abstract: A secure chain of data blocks is maintained at a given computing node, wherein the given computing node is part of a set of computing nodes in a distributed network of computing nodes, and wherein each of the set of computing nodes maintains the secure chain of data blocks. The secure chain of data blocks maintained at each computing node comprises one or more data blocks that respectively represent one or more transactions associated with a vehicle. At least one data block is added to the secure chain of data blocks maintained at the given computing node in response to determining that transaction data associated with the at least one data block is valid.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: August 13, 2019
    Assignee: International Business Machines Corporation
    Inventors: Clifford A. Pickover, Komminist Weldemariam
  • Patent number: 10366005
    Abstract: Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 30, 2019
    Assignee: NXP USA, INC.
    Inventors: Arup Chakraborty, Mazyar Razzaz, James A. Welker
  • Patent number: 10353797
    Abstract: A method of runtime analysis for a computer program can include generating runtime data relating to memory usage for an instrumented computer program and creating a memory map comprising a plurality of memory ranges of different types according to the runtime data. At least a portion of the memory map can be presented to indicate selected ones of the plurality of memory ranges.
    Type: Grant
    Filed: December 29, 2006
    Date of Patent: July 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Kirk J. Krauss
  • Patent number: 10325637
    Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: June 18, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventor: Alejandro F. Gonzalez
  • Patent number: 10318187
    Abstract: A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: June 11, 2019
    Assignee: SK hynix Inc.
    Inventors: Il Park, Sang-Jin Byeon, Taek-Sang Song
  • Patent number: 10310876
    Abstract: A method for a hard disk to execute application code and an apparatus relate to the field of storage technologies such that a hard disk can support a manner of accessing the hard disk based on application code that is from outside of the hard disk, thereby improving performance of the hard disk, and improving a capability of a client to interact with the hard disk. The method includes receiving, by a hard disk, application code and an execution policy of the application code, determining, by the hard disk according to the application code, whether the application code needs to be executed in a virtual machine environment, and executing, by the hard disk in the virtual machine environment, the application code according to the execution policy of the application code when the application code needs to be executed in the virtual machine environment.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: June 4, 2019
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventor: Xiaosong Lei
  • Patent number: 10268393
    Abstract: A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: April 23, 2019
    Assignee: Avalanche Technology, Inc.
    Inventor: Siamack Nemazie
  • Patent number: 10262737
    Abstract: According to one embodiment, a semiconductor integrated circuit includes a ROM, an SRAM, a memory and a selector. The ROM stores initialization data. At least part of the initialization data is writable to the SRAM. The memory stores information indicating whether data is written to the SRAM. The selector outputs one of data supplied from the SRAM and data supplied from the ROM in accordance with the information stored in the memory.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: April 16, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yoshinori Adachi
  • Patent number: 10255069
    Abstract: Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A clear indicator that indicates whether the memory block is in a cleared state is assessed by the processor. The cleared state is a state of the memory block in which the memory block does not have any data stored therein. The method also includes determining based on the clear indicator whether the memory block is in the cleared state.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Peter G. Sutton, Craig R. Walters
  • Patent number: 10255073
    Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.
    Type: Grant
    Filed: May 11, 2017
    Date of Patent: April 9, 2019
    Assignee: MICROCHIP TECHNOLOGY INCORPORATED
    Inventors: Ashish Senapati, Sean Steedman, Brent Loertscher
  • Patent number: 10248418
    Abstract: Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A clear indicator that indicates whether the memory block is in a cleared state is assessed by the processor. The cleared state is a state of the memory block in which the memory block does not have any data stored therein. The method also includes determining based on the clear indicator whether the memory block is in the cleared state.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jane H. Bartik, Peter G. Sutton, Craig R. Walters
  • Patent number: 10241710
    Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.
    Type: Grant
    Filed: June 30, 2017
    Date of Patent: March 26, 2019
    Assignee: Intel Corporation
    Inventors: Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick, Frank T. Hady
  • Patent number: 10229890
    Abstract: Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: March 12, 2019
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Timothy M. Hollis
  • Patent number: 10223005
    Abstract: Techniques are described for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. A memory is partitioned into a group of sub-blocks, a parity block is associated with the sub-blocks, and the sub-blocks are accessed to read data as needed. A pending write buffer is added to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer handles collisions for write accesses to the same block.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: March 5, 2019
    Assignee: Cisco Technology, Inc.
    Inventors: Wei-Jen Huang, Chih-Tsung Huang, Sachin Agarwal, Sha Ma
  • Patent number: 10216658
    Abstract: A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. A microcontroller uses a counter to count how many times a rank of the DRAM is refreshed entirely (whether by a one-time per-rank refresh operation or by a series of per-bank refresh operations). When the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue, the microcontroller repeatedly performs the per-rank refresh operation on the rank. Every refresh inspection interval, the microcontroller decreases the counter by 1.
    Type: Grant
    Filed: May 19, 2017
    Date of Patent: February 26, 2019
    Assignee: VIA ALLIANCE SEMICONDUCTOR CO., LTD.
    Inventors: Chen Chen, Peng Shen
  • Patent number: 10191873
    Abstract: A method of and device for transferring data is provided. The method includes determining a difference between a data segment that was transferred last relative to each of one or more data segments available to be transferred next. In some embodiments, for so long as no data segment available to be sent has been waiting too long, the data segment chosen to be sent next is the data segment having the smallest difference relative to the data segment transferred last. The chosen data segment is then transmitted as the next data segment transferred.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: January 29, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Greg Sadowski