For Multiple Memory Modules (e.g., Banks, Interleaved Memory) Patents (Class 711/5)
  • Patent number: 11372546
    Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: June 28, 2022
    Assignee: Nordic Semiconductor ASA
    Inventors: Adrian J. Anderson, Gary C. Wass, Gareth J. Davies
  • Patent number: 11354420
    Abstract: Systems and methods for performing data duplication on data that was previously consolidated (e.g., deduplicated or merged). An example method may comprise: receiving, by a processing device, a request to modify a storage block comprising data encrypted using a location dependent cryptographic input; causing the data of the storage block to be encrypted using a location independent cryptographic input corresponding to a first storage location; copying the data encrypted using the location independent cryptographic input from the first storage location to a second storage location; causing data at the second storage location to be encrypted using a location dependent cryptographic input corresponding to the second storage location; and updating a reference of the storage block from the first storage location to the second storage location.
    Type: Grant
    Filed: July 21, 2017
    Date of Patent: June 7, 2022
    Assignee: Red Hat, Inc.
    Inventors: Henri Han Van Riel, Michael Tsirkin
  • Patent number: 11341045
    Abstract: A memory apparatus and a method for processing data the same are suggested to process 10-bit or 12-bit data. A processor that uses 10-bit or 12-bit data can efficiently store 10-bit or 12-bit data and provide a flexible memory access method that reduces memory usage. To this end, by adding a new memory bank that is ¼ of the size of an existing memory bank word, when storing data in 10-bit units, 2 out of 10 bits can be stored in a new memory bank to reduce memory waste. In addition, when 8-bit data is stored using a flexible memory structure, data can be stored in the same way as a previously operated memory bank.
    Type: Grant
    Filed: November 9, 2018
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: In Sang Cho
  • Patent number: 11307996
    Abstract: In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 19, 2022
    Assignee: Intel Corporation
    Inventors: Sarathy Jayakumar, Ashok Raj, Wei P. Chen, Theodros Yigzaw, John Holm
  • Patent number: 11301249
    Abstract: Handling an exception includes (i) executing a return from an exception; and (ii) executing a subsequent instruction with an additional functionality in case the additional functionality of the subsequent instruction can be triggered by a special instruction.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: April 12, 2022
    Assignee: Infineon Technologies AG
    Inventors: Albrecht Mayer, Neil Stuart Hastie, Pawel Jewstafjew
  • Patent number: 11288274
    Abstract: A system and method processes join requests via independently running engines. A build side table to be joined is allocated among high speed memories of the engines. Each row of a probe side are allocated to the engine likely to have build side data corresponding to the row, and the engine then performs the join. Aggregation statistics may be computed by distributing the information across the engines.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: March 29, 2022
    Assignee: Yellowbrick Data, Inc.
    Inventors: Adel Alsaadi, Jim Peterson, Paritosh Kulkarni
  • Patent number: 11283672
    Abstract: The techniques describe detecting connectivity failure of an aggregated interface. To monitor connectivity of the aggregated interface, a packet processor of a plurality of packet processors is set as a session master responsible for managing an active forwarding plane connectivity detection session with a peer session master node. The other local packet processors of the virtual network node are selected as session standby nodes that each have a passive forwarding plane connectivity detection session running to the peer session master node. If a session master node goes down (i.e., by link or node failure), one of the local session standby nodes may detect the failure and is set as a new session master node by activating its passive session having the same session parameters.
    Type: Grant
    Filed: May 25, 2018
    Date of Patent: March 22, 2022
    Assignee: Juniper Networks, Inc.
    Inventors: Gaurav Ganeriwal, Sharmila Koppula, Babu Singarayan, Vishnu Janardhanan S, Sayantani Gupta
  • Patent number: 11269398
    Abstract: Reducing power consumption of an electrical device is provided. The electrical device includes a first and a second module. The first and second modules include a first and a second memory, and a first and second system on chip (SoC) respectively. The first and second SoCs include a first and a second micro-processor respectively. A PCI-e bus connects the modules. The second module enters a sleep mode state that includes a first and a second sleep mode. The second module transitions between the first and second sleep modes while in the sleep mode state. The second SoC reduces a power state of the second module during the first sleep mode, and powers off the second SoC during the second sleep mode.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: March 8, 2022
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Dominique Gougeon, Frankie Alcazar, Paul D Bliley, Tyler Kapp
  • Patent number: 11223575
    Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: January 11, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Greggory D. Donley, Vydhyanathan Kalyanasundharam, Mark A. Silla, Ashwin Chincholi
  • Patent number: 11221771
    Abstract: A memory system may include a volatile memory that is configured to store an address data structure that includes a plurality of logical-to-physical address entries. The address data structure may be stored across a plurality of bank groups of the volatile memory. A controller may be configured to store consecutive logical-to-physical address entries across different bank groups. In turn, during read and write operations for data sets associated with consecutive logical addresses, read requests for physical addresses where the data sets are stored may be sent to multiple bank groups and processed by the multiple banks in parallel.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: January 11, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Jameer Mulani, Kapil Sundrani, Anindya Rai
  • Patent number: 11195497
    Abstract: Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: December 7, 2021
    Assignee: Intel Corporation
    Inventors: Altug Koker, Louis Feng, Tomasz Janczak, Andrew T. Lauritzen, David M. Cimini, Abhishek R. Appu
  • Patent number: 11182109
    Abstract: A data storage device includes a storage and a controller.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: November 23, 2021
    Assignee: SK hynix Inc.
    Inventor: Sung Yeob Cho
  • Patent number: 11169732
    Abstract: According to one embodiment, a computing device includes a first magnetic section, a first reading section, a memory section, and a computing section. The first reading section is configured to output a first signal corresponding to a magnetization state of a partial region of the first magnetic section. The computing section is configured to perform computation using the first signal when first information stored in the memory section is in a first state, and to perform computation using a reverse signal of the first signal when the first information is in a second state.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 9, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Rie Sato, Koichi Mizushima, Hayato Goto
  • Patent number: 11169745
    Abstract: An apparatus, method, and computer-readable storage medium for allowing a block-addressable storage device to provide a sparse address space to a host computer. The storage device exports an address space to a host computing device which is larger than the storage capacity of the storage device. The storage device translates received file system object addresses in the larger address space to physical locations in the smaller address space of the storage device. This allows the host computing device more flexibility in selecting addresses for file system objects which are stored on the storage device.
    Type: Grant
    Filed: July 23, 2019
    Date of Patent: November 9, 2021
    Assignee: Pure Storage, Inc.
    Inventors: Ethan Miller, John Colgrove, John Hayes
  • Patent number: 11139010
    Abstract: Provided is a method for operating an interface circuit of a memory device. The method includes receiving a command from a controller; determining whether the command is for a semiconductor memory or the interface circuit, the semiconductor memory operatively coupled to the interface circuit; and when it is determined that the command is for the interface circuit, performing a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performing an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: October 5, 2021
    Assignee: SK hynix Inc.
    Inventors: Chang Kyun Park, Young Sik Koh, Seung Jin Park, Dong Hyun Lee
  • Patent number: 11126433
    Abstract: Systems, apparatuses, and methods related to a block-based processor core composition register are disclosed. In one example of the disclosed technology, a processor can include a plurality of block-based processor cores for executing a program including a plurality of instruction blocks. A respective block-based processor core can include one or more sharable resources and a programmable composition control register. The programmable composition control register can be used to configure which resources of the one or more sharable resources are shared with other processor cores of the plurality of processor cores.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: September 21, 2021
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Douglas C. Burger, Aaron L. Smith
  • Patent number: 11093416
    Abstract: A memory system supporting programmable selective access to subsets of parallel-arranged memory chips for efficient memory accesses is disclosed. A memory controller is programmable to selectively control a number of parallel-arranged memory chips in the memory system activated in a grouping for a memory access based on a memory access policy. The memory access policy is based on the number of memory chips to be activated to achieve the desired data line size for a given memory access. This programmability of the memory controller is made possible by separate dedicated chip select lines being coupled to each memory chip. Being able to only activate a subset of the memory chips for a memory access allows conservation of data bus bandwidth and power that would otherwise by consumed by asserting unused data on the data buses.
    Type: Grant
    Filed: March 20, 2020
    Date of Patent: August 17, 2021
    Assignee: Qualcomm Intelligent Solutions, Inc
    Inventors: David Stewart Dunning, Shekhar Yeshwant Borkar, Nitin Yeshwant Borkar, Matthew Scott Radecic
  • Patent number: 11074496
    Abstract: Embodiments of the invention relate to providing transposable access to a synapse array using a recursive array layout. One embodiment comprises maintaining synaptic weights for multiple synapses connecting multiple axons and multiple neurons, wherein the synaptic weights are maintained based on a recursive array layout. The recursive array layout facilitates transposable access to the synaptic weights. A neuronal spike event between an axon and a neuron is communicated via a corresponding connecting synapse by accessing the synaptic weight of the corresponding connecting synapse in the recursive array layout.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: John V. Arthur, John E. Barth, Jr., Paul A. Merolla, Dharmendra S. Modha
  • Patent number: 11070512
    Abstract: Embodiments for server port virtualization for guest logical unit number (LUN) masking in a host direct attach configuration using a storage adapter in a computing environment by a processor. An F switch port is simulated by an N storage port to enable either N-port virtualization (NPV) or N-port identification (ID) virtualization (NPIV) in the host direct attach configuration by directly attaching the N server port to the N storage port. A domain name system (DNS) operation is performed to cause each virtualized N-port ID to be mapped to fiber channel (FC) IDs in domain format of domain, area, port.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: July 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Min Fang, Qing Wang, Wei Yin, Jiang Yu
  • Patent number: 11062741
    Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jun Yoon, Hyun Seung Kim
  • Patent number: 11055003
    Abstract: Apparatuses and methods can be related to supplementing AI processing in memory. An accelerator and/or a host can perform AI processing. Some of the operations comprising the AI processing can be performed by a memory device instead of by an accelerator and/or a host. The memory device can perform AI processing in conjunction with the host and/or accelerator to increase the efficiency of the host and/or accelerator.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: July 6, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Honglin Sun, Richard C. Murphy, Glen E. Hush
  • Patent number: 11049530
    Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Young Jun Yoon, Hyun Seung Kim
  • Patent number: 11023371
    Abstract: According to one embodiment, a memory system manages a plurality of parallel units each including blocks belonging to different nonvolatile memory dies. When receiving from a host a write request designating a third address to identify first data to be written, the memory system selects one block from undefective blocks included in one parallel unit as a write destination block by referring to defect information, determines a write destination location in the selected block, and writes the first data to the write destination location. The memory system notifies the host of a first physical address indicative of both of the selected block and the write destination location, and the third address.
    Type: Grant
    Filed: March 12, 2020
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Shinichi Kanno
  • Patent number: 10999568
    Abstract: In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus thereof for receiving a first command via a first interface that is addressable by a first address and receiving a second command via a second interface that is addressable by a second address.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: May 4, 2021
    Assignee: Nokia Technologies Oy
    Inventor: Mikko Muukki
  • Patent number: 10978115
    Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.
    Type: Grant
    Filed: April 21, 2020
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Dean D. Gans, Daniel C. Skinner
  • Patent number: 10922221
    Abstract: An example method includes maintaining a first data structure comprising logical address to physical address mappings for managed units corresponding to a memory, and maintaining a second data structure whose entries correspond to respective physical managed unit addresses. Each entry of the second data structure comprises an activity counter field corresponding to the respective physical managed unit address and a number of additional fields indicating whether the respective physical managed unit address is in one or more of a number of additional data structures. The one or more additional data structures are accessed in association with performing at least one of a wear leveling operation on the respective physical managed unit address, and a neighbor disturb mitigation operation on physical managed unit addresses corresponding to neighbors of the respective physical managed unit address.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: February 16, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Edward C. McGlaughlin, Joseph M. Jeddeloh
  • Patent number: 10891225
    Abstract: An example method can include, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory. The deterministic garbage collection operation performed on the memory can result in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: January 12, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jeffrey L. McVay, Daniel J. Hubbard, Robert W. Strong, Michael B. Danielson, Jonathan Tanguy
  • Patent number: 10854248
    Abstract: A semiconductor device includes an input/output (I/O) line drive control circuit and a data I/O circuit. The I/O line drive control circuit is configured to generate drive control pulses having a generation sequence, wherein the generation sequence of the drive control pulses are controlled based on a command pulse and address latch signals, and wherein the address latch signals are set based on when the command pulse is generated to perform a read operation or a write operation. The command pulse is generated to perform a read operation or a write operation. The data I/O circuit controls data I/O operations of a plurality of bank groups based on the drive control pulses.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: December 1, 2020
    Assignee: SK hynix Inc.
    Inventors: Young Jun Yoon, Hyun Seung Kim
  • Patent number: 10852921
    Abstract: A system and method facilitated on the Internet wherein users connected to the Internet via a system comprised of, a computer driven mobile GPS and/or AGPS enabled device, or, a stationary or portable computing device capable of connecting to the Internet, a corresponding mobile application and/or website portal with user account access, and an Application Programming Interface (API) for the user to interact with a user centric secure online database, engage with a method of constructing, saving, and sharing user defined specific geographic point location identity data sets or files exclusively that is not designed as a social interaction community involving tracking or proximity sensing of the user device. A system and method that is designed and intended for the purposes of constructing, saving, modifying, and sharing user defined geographic location identity data sets or files exclusively and absent requirements of engaging in actively tracking user devices.
    Type: Grant
    Filed: December 27, 2016
    Date of Patent: December 1, 2020
    Assignee: Latloc, LLC
    Inventor: Scott Kennedy
  • Patent number: 10839878
    Abstract: A processing device of a system receives a request to access a selected sector in a memory component. The selected sector is associated with a sector number. The processing device determines a virtual block corresponding to the selected sector. The virtual block is associated with a misalignment factor and a misalignment counter. The processing device determines if the misalignment counter satisfies a threshold criterion. In response to the misalignment counter satisfying the threshold criterion, the processing device generates an updated sector number by shifting the sector number by the misalignment factor and performs the access to the selected sector using the updated sector number. In response to the misalignment counter not satisfying the threshold criterion, the processing device updates the misalignment counter and performs the access to the selected sector using the sector number.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: November 17, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Luca Porzio, Marco Di Pasqua, Paolo Papa
  • Patent number: 10817201
    Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.
    Type: Grant
    Filed: March 25, 2019
    Date of Patent: October 27, 2020
    Assignee: Intel Corporation
    Inventors: Blaise Fanning, Shekoufeh Qawami, Raymond S. Tetrick, Frank T. Hady
  • Patent number: 10778552
    Abstract: A system or method for identifying latency contributors in a data storage network, that may include creating a historical workload fingerprint model for a data storage network from training data, along with monitoring and classifying a current sample data from the data storage network into a cluster, current workload fingerprint, and current workload type. The method may further include assigning a score to the current sample data based on the historical workload fingerprint model and correlating measured latency values from the current sample data to historically measured latency related factors to create a latency score chart that identifies factors causing latency in the data storage network for the current sample data.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: September 15, 2020
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Mayukh Dutta, Manoj Srivatsav, John J. Sengenberger
  • Patent number: 10763894
    Abstract: Methods and apparatus to parallelize data decompression are disclosed. An example method selecting initial starting positions in a compressed data bitstream; adjusting a first one of the initial starting positions to determine a first adjusted starting position by decoding the bitstream starting at a training position in the bitstream, the decoding including traversing the bitstream from the training position as though first data located at the training position is a valid token; outputting first decoded data generated by decoding a first segment of the bitstream starting from the first adjusted starting position; and merging the first decoded data with second decoded data generated by decoding a second segment of the bitstream, the decoding of the second segment starting from a second position in the bitstream and being performed in parallel with the decoding of the first segment, and the second segment preceding the first segment in the bitstream.
    Type: Grant
    Filed: May 3, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventors: Vinodh Gopal, James D. Guilford, Sudhir K. Satpathy, Sanu K. Mathew
  • Patent number: 10761851
    Abstract: The present disclosure provides a memory apparatus comprising a first set of storage blocks operating as a set of read storage blocks in a first computation layer and as a set of write storage blocks in a second computation layer, where the second computation layer follows the first computation layer. The memory apparatus also comprises a second set of storage blocks operating as a set of write storage blocks in the first computation layer and as a set of read storage blocks in the second computation layer.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: September 1, 2020
    Assignee: ALIBABA GROUP HOLDING LIMITED
    Inventors: Liang Han, Xiaowei Jiang, Jian Chen
  • Patent number: 10747452
    Abstract: A computer-implemented method of storing data on a storage device can receive an I/O request to read data from or write data to a data storage device. The data can be stored in special sectors as allocated sectors and regular sectors as a log-structured array (LSA). If the I/O request is to read data from the storage device, a determination can be made as to whether the data to be read is stored as a special sector, which can be read from the LSA, or as a regular sector, which can be can be read from the allocated sectors. If the I/O request is to write data to the storage device, a determination can be made as to whether the data to be written is stored as a special sector, to the LSA or as a regular sector, to the allocated sectors.
    Type: Grant
    Filed: February 21, 2019
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Ben Sasson, Christopher B. E. Beeken, Joanna K. Brown, Florent Rostagni
  • Patent number: 10741266
    Abstract: In a semiconductor integrated circuit, an internal circuit is capable of executing a first operation and a second operation concurrently, and an output circuit outputs to the outside of the semiconductor integrated circuit information indicating whether or not the first operation is being executed and information indicating whether or not the second operation is executable.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: August 11, 2020
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hiroshi Nakamura, Kenichi Imamiya, Toshio Yamamura, Koji Hosono, Koichi Kawai
  • Patent number: 10725781
    Abstract: Systems and methods for pre-fetching data in a memory device are disclosed. The method includes generating a prior read command data structure and receiving a current read command. The method may include retrieving from the prior read command data structure a predicted next read command based on the received current read command, and pre-fetching data associated with the predicted next read command. The method may further include that after pre-fetching the data associate with the predicted next read command and prior to receiving a next read command, retrieving from the prior read command data structure a second predicted next read command based on the predicted next read command, and pre-fetching data associated with the second predicted next read command.
    Type: Grant
    Filed: February 28, 2019
    Date of Patent: July 28, 2020
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dudy Avraham, Ariel Navon, Shay Benisty, Karin Inbar
  • Patent number: 10684980
    Abstract: A system and method for multi-channel communication with dual in-line memory modules (“DIMMs”) is disclosed. The system retrieves information characterizing a plurality of memory channels, each of each is configurable to facilitate data communication between a DIMM and a memory controller with associated memory channel interfaces. Based on the retrieved information, one of the memory channels is designated as the active memory channel, granting the designated memory channel the ability to issue memory requests or transactions to the DIMM. On a periodic or as-needed basis (e.g., when the active memory channel is stalled or nearly stalled), the system determines whether to designate a different of the memory channels as the active memory channel, thereby enabling the newly-designated active memory channel the ability to issue memory requests or transactions to the DIMM. In some embodiments, only one of the memory channels is active at a time for communication with each DIMM.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: June 16, 2020
    Assignee: Facebook, Inc.
    Inventors: Narsing Vijayrao, Jay Parikh
  • Patent number: 10678459
    Abstract: Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: June 9, 2020
    Assignee: Rambus Inc.
    Inventors: Suresh Rajan, Abhijit M. Abhyankar, Ravindranath Kollipara, David A. Secker
  • Patent number: 10672441
    Abstract: Method and devices include a shifter that is configured to receive a write command for a memory device and is configured to produce multiple shifted write commands from the write command. Multiple flip-flops that are configured to receive a subset of the multiple shifted write commands from the shifter. The multiple flip-flops also are configured to output an indicator of whether subsequent write commands of the subset of write commands is asserted when the write command has completed shifting through the shifter as a write start signal.
    Type: Grant
    Filed: July 31, 2018
    Date of Patent: June 2, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Daniel B. Penney, Liang Chen, David R. Brown
  • Patent number: 10629245
    Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: April 21, 2020
    Assignee: Micro Technology, Inc.
    Inventors: Dean D. Gans, Daniel C. Skinner
  • Patent number: 10620954
    Abstract: A method and apparatus are provided for dynamically determining when an operation, specified by one or more instructions in a data processing system, is suitable for accelerated execution. Data indicators are maintained, for data registers of the system, that indicate when data-flow from a register derives from a restricted source. In addition, instruction predicates are provided for instructions to indicate which instructions are capable of accelerated execution. From the data indicators and the instruction predicates, the microarchitecture of the data processing system determines, dynamically, when the operation is a thread-restricted function and suitable for accelerated execution in a hardware accelerator. The thread-restricted function may be executed on a hardware processor, such as a vector, neuromorphic or other processor.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: April 14, 2020
    Assignee: Arm Limited
    Inventors: Jonathan Curtis Beard, Curtis Glenn Dunham, Alejandro Rico Carro
  • Patent number: 10613977
    Abstract: Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, the integrated circuit device can include a target port operable to receive transactions from master ports. The target port can be configured with a multicast address range that is associated with a plurality of indices corresponding to memory banks of the device. When the target port receives a write transaction that has an address that is within the multicast address range, the target port can determine an index from the plurality of indices, and can use the index to determine a second address, which combines the index and the offset value with the address. The target port can then use the second address to write the data to the memory.
    Type: Grant
    Filed: September 27, 2018
    Date of Patent: April 7, 2020
    Assignee: Amazon Technologies, Inc.
    Inventors: Ron Diamant, Randy Renfu Huang
  • Patent number: 10606484
    Abstract: At least one aspect is directed to a NAND flash storage device including a plurality of NAND flash chips and a controller. The controller is configured to receive data over an input/output (I/O) bus and write the received data to a first NAND flash chip of the plurality of NAND flash chips and a second NAND flash chip of the plurality of NAND flash chips. The write operations to each NAND flash chip do not overlap in time. The controller is configured to read data from whichever of the first NAND flash chip or the second NAND flash chip is not currently executing a write operation such that read operations are not queued behind write operations.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: March 31, 2020
    Assignee: Google LLC
    Inventor: Monish Shah
  • Patent number: 10592109
    Abstract: A method for execution by a dispersed storage and task (DST) client module includes determining a storage unit performance level for storage units of a set of storage units. Storage resources of the set of storage units are temporarily selected based on the storage unit performance levels to produce identities of candidate primary storage slots. Identities of candidate primary storage slots are exchanged with another DST client module. Selection of primary storage slots of the candidate primary storage slots is coordinated with the other non-transitory computer readable storage medium to produce identities of selected primary storage slots. Data stored in the set of storage units is accessed using the selected primary storage slots.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: March 17, 2020
    Assignee: PURE STORAGE, INC.
    Inventors: Ravi V. Khadiwala, Jason K. Resch
  • Patent number: 10552319
    Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: February 4, 2020
    Assignee: Intel Corporation
    Inventors: Grzegorz Jereczek, Pawel Lebioda, Maciej Maciejewski, Pawel Makowski, Piotr Pelplinski, Jakub Radtke, Aleksandra Wisz
  • Patent number: 10521342
    Abstract: System and methods for address decoding prioritization. An example processing system may comprise: a plurality of base address registers, wherein each base address registers specifies an address range and a decoding priority associated with the address range; and an address decoding circuit coupled to the plurality of base address registers, the address decoding circuit to: receive a memory address identified by a memory access transaction, and produce a decoded address by decoding the memory address using the plurality of base address registers in an order of respective decoding priorities.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventor: Rodrigo R. Branco
  • Patent number: 10514860
    Abstract: A memory device includes a memory unit comprising one or more storage regions, and a control logic suitable for generating status information representing individualized states for the one or more storage regions.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: December 24, 2019
    Assignee: SK hynix Inc.
    Inventor: Yoon-Jo Oh
  • Patent number: 10509571
    Abstract: A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks. The first block among the blocks has a minimal erase count in the blocks. When determining that a difference between an average erase count of the blocks and the minimal erase count exceeds a cold-data threshold, the controller selects the first block to be a source block. When a data migration of a data-moving process is executed, the controller moves the data of the source block to a target block.
    Type: Grant
    Filed: April 18, 2018
    Date of Patent: December 17, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Zhongyi Gao, Xiaoyu Yang
  • Patent number: 10497089
    Abstract: A convolutional neural network (CNN) for an image processing system comprises an image cache responsive to a request to read a block of N×M pixels extending from a specified location within an input map to provide a block of N×M pixels at an output port. A convolution engine reads blocks of pixels from the output port, combines blocks of pixels with a corresponding set of weights to provide a product, and subjects the product to an activation function to provide an output pixel value. The image cache comprises a plurality of interleaved memories capable of simultaneously providing the N×M pixels at the output port in a single clock cycle. A controller provides a set of weights to the convolution engine before processing an input map, causes the convolution engine to scan across the input map by incrementing a specified location for successive blocks of pixels and generates an output map within the image cache by writing output pixel values to successive locations within the image cache.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: December 3, 2019
    Assignee: FotoNation Limited
    Inventors: Mihai Constantine Munteanu, Alexandru Caliman, Corneliu Zaharia, Dragos Dinu