Abstract: According to one embodiment, a data storage apparatus includes an interface module and a controller. The interface module is configured to control rewritable nonvolatile memories provided for the respective channels. The controller is configured to write calibration data to the nonvolatile memories of any channel designated, through the interface module at the same time, in order to perform calibration.

Abstract: According to one embodiment, an apparatus comprises one or more memory devices and one or more processors coupled to a circuit board. The memory devices are configured according to a second memory technology. The processors are configured to receive messages conforming to a first memory technology, translate the messages from the first memory technology to the second memory technology, and send the translated messages to the memory devices.

Abstract: A memory package and methods for writing data to and reading data from the memory package are presented. The memory package includes a volatile memory and a high-density memory. Data is written to the memory package at a bandwidth and latency associated with the volatile memory. A directory map associates a volatile memory address with data in the high-density memory. A copy of the directory map is stored in the high-density memory. The methods allow writing to and reading from the memory package using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).

Abstract: A system, a method and a non-transitory computer readable medium are disclosed. The non-transitory computer readable medium may store instructions for: (I) interleaving at least two portions of a first codeword of a group of codewords between at least two flash memory planes while violating at least one ordering rule out of (a) an even odd ordering rule, (b) a programming type ordering rule, and (c) a codeword portions ordering rule; and (II) interleaving different portions of other codewords of the group of codewords between multiple flash memory planes while maintaining the even odd ordering rule, the programming type ordering rule and the codeword portions ordering rule. The at least two portions may be programmed to rows in different flash memory blocks, and the flash memory planes may belong to the same or multiple flash memory dies. The programming type ordering may define different decoupling sequence steps with sizes set for different programming types according to sensitivity to noise.

Abstract: In one embodiment, a system comprises a plurality of memory ports. The memory ports are distributed into a plurality of subsets, where each subset is identified by a subset index. The system further comprises a first address hashing unit configured to receive a request including at least one virtual memory address. Each virtual memory address is associated with a replication factor, and the virtual memory address refers to graph data. The first address hashing unit translates the replication factor into a corresponding subset index based on the virtual memory address, and converts the virtual memory address to a hardware based memory address. The hardware based address refers to data in the memory ports within a subset indicated by the corresponding subset index.

Abstract: In embodiments of a multi-dimension memory timing tuner, a memory device controller that can be interfaced with one or more memory devices is coupled to a memory device for data communication with the memory device via a bus, such as a data control system, system bus, or memory bus. Memory maintains values, such as a control register maintaining control register values, which are adjustable to tune bus timing margins in multi-dimensions. The bus timing margins are tunable for implementation of a memory device controller with one or more of the memory devices. A memory timing tuner is implemented to adjust the values to tune the bus timing margins in the multi-dimensions.

Abstract: In some embodiments, an apparatus includes a set of memory modules configured to store data and a reprogrammable circuit module operatively coupled to the set of memory modules. The reprogrammable circuit module is configured to receive, from a host device, information associated with a search request. The reprogrammable circuit module is configured to change from a first configuration to a second configuration in response to receiving the information. The reprogrammable circuit module is configured to retrieve at least a portion of the data stored at the set of memory modules associated with the second configuration. The reprogrammable circuit module is configured to generate a search result based on the portion of the data, and transmit the search result to the host device.

Abstract: A method and apparatus for efficient memory bank utilization in multi-threaded packet processors is presented. A plurality of memory access requests, are received and are buffered by a plurality of memory First In First Out (FIFO) buffers, each of the memory FIFO buffers in communication with a memory controller. The memory access requests are distributed evenly across said memory banks by way of the memory controller. This reduces and/or eliminates memory latency which can occur when sequential memory operations are performed on the same memory bank.

Abstract: This document discusses, among other things, an example system and methods for memory expansion. An example embodiment includes receiving a memory request from a memory controller over a channel. Based on the memory request, the example embodiment includes selecting a location in memory to couple to a sub-channel of the channel and configuring the set of field effect transistors to couple the channel with the sub-channel. In the example embodiment, data may be allowed to flow between the memory controller and the location in the memory over the channel and the sub-channel.

Abstract: A display system comprises a mapping memory comprising a plurality of memory banks configured to store a plurality of image tiles corresponding to an image, and an image mapping component configured to assign each of the plurality of tiles to one of the plurality of memory banks according to a first mapping or a second mapping, wherein the image mapping component determines whether to use the first or second mapping based on a bank interleaving metric of the first and second mappings.

Abstract: A memory system that interleaves storage of data across and within a plurality memory modules is described. The memory system includes a hybrid interleaving mechanism which maps physical addresses to locations within memory modules and ranks so that physical addresses for a given page all map to the same memory module, and physical addresses for the given page are interleaved across the plurality of ranks which comprise the same memory module.

Abstract: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A performance ranking of a particular memory bank may be based at least in part on both a busyness and a row hit ratio of the particular memory bank. Apparatus and computer readable media are also described.

Abstract: A system and method for clients, a control module, and storage modules to participate in a unifed address space in order to and read and write data efficiently using direct-memory access. The method for reading data includes determining a first location in a first memory to write a first copy of the data, a second location in a second memory to write a second copy of the data, where the first memory is located in a first storage module including a first persistent storage and the second memory is located in a second storage module including a second persistent storage. The method further includes programming a direct memory access engine to read the data from the client memory and issue a first write request to a multicast address, where the first location, the second location, and a third location are associated with the multicast address.

Abstract: One system may comprise an interleave system that determines a desired interleave for at least a selected portion of a distributed memory system. A migration system is associated with the interleave system to migrate blocks of data from first assigned memory locations of the distributed memory system to second interleaved memory locations of the distributed memory system to implement the desired interleave.

Abstract: An information processing device according to the present invention includes an operation unit that outputs an access request, a storage unit including a plurality of connection ports and a plurality of memories capable of a simultaneous parallel process that has an access unit of a plurality of word lengths for the connection ports, and a memory access control unit that distributes a plurality access addresses corresponding to the access request received for each processing cycle from the operation unit, and generates an address in a port including a discontinuous word by one access unit for each of the connection ports.

Abstract: An instruction set for a microcontroller with a data memory divided into a plurality of memory banks wherein the data memory has more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped, a bank select register which is not mapped to the data memory for selecting a memory bank, and with an indirect access register mapped to at least one memory bank, wherein the instruction set includes a plurality of instructions operable to directly address all memory locations within a selected bank, at least one instruction that provides access to the bank select register, and at least one instruction performing an indirect address to the data memory using the indirect access register.

Abstract: Systems, methods, and devices for dynamically mapping and remapping memory when a portion of memory is activated or deactivated are provided. In accordance with an embodiment, an electronic device may include several memory banks, one or more processors, and a memory controller. The memory banks may store data in hardware memory locations and may be independently deactivated. The processors may request the data using physical memory addresses, and the memory controller may translate the physical addresses to hardware memory locations. The memory controller may use a first memory mapping function when a first number of memory banks is active and a second memory mapping function when a second number is active. When one of the memory banks is to be deactivated, the memory controller may copy data from only the memory bank that is to be deactivated to the active remainder of memory banks.

Abstract: A storage control device includes a first storage unit, a write control unit, and a read control unit. The first storage unit includes a plurality of storage areas corresponding to a plurality of addresses. The write control unit performs a write process to sequentially designate one of the plurality of addresses and write data to the storage area corresponding to the designated address, in a predetermined first order. The read control unit performs a read process to sequentially designate one of the plurality of addresses and read data stored in the storage area corresponding to the designated address, in a second order opposite to the first order, starting with the address corresponding to the storage area in which data has been stored immediately near a predetermined start timing after the beginning of execution of the write process, the read process being started at the predetermined start timing.

Abstract: A microcontroller has a data memory divided into a plurality of memory banks, an address multiplexer for providing an address to the data memory, an instruction register providing a first partial address to a first input of the address multiplexer, a bank select register which is not mapped to the data memory for providing a second partial address to a the first input of the address multiplexer, and a plurality of special function registers mapped to the data memory, wherein the plurality of special function registers comprises an indirect access register coupled with a second input of the address multiplexer, and wherein the data memory comprises more than one memory bank of the plurality of memory banks that form a block of linear data memory to which no special function registers are mapped.

Abstract: Embodiments of the present invention are directed to a method, computer-readable medium and system for deskewing data. More specifically, skewed data is accessed and written into a plurality of memories in an aligned manner. Each memory may be associated with a respective lane of a multiple lane distribution (MLD) system and may receive a respective initial portion of data associated with a frame. The memory or lane that is the last to receive an initial portion of data associated with the frame may be determined. The address at which the initial portion of data is written into the memory may be determined using a write pointer associated with the memory. At least one read pointer associated with the memories may be set to the address to allow the initial portions of data to be contemporaneously read from the memories.

Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.

Abstract: A memory system architecture has serially connected memory devices. The memory system is scalable to include any number of memory devices without any performance degradation or complex redesign. Each memory device has a serial input/output interface for communicating between other memory devices and a memory controller. The memory controller issues commands in at least one bitstream, where the bitstream follows a modular command protocol. The command includes an operation code with optional address information and a device address, so that only the addressed memory device acts upon the command. Separate data output strobe and command input strobe signals are provided in parallel with each output data stream and input command data stream, respectively, for identifying the type of data and the length of the data. The modular command protocol is used for executing concurrent operations in each memory device to further improve performance.

Abstract: A controller designed for use with a flash memory storage module, including a crossbar switch designed to connect a plurality of internal processors with various internal resources, including a plurality of internal memories. The memories contain work lists for the processors. In one embodiment, the processors communicate by using the crossbar switch to place tasks on the work lists of other processors.

Abstract: A method and system for performing byte-writes are described, where byte-writes involve writing only particular bytes of a multiple byte write operation. Embodiments include mask data that indicates which bytes are to be written in a byte-write operation. No dedicated mask pin(s) or dedicated mask line(s) are used. In one embodiment, the mask data is transmitted on data lines and store in response to a write_mask command. In one embodiment, the mask data is transmitted as part of the write command.

Abstract: A transactional memory (TM) receives an Atomic Metering Command (AMC) across a bus from a processor. The command includes a memory address and a meter pair indicator value. In response to the AMC, the TM pulls an input value (IV). The TM uses the memory address to read a word including multiple credit values from a memory unit. Circuitry within the TM selects a pair of credit values, subtracts the IV from each of the pair of credit values thereby generating a pair of decremented credit values, compares the pair of decremented credit values with a threshold value, respectively, thereby generating a pair of indicator values, performs a lookup based upon the pair of indicator values and the meter pair indicator value, and outputs a selector value and a result value that represents a meter color. The selector value determines the credit values written back to the memory unit.

Abstract: A system includes: a controller, a first memory module connected to the controller through a first data bus, and a second memory module connected to the controller through a second data bus, wherein the first memory module includes: first and second memory chips; a first data terminal connected to the first data bus, and a first switch unit that electrical connects the first data terminal with either the first memory chip and the second memory chip, and the second module includes: third and fourth memory chips; a second data terminal connected to the second data bus, and a second switch unit that switches over electrical connection of the second data terminal with either the third memory chip or the fourth memory chip.

Abstract: Systems and methods for re-mapping memory transactions are described. In an embodiment, a method includes receiving a memory request from a hardware subsystem to a memory, replacing a first identifier with a modified identifier in the memory request, and transmitting the memory request to the memory through a processor complex. The method further includes receiving a response from the memory, determining that the response corresponds to the memory request, replacing the modified identifier with the first identifier in the response, and transmitting the response to the hardware subsystem. In some embodiments, a system may be implemented as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.

Abstract: Described are memory apparatus organized in physical banks and including configurable data control circuit to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey configuration value to configurable memory apparatus and support point-to-point data buffers for multiple width configurations.

Abstract: Systems and techniques relating to storage technologies are described. A described technique includes operating drives such as a solid state drive (SSD) and a disk drive, where the SSD and the disk drive are virtualized as a single logical drive having a logical address space, where the logical drive maps logical block addresses to the SSD and to the disk drive. The technique includes determining, based on a file to be written to the logical drive, a target logical address that corresponds to one of the SSD and the disk drive, and writing the file to the logical drive at the target logical address to effect storage on one of the SSD and the disk drive.

Abstract: A storage controller containing multiple processors. The processors are divided into groups, each of which handles a different stage of a pipelined process of performing host reads and writes. In one embodiment, the storage controller operates with a flash memory module, and includes multiple parallel pipelines that allow plural host commands to be handled simultaneously.

Abstract: A storage subsystem coupled to a host computer is described. The storage subsystem includes storage devices and first and second storage apparatuses that control data transfer between the host computer and the storage devices. The first storage apparatus includes a first controller coupled to the host computer via a first host communication control unit and to the storage devices via a first storage device communication control unit. The second storage apparatus includes a second controller coupled to the host computer via a second host communication control unit and to the storage devices via a second storage device communication control unit. At least one of the controllers monitors a status of the first host communication control unit and the storage device communication control units, and, if the status of the first storage device communication unit indicates failure, switch communication paths for transferring data from the host computer to the storage devices.

Abstract: In embodiments of a multi-dimension memory timing tuner, a memory device controller that can be interfaced with one or more memory devices is coupled to a memory device for data communication with the memory device via a memory bus. Control registers maintain control register values that are adjustable to tune memory bus timing margins in multi-dimensions. The memory bus timing margins are tunable for implementation of a memory device controller with one or more of the memory devices. A memory timing tuner is implemented to adjust the control register values to tune the memory bus timing margins in the multi-dimensions.

Abstract: Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.

Abstract: A circuit is configured to be mounted on a memory module connectable to a computer system so as to be electrically coupled to a plurality of memory devices on the memory module. The memory module has a first number of ranks of double-data-rate (DDR) memory devices activated at least in part to a first number of chip-select signals. The circuit is configurable to receive address signals and a second number of chip-select signals from the computer system. The circuit is further configurable to generate and transmit phase-locked clock signals to the first number of ranks, and to generate the first number of chip-select signals in response at least in part to the phase-locked clock signals, the address signals, and the second number of chip-select signals.

Abstract: A method and system are provided for determining a next available address for writing data to a cache memory. In one implementation, a method includes receiving a request for a candidate address in the cache memory, the cache memory divided into a plurality of banks. The method further includes determining a candidate address in each of the cache memory banks using an address determination algorithm, selecting one of the candidate addresses from among the determined candidate addresses using an address selection function different from the address determination algorithm, and returning the selected candidate address in response to the request.

Abstract: Techniques for efficiently generating addresses for pruned interleavers and pruned de-interleavers are described. In an aspect, a linear address may be mapped to an interleaved address for a pruned interleaver by determining the total number of invalid mappings corresponding to the linear address. The linear address may be summed with the total number of invalid mappings to obtain an intermediate address. The interleaved address for the pruned interleaver may then be determined based on a non-pruned interleaver function of the intermediate address. The pruned interleaver may be a pruned bit-reversal interleaver, a pruned Turbo interleaver composed of a bit-reversal function and a linear congruential sequence function, or some other type of interleaver. The total number of invalid mappings may be determined iteratively, and each iteration may be performed in different manners for different types of pruned interleaver.

Abstract: A volatile memory associated with a mass storage controller and a flash memory module. The volatile memory includes a number of tables containing information related to the flash memory storage, including a table storing physical flash memory addresses and a plurality of tables containing metadata.

Abstract: The present disclosure includes methods, devices, and systems for object oriented memory in solid state devices. One embodiment of a method for object oriented memory in solid state devices includes accessing a defined set of data as a single object in an atomic operation manner, where the accessing is from a source other than a host. The embodiment also includes storing the defined set of data as the single object in a number of solid state memory blocks as formatted by a control component of a solid state device that includes the number of solid state memory blocks.

Abstract: An access control device, which increases memory access efficiency to data stored in a memory, includes a plurality of groups of the memory, and divides and stores the data in different memory areas of the plurality of groups of the memory, distinguished based on predetermined bits of an access address. The access control device accesses the data stored in the different memory areas simultaneously in the same clock cycle of access to the memory. The predetermined bits of the access address are controlled independently for each of the groups of the memory. The part of the access address other than the predetermined bits controlled independently for each of the groups is common for the plurality of groups. Modes can be selected to access two horizontally or vertically consecutive unit data or data on vertically alternate lines at a time. The data may be image data or pixel data.

Abstract: Systems and methods to process packets of information using an on-chip processing system include a memory bank, an interconnect module, a controller, and one or more processing engines. The packets of information include a packet header and a packet payload. The packet header includes one or more operator codes. The transfer of individual packets is guided to a processing engine through the interconnect module and through the controller by operator codes included in the packets.

Abstract: A memory system having a memory controller and several separate memory devices connected to the controller by a system bus. The memory devices each included an array of memory cells, addressing circuitry used to address the cells and an address storage circuit which stores a local address unique to each of the memory devices. The local addresses are sequentially assigned to the memory devices by selecting a first one of the devices and forwarding an address assign command to the selected device. A command decoder, having detected the address assign command, will permit a local address placed on the bus by the controller to be loaded into the selected memory device. This sequence will continue until all of the memory devices have been assigned local addresses at which time the memory devices can be accessed to perform memory read, program, erase and other operations.

Abstract: A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.

Abstract: Embodiments of the present disclosure describe methods, apparatus, and system configurations for providing rank-specific cyclic redundancy checks in memory systems.

Abstract: A non-volatile memory may include a plurality of map blocks for storing a plurality of map units, the map units representing mapping information between physical addresses and logical addresses. A storage device may include such a non-volatile memory. A method of mapping such a non-volatile memory may include writing historical information regarding locations of valid map units among the map units included in map blocks previously allocated among the map blocks when a new map block among the map blocks is allocated, the valid map units representing valid mapping information, and constructing a map table including all of the valid mapping information based on the historical information and a result of searching a map block recently allocated among the map blocks.

Abstract: A storage controller connected to a flash memory storage module, the controller and module including multiple sets of buffers. The buffers are part of one or more pipelines through which data is moved between the storage module and one or more hosts.

Abstract: A memory system is provided. The system includes an operating system kernel that regulates read and write access to one or more FLASH memory devices that are employed for random access memory applications. A buffer component operates in conjunction with the kernel to regulate read and write access to the one or more FLASH devices.

Abstract: A method is described for operation of a DMA engine. Copying is initiated for transfer of a first number of bytes from first source memory locations to first destination memory locations. Then, a halt instruction is issued before the first number of bytes are copied. After copying is stopped, a second number of bytes is established, encompassing those bytes remaining to be copied. After the transfer is halted, a quantity of the second number of bytes is identified. Quantity information is then generated and stored. Second source memory locations are identified to indicate where the second number of bytes are stored. Second source memory location information is then generated and stored. Second destination memory locations are then identified to indicate where the second number of bytes are to be transferred. Second destination memory location information is then generated and stored.

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract: A method and system for secure data storage and retrieval is provided. A sequence of data units is divided into multiple subsets of data units corresponding to multiple data channels. The multiple data channels are assigned to multiple data writers based on a key code. Then, each subset of data units is transferred to a writer via an assigned channel for writing to storage media. Thereafter, to securely retrieve the stored data, each subset of data units is read from the storage media using a data reader. The original sequence of data units can only be reassembled using the key code for properly reassembling the subsets of data units into their original sequence.

Abstract: Method, process, and apparatus to efficiently store, read, and/or process syllables of word data. A portion of a data word, which includes multiple syllables, may be read by a computer processor. The processor may read a first syllable of the data word from a first memory. The processor may read a second syllable of the data word from a second portion of memory. The second syllable may include bits which are less critical than the bits of the first syllable. The second memory may be distinct from the first memory based on one or more physical attributes.