Abstract: Provided are integrated circuit devices and methods for operating integrated circuit devices. In various examples, the integrated circuit device can include a target port operable to receive transactions from master ports. The target port can be configured with a multicast address range that is associated with a plurality of indices corresponding to memory banks of the device. When the target port receives a write transaction that has an address that is within the multicast address range, the target port can determine an index from the plurality of indices, and can use the index to determine a second address, which combines the index and the offset value with the address. The target port can then use the second address to write the data to the memory.

Abstract: At least one aspect is directed to a NAND flash storage device including a plurality of NAND flash chips and a controller. The controller is configured to receive data over an input/output (I/O) bus and write the received data to a first NAND flash chip of the plurality of NAND flash chips and a second NAND flash chip of the plurality of NAND flash chips. The write operations to each NAND flash chip do not overlap in time. The controller is configured to read data from whichever of the first NAND flash chip or the second NAND flash chip is not currently executing a write operation such that read operations are not queued behind write operations.

Abstract: A method for execution by a dispersed storage and task (DST) client module includes determining a storage unit performance level for storage units of a set of storage units. Storage resources of the set of storage units are temporarily selected based on the storage unit performance levels to produce identities of candidate primary storage slots. Identities of candidate primary storage slots are exchanged with another DST client module. Selection of primary storage slots of the candidate primary storage slots is coordinated with the other non-transitory computer readable storage medium to produce identities of selected primary storage slots. Data stored in the set of storage units is accessed using the selected primary storage slots.

Abstract: An embodiment of a semiconductor apparatus may include technology to identify a group of objects based on a common object structure, and allocate the group of objects to two or more memory channels based on interleave set information. Other embodiments are disclosed and claimed.

Abstract: System and methods for address decoding prioritization. An example processing system may comprise: a plurality of base address registers, wherein each base address registers specifies an address range and a decoding priority associated with the address range; and an address decoding circuit coupled to the plurality of base address registers, the address decoding circuit to: receive a memory address identified by a memory access transaction, and produce a decoded address by decoding the memory address using the plurality of base address registers in an order of respective decoding priorities.

Abstract: A memory device includes a memory unit comprising one or more storage regions, and a control logic suitable for generating status information representing individualized states for the one or more storage regions.

Abstract: A storage device includes a flash memory array and a controller. The flash memory array includes a plurality of blocks. The first block among the blocks has a minimal erase count in the blocks. When determining that a difference between an average erase count of the blocks and the minimal erase count exceeds a cold-data threshold, the controller selects the first block to be a source block. When a data migration of a data-moving process is executed, the controller moves the data of the source block to a target block.

Abstract: A convolutional neural network (CNN) for an image processing system comprises an image cache responsive to a request to read a block of N×M pixels extending from a specified location within an input map to provide a block of N×M pixels at an output port. A convolution engine reads blocks of pixels from the output port, combines blocks of pixels with a corresponding set of weights to provide a product, and subjects the product to an activation function to provide an output pixel value. The image cache comprises a plurality of interleaved memories capable of simultaneously providing the N×M pixels at the output port in a single clock cycle. A controller provides a set of weights to the convolution engine before processing an input map, causes the convolution engine to scan across the input map by incrementing a specified location for successive blocks of pixels and generates an output map within the image cache by writing output pixel values to successive locations within the image cache.

Abstract: The present disclosure includes apparatuses and methods for directed sanitization of memory. One example method comprises, responsive to receiving a sanitization command, performing a deterministic garbage collection operation on a memory, wherein performing the deterministic garbage collection operation results in physical erasure of all invalid data stored on the memory without losing valid data stored on the memory.

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

Abstract: A secure chain of data blocks is maintained at a given computing node, wherein the given computing node is part of a set of computing nodes in a distributed network of computing nodes, and wherein each of the set of computing nodes maintains the secure chain of data blocks. The secure chain of data blocks maintained at each computing node comprises one or more data blocks that respectively represent one or more transactions associated with a vehicle. At least one data block is added to the secure chain of data blocks maintained at the given computing node in response to determining that transaction data associated with the at least one data block is valid.

Abstract: Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.

Abstract: A method of runtime analysis for a computer program can include generating runtime data relating to memory usage for an instrumented computer program and creating a memory map comprising a plurality of memory ranges of different types according to the runtime data. At least a portion of the memory map can be presented to indicate selected ones of the plurality of memory ranges.

Abstract: An apparatus includes a plurality of memory devices and a control circuit. The control circuit may be configured to enable a plurality of access modes for the plurality of memory devices. In a one-channel mode, all of the memory devices are accessed using a single selectable channel. In a two-channel mode, a first portion of the plurality of memory devices is accessed using a first channel and a second portion of the plurality of memory devices is accessed using a second channel.

Abstract: A memory system includes: a memory device including a plurality of memory banks; and a memory controller suitable for monitoring a workload of the memory device and applying one of a first refresh command and a second refresh command to the memory device according to a result of the monitoring. In the memory device, the number of memory banks to be refreshed by the second refresh command may be greater than the number of memory banks to be refreshed by the first refresh command.

Abstract: A method for a hard disk to execute application code and an apparatus relate to the field of storage technologies such that a hard disk can support a manner of accessing the hard disk based on application code that is from outside of the hard disk, thereby improving performance of the hard disk, and improving a capability of a client to interact with the hard disk. The method includes receiving, by a hard disk, application code and an execution policy of the application code, determining, by the hard disk according to the application code, whether the application code needs to be executed in a virtual machine environment, and executing, by the hard disk in the virtual machine environment, the application code according to the execution policy of the application code when the application code needs to be executed in the virtual machine environment.

Abstract: A non-volatile memory device configured to emulate DRAM interface comprising a memory array that includes a plurality of magnetic memory cells organized into rows and columns with at least one row of the magnetic memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.

Abstract: According to one embodiment, a semiconductor integrated circuit includes a ROM, an SRAM, a memory and a selector. The ROM stores initialization data. At least part of the initialization data is writable to the SRAM. The memory stores information indicating whether data is written to the SRAM. The selector outputs one of data supplied from the SRAM and data supplied from the ROM in accordance with the information stored in the memory.

Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.

Abstract: Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A clear indicator that indicates whether the memory block is in a cleared state is assessed by the processor. The cleared state is a state of the memory block in which the memory block does not have any data stored therein. The method also includes determining based on the clear indicator whether the memory block is in the cleared state.

Abstract: Aspects include a computer-implemented method for receiving an instruction at a processor, the instruction associated with a memory block having an address. A clear indicator that indicates whether the memory block is in a cleared state is assessed by the processor. The cleared state is a state of the memory block in which the memory block does not have any data stored therein. The method also includes determining based on the clear indicator whether the memory block is in the cleared state.

Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

Abstract: Methods, systems, and devices for compensating for memory input capacitance. Techniques are described herein to alter the capacitance of an access line coupled with a plurality of memory cells. The capacitance of the access line may be filtered by an inductive region, which could be implemented in one or more individual signal paths. Thus a signal may be transmitted to one or more selected memory cells and the inductive region may alter a capacitance of the access line in response to receiving a reflection of the signal from an unselected memory cell. In some examples, the transmitted signal may be modulated using pulse amplitude modulation (PAM), where the signal may be modulated using a modulation scheme that includes at least three levels to encode more than one bit of information (e.g., PAM4).

Abstract: Techniques are described for a memory device. In various embodiments, a scheduler/controller is configured to manage data as it read to or written from a memory. A memory is partitioned into a group of sub-blocks, a parity block is associated with the sub-blocks, and the sub-blocks are accessed to read data as needed. A pending write buffer is added to a group of memory sub-blocks. Such a buffer may be sized to be equal to the group of memory sub-blocks. The pending write buffer handles collisions for write accesses to the same block.

Abstract: A schedule for refreshing a dynamic random access memory (DRAM). Access commands for a DRAM are queued in a command queue. A microcontroller uses a counter to count how many times a rank of the DRAM is refreshed entirely (whether by a one-time per-rank refresh operation or by a series of per-bank refresh operations). When the counter has not reached an upper limit and no access command corresponding to the rank is waiting in the command queue, the microcontroller repeatedly performs the per-rank refresh operation on the rank. Every refresh inspection interval, the microcontroller decreases the counter by 1.

Abstract: A method of and device for transferring data is provided. The method includes determining a difference between a data segment that was transferred last relative to each of one or more data segments available to be transferred next. In some embodiments, for so long as no data segment available to be sent has been waiting too long, the data segment chosen to be sent next is the data segment having the smallest difference relative to the data segment transferred last. The chosen data segment is then transmitted as the next data segment transferred.

Abstract: An apparatus includes an arbiter circuit and a translation circuit. The arbiter circuit may be configured to generate a first address signal in a virtual memory space by arbitrating among a plurality of clients to access a physical memory space. The clients may be classified as either privileged clients or non-privileged clients. The physical memory space may comprise at least one secure space. The translation circuit may be configured to generate a second address signal by translating a page in the virtual memory space into the physical memory space based on the first address signal. The page may corresponds to a particular one of the clients that won the arbitration. The page may be translated (a) into the secure space if the particular client is one of the privileged clients and (b) outside the secure space otherwise.

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

Abstract: A controller includes a command generation unit suitable for generating a first read command for at least one page selected from said plurality of pages, an error correction block suitable for performing a first error correction operation to one or more code words stored in said at least one selected page in response to the first read command, and a command mirroring unit suitable for generating a mirrored command by mirroring the first read command.

Abstract: A resiliency system detects and corrects memory errors reported by a memory system of a computing system using previously stored error correction information. When a program stores data into a memory location, the resiliency system executing on the computing system generates and stores error correction information. When the program then executes a load instruction to retrieve the data from the memory location, the load instruction completes normally if there is no memory error. If, however, there is a memory error, the computing system passes control to the resiliency system (e.g., via a trap) to handle the memory error. The resiliency system retrieves the error correction information for the memory location and re-creates the data of the memory location. The resiliency system stores the data as if the load instruction had completed normally and passes control to the next instruction of the program.

Abstract: A memory device may be provided. The memory device may include an active control section configured to output a row active signal in response to a refresh signal when an active signal is activated. The memory device may include a refresh management section configured to control the refresh signal to skip a refresh operation for an unused row address in response to a refresh command signal and a refresh skip signal, and output an active row address for controlling the refresh operation. The memory device may include a memory section configured to perform a refresh operation for only an area of a cell array corresponding to a used row address in response to the row active signal and the active row address.

Abstract: Embodiments of the present disclosure provide a method and apparatus for handling the movement of a physical drive by generating a provision drive for a physical drive that is moved; establishing a connection from the provision drive to the physical drive; and updating the provision drive via the connection according to location information of the physical drive.

Abstract: A system includes a processing component and a memory controller. The memory controller is to conduct memory accesses to a banked memory responsive to memory access requests from the processing component, whereby the memory controller is to distribute memory accesses among the plurality of banks by modifying, for each memory access request, a bank of the bank memory referenced by the memory access request. A memory device includes a plurality of banks, an interface to receive memory access requests, bank remapping logic, and access control logic. The bank remapping logic is to, for each received memory access request, remap a bank segment of a memory address associated with the received memory access request with a modified bank segment. The access control logic is to, for each received memory access request, access a bank of the plurality of banks based on the modified bank segment for the memory access request.

Abstract: A semiconductor memory device includes a first memory area in the semiconductor memory device, and a second memory area in the semiconductor memory device. The second memory area is accessed independently of the first memory area based on a usage selecting signal. The first and second memory areas share command and address lines, and perform a rank interleaving operation based on the usage selecting signal.

Abstract: Embodiments include computing devices, apparatus, and methods implemented by the apparatus for time varying address space layout randomization. The apparatus may launch first plurality of versions of a system service and assign a random virtual address space layout to each of the first plurality of versions of the system service. The apparatus may receive a first request to execute the system service from a first application. The apparatus may randomly select a first version of the system service from the first plurality of versions of the system service, and execute the system service using data of the first version of the system service.

Abstract: An operating method for a dynamic random access memory (DRAM) obtains a plurality of first sub-commands of a first activate command via a command bus, and obtaining a plurality of first address information regarding a plurality of first portions of a first row address of a specific bank via an address bus. Each of the first sub-commands corresponds to an individual first portion of the first row address of the specific bank. The method further combines the first portions of the first row address of the specific bank in response to a specific sub-command of the first sub-commands, so as to obtain a first complete row address; and obtains an access command via the command bus.

Abstract: A method, information processing system, and computer program storage product optimize the placement of database objects on a multiplicity of storage devices. A set of database objects are placed on a first storage device in a multiplicity of storage devices. Each storage device comprises differing characteristics. A query workload is run on the set of database objects that have been placed on the first storage device. Profiling information associated with the query workload that is running is collected. A subset of database objects is selected from the set of the database objects to be stored on a second storage device. The subset of database objects is stored on the second storage device and all remaining database objects in the set of database objects on the first storage device.

Abstract: In one embodiment, a device includes: at least one processor; at least one sensor to sense an environmental condition; and a storage to store instructions that, when executed by the at least one processor, enable the device to: receive an encrypted nonce from a safety controller; decrypt the encrypted nonce using a value obtained from an entropy multiplexing seed tree generated by the device based at least in part on an initialization seed value received from the safety controller; responsive to decryption of the nonce, update a portion of a shared memory associated with the device to identify a safety state of the device; and encrypt a second nonce using the value obtained from the entropy multiplexing seed tree and send the encrypted second nonce to the safety controller. Other embodiments are described and claimed.

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.

Abstract: A memory subsystem includes a group of memory devices connected to an address bus. The memory subsystem includes logic to uniquely map a physical address of a memory access command to each memory device of the group. Thus, each physical address sent by an associated memory controller uniquely accesses a different row of each memory device, instead of being mapped to the same or corresponding row of each memory device.

Abstract: Memory corruption detection technologies are described. A system on a chip (SoC) may include a memory device and a memory controller. The memory device may store data from an application, wherein the memory device comprises a memory corruption detection (MCD) table. The memory controller may be coupled to the memory device. The memory controller may allocate a contiguous memory block in the memory and write a MCD word into the MCD table. The MCD word may include a write protection indicator that indicates a protection mode of a first portion of the contiguous memory block.

Abstract: Apparatuses and methods for writing and storing parameter codes for operating parameters, and selecting between the parameter codes to set an operating condition for a memory are disclosed. An example apparatus includes a first mode register and a second mode register. The first mode register is configured to store first and second parameter codes for a same operating parameter. The second mode register is configured to store a parameter code for a control parameter to select between the first and second parameter codes to set a current operating condition for the operating parameter. An example method includes storing in a first register a first parameter code for an operating parameter used to set a first memory operating condition, and further includes storing in a second register a second parameter code for the operating parameter used to set a second memory operating condition.

Abstract: In some embodiments, an apparatus includes a first controller configured to be operatively coupled within a network having a set of network nodes, a forwarding gateway and a configuration entity. The first controller is configured to manage session state and node state associated with the set of network nodes independent of the forwarding gateway. The first controller is configured to fail over to a second controller when the first controller fails, without the forwarding gateway failing over and without the configuration entity failing over.

Abstract: A memory device configured to emulate DRAM comprising a memory array that includes a plurality of memory cells organized into rows and columns with at least one row of memory cells comprising one or more pages that store data during a burst write operation; a control circuit; an encoder operable to encode the data to be written to the memory array; and a decoder coupled to the memory array and operable to check and correct the data previously encoded by the encoder and saved in the memory array. The control circuit is operable to initiate the burst write operation that writes the data to the memory array while spanning multiple clock cycles; and after receiving one or more data units of the data by the memory array, allow a subsequent burst write or read command to begin before completion of the burst write operation in progress.

Abstract: A storage control device includes: a detection unit that determines whether a preliminary process of saving data from a first memory to a second memory is necessary, where the second memory includes a suspend area and a typical area; a preliminary processing unit that writes a first value to the suspend area when the detection unit has determined that the preliminary process is necessary; and a saving processing unit that writes a second value corresponding to the data. The first value is different from the second value when the detection unit has determined that the preliminary process is necessary.

Abstract: The present disclosure includes apparatuses and methods related to performing comparison operations in memory. An example apparatus can include a first group of memory cells coupled to a first access line and configured to store a plurality of first elements, and a second group of memory cells coupled to a second access line and configured to store a plurality of second elements. The apparatus can include a controller configured to cause the plurality of first elements to be compared with the plurality of second elements by controlling sensing circuitry to perform a number of operations without transferring data via an input/output (I/O) line, and the plurality of first elements and the plurality of second elements can be compared in parallel.

Abstract: A memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes a plurality of dynamic memory cells. The memory controller controls the semiconductor memory device. The memory controller applies an auto-refresh command to the semiconductor memory device at each refresh interval of the semiconductor memory device such that the semiconductor memory performs a refresh operation in a normal mode, and does not apply the auto-refresh command to the semiconductor memory device during a self-refresh interval in which the semiconductor memory performs a self-refresh operation. After the semiconductor memory device exits from the self-refresh interval, the memory controller adjusts an application of the auto-refresh command in the normal mode by reflecting information of the self-refresh interval.

Abstract: The disclosed computer-implemented method for connecting purpose-built appliances to secure wireless networks may include (1) receiving, via an unsecured wireless network, an identifier from a network device that is not connected to a secure wireless network associated with the computing device, (2) sending, via the unsecured wireless network, a token to the network device, (3) receiving confirmation from a user of the network device that the network device correctly displayed the token and that the user would like to connect the network device to the secure wireless network, and (4) in response to the confirming that the user would like to connect the network device to the secure wireless network, sending, via the unsecured wireless network, network credentials for the secure wireless network to the network device to enable the network device to connect to the secure wireless network. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Examples of a multi-level memory with direct access are described. Examples include designating an amount of a non-volatile random access memory (NVRAM) for use as memory for a computer system. Examples also include designating a second amount of the NVRAM to for use as storage for the computing device. Examples also include re-designating at least a first portion of the first amount of NVRAM from use as memory to use as storage.

Abstract: Systems and methods for explicit organization of memory allocation on an integrated circuit (IC) are provided. In particular, a programmable logic designer may incorporate specific mapping requests into programmable logic designs. The mapping requests may specify particular mappings between one or more data blocks (e.g., memory buffers) of a host program to one or more physical memory banks.