Abstract: A memory controller that implements an interleaving and arbitration scheme includes an address decoder that selects a memory bank for an access request based on a set of address least significant bits included in the access request. A core requiring sequential access to memory is routed to consecutive memory banks of the memory for consecutive access requests. When multiple cores request access to the same memory bank, an arbiter determines an access sequence for the cores. The arbiter can modify the access sequence without significantly increasing the complexity of the memory controller. The address decoder determines whether the selected memory banks are available and also whether an access request is a wide access request, in which case it selects two consecutive memory banks.

Abstract: Apparatuses and methods for performing concurrent memory access operations for different memory planes are disclosed herein. An example apparatus may include a memory array having a plurality of memory planes. Each of the plurality of memory planes comprises a plurality of memory cells. The apparatus may further include a controller configured to receive a group of memory command and address pairs. Each memory command and address pair of the group of memory command and address pairs may be associated with a respective memory plane of the plurality of memory planes. The internal controller may be configured to concurrently perform memory access operations associated with each memory command and address pair of the group of memory command and address pairs regardless of page types associated with the pairs of the group (e.g., even if two or more of the memory command and address pairs may be associated with different page types).

Abstract: A convolutional neural network (CNN) for an image processing system comprises an image cache responsive to a request to read a block of N×M pixels extending from a specified location within an input map to provide a block of N×M pixels at an output port. A convolution engine reads blocks of pixels from the output port, combines blocks of pixels with a corresponding set of weights to provide a product, and subjects the product to an activation function to provide an output pixel value. The image cache comprises a plurality of interleaved memories capable of simultaneously providing the N×M pixels at the output port in a single clock cycle. A controller provides a set of weights to the convolution engine before processing an input map, causes the convolution engine to scan across the input map by incrementing a specified location for successive blocks of pixels and generates an output map within the image cache by writing output pixel values to successive locations within the image cache.

Abstract: A method and apparatus for controlling affinity of subcaches is disclosed. When a core compute unit evicts a line of victim data, a prioritized search for space allocation on available subcaches is executed, in order of proximity between the subcache and the compute unit. The victim data may be injected into an adjacent subcache if space is available. Otherwise, a line may be evicted from the adjacent subcache to make room for the victim data or the victim data may be sent to the next closest subcache. To retrieve data, a core compute unit sends a Tag Lookup Request message directly to the nearest subcache as well as to a cache controller, which controls routing of messages to all of the subcaches. A Tag Lookup Response message is sent back to the cache controller to indicate if the requested data is located in the nearest sub-cache.

Abstract: A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.

Abstract: A dynamic cache partitioning apparatus and method is described, which may be used in a multi-core system having a plurality of cores. The apparatus includes at least one multi-core processor and at least one shared cache shared by a plurality of processing cores, the shared cache including a plurality of cache lines and being partitioned into a plurality of sub-caches including at least one private sub-cache for each single processing core and at least one public sub-cache being shared by all of the processing cores; means for detecting shared cache hit information for each respective processing core of the plurality of processing cores; and means for determining whether a cache line should be allocated to public sub-cache or to a private sub-cache associated with one of the plurality of processing cores.

Abstract: A method to configure a storage library, comprising the steps of establishing a logical configuration for said storage library comprising a plurality of physical objects, by configuring a plurality of logical objects using a plurality of logical configuration commands, and adding that plurality of logical objects to the logical configuration. The method further adds the plurality of logical configuration commands to a Configuration Library, and saves that Configuration Library for later use.

Abstract: An array can include a controller and multiple storage devices of a first type. When a storage device of the first type is replaced by a replacement storage device of a second type, and other storage devices of the first type remain in the array, the controller instructs the replacement storage device to configure itself as a storage device of the first type. When the last storage device of the first type in the array is replaced by a replacement storage device of the second type, the controller instructs all the storage devices of the array to configure themselves as storage devices of the second type.

Abstract: Mechanisms are provided for importing pre-existing data into a storage system utilizing a current storage management system that is different from an original storage management system used to create the pre-existing data. One or more data storage devices are integrated into the storage system in-place without modification of the pre-existing data stored on the one or more data storage devices. Metadata for the pre-existing data is created based on a linear progression of data in the pre-existing data. Read access requests targeting the pre-existing data are executed using the created metadata. Write access requests targeting the pre-existing data are executed by redirecting the write access requests to a copy of the pre-existing data created in another storage location.

Abstract: Mechanisms are provided for importing pre-existing data into a storage system utilizing a current storage management system that is different from an original storage management system used to create the pre-existing data. One or more data storage devices are integrated into the storage system in-place without modification of the pre-existing data stored on the one or more data storage devices. Metadata for the pre-existing data is created based on a linear progression of data in the pre-existing data. Read access requests targeting the pre-existing data are executed using the created metadata. Write access requests targeting the pre-existing data are executed by redirecting the write access requests to a copy of the pre-existing data created in another storage location.

Abstract: An arbiter circuit and a translation circuit. The arbiter circuit may be configured to generate a first address signal in a virtual memory space by arbitrating among a plurality of clients to access a physical memory space. The clients may be classified as either privileged clients or non-privileged clients. The physical memory space may comprise at least one secure space. The secure space may be used to protect data of the privileged clients from being accessed by the non-privileged clients. The translation circuit may be configured to generate a second address signal by translating a page in the virtual memory space into the physical memory space. The page may correspond to a particular one of the clients that won the arbitration. The page may translate into the secure space if the particular client is one of the privileged clients. The page may also translate outside the secure space if the particular client is one of the non-privileged clients.

Abstract: A semiconductor system includes a first semiconductor device and a second semiconductor device. The first semiconductor device outputs command/address signals, data and a test mode signal. The first semiconductor device receives output data from the second semiconductor device. The second semiconductor device buffers the data inputted through a first pad to write the buffered data according to a combination of the command/address signals or inversely buffers the data to write the inversely buffered data if a control signal enabled in response to the test mode signal inputted through a second pad is inputted through a third pad.

Abstract: Techniques for using a host-side cache to accelerate virtual machine (VM) I/O are provided. In one embodiment, the hypervisor of a host system can intercept an I/O request from a VM running on the host system, where the I/O request is directed to a virtual disk residing on a shared storage device. The hypervisor can then process the I/O request by accessing a host-side cache that resides one or more cache devices distinct from the shared storage device, where the accessing of the host-side cache is transparent to the VM.

Abstract: A system and method for designing and constructing hierarchical memory systems is disclosed. A plurality of different algorithmic memory blocks are disclosed. Each algorithmic memory block includes a memory controller that implements a specific storage algorithm and a set of lower level memory components. Each of those lower level memory components may be constructed with another algorithmic memory block or with a fundamental memory block. By organizing algorithmic memory blocks in various different hierarchical organizations, may different complex memory systems that provide new features may be created.

Abstract: A method and apparatus are disclosed herein for retrieving network traffic data. In one embodiment, a networking apparatus comprises a memory; a network device; and a processing unit coupled to the network device and the memory. The processing unit is operable to execute a data engine that performs bulk data transfers from the network device periodically into a data buffer in the memory and translates data received from the network device, based on a mapping definition, into a user defined format for export to one or more applications running on networking apparatus.

Abstract: In one embodiment, an apparatus, such as a memory device, is disclosed. The apparatus includes multiple memory tiles and selection circuitry. Each memory tile has an array of storage components at intersections of a plurality of digit line conductors and a plurality of access line conductors. The selection circuitry includes line drivers that select a storage component of a memory tile based on a corresponding digit line conductor and a corresponding access line conductor to the storage component. The selection circuitry may select two or more storage components of a memory tile in a consecutive manner before selecting the storage components of a different memory tile.

Abstract: A memory device includes a magnetic memory unit for storing a burst of data during a burst write operation. Each burst of data includes sequential data units with each data unit being received at a clock cycle, and written during the burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data. Furthermore, the memory device allows a next burst write operation to begin while receiving data units of the burst of data to be written or providing read data.

Abstract: A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.

Abstract: Methods and apparatus for providing a network attached storage system which does not require specialized hardware to operate. In one embodiment, a downloadable software package is provided via a web interface. After a user has downloaded and installed the software package, a sharable volume is created upon a host system. In one embodiment, the sharable volume is adapted to present the contents of one or more remote systems to the host system as a local file, drive, or directory. One or more processes resident in the host system are adapted to intercept a command interpretable by the host system and translate the command into one or more commands interpretable by at least one remote system. The one or more commands are then serviced by at least one remote system and a result set is generated. The result set may then be converted into a format interpretable by the host system and output accordingly.

Abstract: A method of avoiding a write collision in single port memory devices from two independent write operations is described. A first data object from a first write operation is divided into a first even sub-data object and first odd sub-data object. A second data object from a second write operation is divided into a second even sub-data object and a second odd sub-data object. The first even sub-data object is stored to a first single port memory device and the second odd sub-data object to a second single port memory device when the first write operation and the second write operation occur at the same time. The second even sub-data object is stored to the first single port memory device and the first odd sub-data object to the second single port memory device when the first write operation and the second write operation occur at the same time.

Abstract: An example apparatus includes a row address register to store a row address corresponding to a row in a memory array. The example apparatus also includes a row decoder coupled to the row address register to assert a signal on a wordline of the row after the memory receives a column address. In addition, the example apparatus includes a column decoder to selectively activate a portion of the row based on the column address and the signal asserted on the wordline.

Abstract: A method of sampling data signals in response to a timing signal includes receiving data signals that are skewed relative to each other. Each data signal has a valid-data window having an extent such that, when a data signal is received, an invisible portion of the valid-data window is outside an observation window and a visible portion of the valid-data window is inside the observation window. The method further includes, for each of the data signals, identifying a designated location within the valid-data window that is part way across the extent of the valid-data window, and for each of the data signals, aligning the data signal such that the designated location aligns with the timing signal.

Abstract: Systems and methods are provided that facilitate memory storage in a multi-bank memory device. The system contains a memory controller and a memory array communicatively coupled to the memory controller. The memory controller sends commands to the memory array and the memory array updates or retrieves data contained therein based upon the command. If the memory controller detects a pattern of memory requests, the memory controller can issue a preemptive activation request to the memory array. Accordingly, memory access overhead is reduced.

Abstract: An apparatus includes an interface and a processor. The interface is configured to communicate with multiple memory devices over a bus that includes a plurality of parallel data lines. The processor is configured to request the memory devices to provide respective status reports, and to receive the status reports from the memory devices such that, in a given clock cycle of the bus, the multiple status reports from the respective memory devices are received in parallel over respective different subsets of the data lines of the bus.

Abstract: A memory module may have a redrive circuit having a plurality of redrive paths, a memory device, and a deskew circuit. The deskew circuit may be separate from the plurality of redrive paths. The deskew circuit may be coupled between the plurality of redrive paths and the memory device to selectively deskew data received in the redrive circuit.

Abstract: A network processor includes multiple processor cores for processing packet data. In order to provide the processor cores with access to a memory subsystem, an interconnect circuit directs communications between the processor cores and the L2 Cache and other memory devices. The processor cores are divided into several groups, each group sharing an individual bus, and the L2 Cache is divided into a number of banks, each bank having access to a separate bus. The interconnect circuit processes requests to store and retrieve data from the processor cores across multiple buses, and processes responses to return data from the cache banks. As a result, the network processor provides high-bandwidth memory access for multiple processor cores.

Abstract: A method reduces a cycle time of an individual memory module to an effective cycle time shorter than the cycle time using a plurality of memory modules having a circular sequence. The method includes initiating a set of read operations on different memory modules of the plurality of memory modules in the circular sequence from a first read operation initiated on a first module of the plurality of memory modules to a last read operation initiated on the second module. After initiating each read operation of the set of read operations on a particular memory module of the plurality of memory modules and prior to initiating a next read operation in the set of read operations, the method initiates a set of write operations to write a same value to all of the plurality of memory modules in the circular sequence beginning one memory module after the particular memory module.

Abstract: A semiconductor memory device includes a memory cell array, a refresh control circuit, an address counter and an address converter. The memory cell array includes a plurality of memory cells. The refresh control circuit is configured to receive a refresh command and output m refresh control signals during one refresh cycle for refreshing all the memory cells of the semiconductor memory device. The address counter is configured to generate counting signals for refreshing memory cells in response to the m refresh control signals. The address converter is configured to receive the counting signals and output refresh addresses by converting the counting signals in response to a cycle select signal. The address converter is configured to output refresh addresses such that the number of m refresh control signals during one refresh cycle is variable.

Abstract: Hardware processors in an SOC integrated circuit logically swapping memories by remapping memory addresses, including tightly coupled and local memories, to enable a sequence of data-processing algorithms to execute more quickly by different hardware processors without having to copy the data between different memories using a relatively slow data crossbar switch. When a memory stores error-correction code (ECC) address information linking stored ECC data with stored user data, the hardware processor dynamically remaps the ECC address information, as needed.

Abstract: A method, apparatus, and system are described, which generally relate to an interconnect routing transactions to target IP cores, including two or more channels making up a first aggregate target. The two or more channels populate an address space assigned to the first aggregate target and appear as a single target to the initiator IP cores. The interconnect implements chopping logic to chop an individual transaction from a first initiator IP core whose address sequence crosses a channel address boundary from a first channel to a second channel within the first aggregate target into two or more burst transactions. A first chopped burst transaction is chopped to fit within the address boundaries of the first channel and a second chopped burst transaction is chopped to fit within the address boundaries of the second channel.

Abstract: A method for making memory more reliable involves accessing data stored in a removable storage device by translating a logical memory address provided by a host digital device to a physical memory address in the device. A logical memory address is received from the host digital device. The logical memory address corresponds to a location of data stored on the removable storage device. A physical memory address corresponding to the local address is determined by accessing a lookup table corresponding to the logical zone.

Abstract: A mechanism implemented by a controller enables efficient access to an interleaved memory system that includes M modules, M being (2n+1) or (2n?1), n being a positive integer number. Upon receiving an address N, the controller performs shift and add/subtract operations to obtain a quotient of N divided by M based on a binomial series expansion of N over M. The controller computes a remainder of N divided by M based on the quotient. The controller then accesses one of the modules in the memory based on the remainder.

Abstract: Methods, and apparatus configured to perform methods, including loading trim settings into a trim register of a memory device associated with a command for an access operation, receiving the command for the access operation at the memory device, setting trims for the access operation in response to the trim settings of the trim register associated with the command for the access operation, and performing the access operation using the trims for the access operation; and including performing an access operation on a memory device using trims corresponding to trim settings, receiving a command to suspend the access operation, loading updated trim settings into a particular trim register of the memory device, setting updated trims for the access operation in response to the updated trim settings of the particular trim register, and resuming the access operation using the updated trims.

Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

Abstract: A memory device includes a magnetic memory unit for storing a burst of data during burst write operations, each burst of data includes, sequential data units with each data unit being received at a clock cycle, and written during a burst write operation, wherein the burst write operation is performed during multiple clock cycles. Further, the memory device includes a mask register coupled to the magnetic memory unit that generates a write mask during the burst write operation to inhibit or enable data units of write data, furthermore the memory device allowing burst write operation to begin while receiving data units of the next burst of data to be written or providing read data.

Abstract: In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.

Abstract: An apparatus for processing data 2 includes a memory 4 having a plurality of memory regions 28 to 38. A mapping controller 56 applies a variable mapping to map memory addresses of access requests to different regions within the memory 4. The mapping controller varies the mapping applied in dependence upon both one or more memory behavioral parameters indicative of behavioral characteristics of the different regions and one or more access behavioral parameters indicative of behavioral characteristics of an access request to be mapped. The memory behavioral parameters may include the temperature of the regions and/or the refresh period of the regions. The access behavior able parameters may include the quality of service level, the access frequency, the access volume and/or the identity of the source of the access request.

Abstract: The embodiments described herein provide a system and method for efficiently storing small, random modifications or changes to data on one or more storage devices, such as disks, of storage servers coupled to a host computer in a network environment. Illustratively, the data is stored in a region of a byte-addressable, persistent memory of the host computer and is replicated (i.e., copied) as changed data of the region on the disks at the granularity at which it was modified, e.g., at the byte-addressable granularity. To that end, each storage server employs a data structure (e.g., a Fibonacci array) that is configured to efficiently accumulate the small, random data changes into one or more large blocks of changed data for storage on the disks in a manner that realizes the streaming bandwidth of the disk.

Abstract: A microcontroller system can operate in a number of power modes. In response to changing from a previous mode to a present mode, the microcontroller system reads a present calibration value correspond to the present mode from system configuration storage and write the present calibration value to a configuration register for a component. A logic block for the component reads the present calibration value and calibrates the component.

Abstract: A microprocessor or microcontroller device may have a central processing unit (CPU), a data memory coupled with the CPU, wherein the data memory is divided into a plurality of memory banks, wherein a bank select register determines which memory bank is currently coupled with the CPU. Furthermore, a first and second set of special function registers are provided, wherein upon occurrence of a context switch either the first or the second set of special function register are selected as active context registers for the CPU and the respective other set of special function registers are selected as inactive context registers, wherein at least some of the registers of the active context registers are memory mapped to more than two memory banks of the data memory and wherein all registers of the inactive context registers are memory mapped to at least one memory location within the data memory.

Abstract: A processing node in a temporal memory system includes a spatial pooler and a sequence processor. The spatial pooler generates a spatial pooler signal representing similarity between received spatial patterns in an input signal and stored co-occurrence patterns. The spatial pooler signal is represented by a combination of elements that are active or inactive. Each co-occurrence pattern is mapped to different subsets of elements of an input signal. The spatial pooler signal is fed to a sequence processor receiving and processed to learn, recognize and predict temporal sequences in the input signal. The sequence processor includes one or more columns, each column including one or more cells. A subset of columns may be selected by the spatial pooler signal, causing one or more cells in these columns to activate.

Abstract: Systems and methods are provided for managing access to registers. A system may include a set of direct registers and a set of indirect registers. The indirect registers may be accessed through the direct registers, and the direct registers may provide various features to provide faster access to the indirect registers. One of the direct registers may indicate access modes for accessing the indirect registers. The access modes may include auto-increment, auto-decrement, auto-reset, and no change modes. Based on the access mode, the currently accessed address may be automatically modified after accessing the indirect register at the address.

Abstract: One embodiment relates to a frame detection circuit for detecting a frame boundary. The circuit includes at least two frame buffers and a staged-parallel structure of syndrome computation circuits that computes a number of syndromes in one cycle. The two frame buffers are each one word in width. The number of syndromes computed in one cycle by the cascaded series is a fraction of a number of bits in one word. Another embodiment relates to a method for detecting a frame boundary. Another embodiment relates to a method for computing a current syndrome. Other embodiments, aspects, and features are also disclosed.

Abstract: A method, information processing system, and computer program storage product optimize the placement of database objects on a multiplicity of storage devices. A set of database objects are placed on a first storage device in a multiplicity of storage devices. Each storage device comprises differing characteristics. A query workload is run on the set of database objects that have been placed on the first storage device. Profiling information associated with the query workload that is running is collected. A subset of database objects is selected from the set of the database objects to be stored on a second storage device. The second storage device is a separate physical device from, and performs faster than, the first storage device. The subset of database objects is stored on the second storage device and all remaining database objects in the set of database objects on the first storage device.

Abstract: A method of an aspect includes receiving a request to move between filemarks at a network interface. A filemark cache is accessed with an offset into an open virtual tape file based on the received request. A determination is made that the offset is in the filemark cache. Filemark metadata corresponding to the offset is read from the filemark cache. The filemark cache is separate from the open virtual tape file. Other methods, apparatus, and articles are also disclosed.

Abstract: In a hybrid memory system that includes a host memory controller and a non-volatile memory DIMM, where the DIMM is coupled to the host memory controller by a memory bus, the DIMM includes non-volatile memory, a DIMM bus adapter, and a local memory controller, the local memory controller is configured to control memory accesses within the DIMM, the DIMM bus adapter is configured to adapt the local memory controller to the bus for memory communications with the host memory controller in accordance with a bus protocol, bus resiliency may be provided by: discovering, by the DIMM bus adapter, a memory error in the DIMM; providing, by the DIMM bus adapter to the host memory controller, an indication of an error by emulating a hardware error native to the bus protocol; and performing, by the host memory controller, one or more resiliency measures responsive to the indication of the error.

Abstract: Embodiments relate to address mapping including generic bits. An aspect includes receiving an address including generic bits from a memory control unit (MCU) by a buffer module in a main memory. Another aspect includes mapping the generic bits to an address format corresponding to a type of dynamic random access memory (DRAM) in a memory subsystem associated with the buffer module by the buffer module. Yet another aspect includes accessing a physical location in the DRAM in the memory subsystem by the buffer module based on the mapped generic bits.

Abstract: A system and method for mapping an address space to a non-power-of-two number of memory channels. Addresses are translated and interleaved to the memory channels such that each memory channel has an equal amount of mapped address space. The address space is partitioned into two regions, and a first translation function is used for memory requests targeting the first region and a second translation function is used for memory requests targeting the second region. The first translation function is based on a first set of address bits and the second translation function is based on a second set of address bits.

Abstract: In a terminal device, contents data from an attachment mounted on the device is received by a transmission/reception section and replayed by a first playback section. A detection section detects the mounting or removing of the attachment during the playback of the contents data. As an output destination for the contents data, a selection section selects the first playback section when the attachment has been mounted, or selects a first storage section when the attachment has been removed. In the attachment, the contents data is outputted to one of the first storage section and the first playback section based on the selection result of the terminal device. Accordingly, the usage mode of contents data can be readily changed with the mounting or removing of an attachment as a trigger.

Abstract: A method for optimizing memory bandwidth using bank-based memory allocation is described. The method includes receiving a request for an allocation of memory. In response to receiving the request, memory is allocated to the request based on a performance ranking of memory banks in a plurality of memory banks. A performance ranking of a particular memory bank may be based at least in part on both a busyness and a row hit ratio of the particular memory bank. Apparatus and computer readable media are also described.