For Multiple Memory Modules (e.g., Banks, Interleaved Memory) Patents (Class 711/5)
  • Patent number: 7062597
    Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: June 13, 2006
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern
  • Patent number: 7062630
    Abstract: A storing device can reduce the frequency of the saving operation at a step of rewriting data on the storing mediums. Where q is a size of all the data to write in storing mediums, m is the number of the storing mediums, and p is each block size, a quotient expressed by zm+w+y(z: 0?z (integer); w: 0?w<m (integer); y: 0?y<1) is calculated by dividing q by p. It is configured so that the data for zm blocks is written in parallel on m storing mediums, and then the data for q/p?zm blocks is written on w+1 storing mediums (win the case of y=0).
    Type: Grant
    Filed: October 26, 2001
    Date of Patent: June 13, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Toshihiko Otake, Tsutomu Sekibe
  • Patent number: 7058756
    Abstract: Disclosed is a circuit for implementing a special mode in a packet-based semiconductor memory device, which performs the special mode in the same manner as a normal operation without changing the semiconductor memory devie from a special mode register to a control register mode prior to a normal operation or at the middle of the normal operation after an initial operation having a reset operation. A packet receiving part receives external packet data. A register controller generates a control signal to select a special mode register according to a value of a first field among the external packet data received by the packet receiving part. A register value generator generates a value of the special mode register selected by the control signal from the register controller according to a value of a second field among the received external packet data when the register controller generates the control signal.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: June 6, 2006
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nak Kyu Park
  • Patent number: 7055012
    Abstract: A method of selecting CAS latencies in a system. Specifically, a system which includes a plurality of memory devices and a memory controller is provided. Because different memory devices may have different CAS latencies, a system CAS latency is selected wherein the system CAS latency is the fastest common CAS latency of each of the plurality of memory devices. After a read request is delivered to a memory device, the memory controller initiates a transmission flag to the memory device at a time equal to the system CAS latency, indicating that it is safe to transmit the requested data from the memory device to the memory controller. The transmission flags may be used in conjunction with mode registers such that one or both of the transmission flag and the data may be received by or delivered by a corresponding memory device.
    Type: Grant
    Filed: August 31, 2004
    Date of Patent: May 30, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Paul A. LaBerge, Jeff W. Janzen
  • Patent number: 7051178
    Abstract: A synchronous flash memory has been described that includes an array of non-volatile memory cells. The memory device has a package configuration that is compatible with an SDRAM. The synchronous flash memory device includes an array of non-volatile memory cells arranged in a plurality of rows and columns. During a read operation, a row of the memory array can be accessed and data written to a group of columns during a burst write operation. The burst columns are generated using an internal counter and an externally provided start address. Repeating sequences of commands and data packets are provided to the memory device. An externally provided data mask signal is used to write one of the data packets to the memory on each of the sequences.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: May 23, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Frankie F. Roohparvar
  • Patent number: 7051171
    Abstract: A deinterleaver for performing high-speed multi-channel forward error correction using external SDRAM is provided. According to one exemplary aspect, the deinterleaver performs both read and write accesses to the SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The data bus length of the SDRAM is designed to be twice the deinterleaving symbol size thereby allowing bandwidth to be increased. The deinterleaver accesses data in the SDRAM as read blocks and write blocks. Each block includes a predetermined number of data words to be interleaved/deinterleaved. The ACTIVE command for one block is issued when a preceding block is being processed. Data in one read/write block has the same row address within the same bank of the SDRAM.
    Type: Grant
    Filed: April 11, 2003
    Date of Patent: May 23, 2006
    Assignee: BroadLogic Network Technologies, Inc.
    Inventors: Binfan Liu, Zhongqiang Wang, Thomas Ayers
  • Patent number: 7051151
    Abstract: An integrated circuit buffer device including a first port and a second port. The first port to receive data from a first integrated circuit memory device, and the second port to receive data from a second integrated circuit memory device. The integrated circuit buffer device further includes a multiplexer to output a data stream that includes the data received from the first integrated circuit memory device and the data received from the second integrated circuit memory device. In addition, the integrated circuit buffer device includes an interface including transmit circuitry to transmit the data stream to an integrated circuit controller device.
    Type: Grant
    Filed: October 15, 2002
    Date of Patent: May 23, 2006
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern
  • Patent number: 7047385
    Abstract: A memory integrated circuit includes an array of high-speed memory blocks coupled to the address input interface and data output interface of the integrated circuit by address and data pipelines clocked at the same rate as the high-speed memory blocks. After an initial read latency, data is read from the memory at the same speed it is read from the high-speed memory blocks.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: May 16, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Dipankar Bhattacharya, Jeff Hirschman
  • Patent number: 7047351
    Abstract: A computer system and a method used to access data from a plurality of memory devices with a memory hub. The computer system includes a plurality of memory modules coupled to a memory hub controller. Each of the memory modules includes the memory hub and the plurality of memory devices. The memory hub includes a sequencer and a bypass circuit. When the memory hub is busy servicing one or more memory requests, the sequencer generates and couples the memory requests to the memory devices. When the memory hub is not busy servicing multiple memory requests, the bypass circuit generates and couples a portion of each the memory requests to the memory devices and the sequencer generates and couples the remaining portion of each of the memory requests to the memory devices.
    Type: Grant
    Filed: January 21, 2005
    Date of Patent: May 16, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Joseph M. Jeddeloh
  • Patent number: 7047371
    Abstract: An integrated memory has at least two connection panels, which can be operated independently of one another, for external communication by the memory. In addition, a control circuit produces a number of first control signals and a number of second control signals for external tap-off. The number of first control signals corresponds to a number of memory banks. The first control signals are each associated with a memory bank and indicate that an associated memory bank is being accessed. The number of second control signals corresponds to the number of connection panels. One of the second control signals is produced if an access collision occurs between access to one of the memory banks via one connection panel and access to the same memory bank via another connection panel. Two processor units are connected to the connection panels and access the memory independently of one another on the basis of the control signals.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: May 16, 2006
    Assignee: Infineon Technologies AG
    Inventor: Jean-Marc Dortu
  • Patent number: 7043598
    Abstract: In a memory device with a bank of N memory blocks, an address is generated for a first and a second one of the blocks. The first and second addresses include addresses for current first and second possible “refresh blocks”. If its memory block does not contend with the current first possible refresh block, an externally generated access to one of the N memory blocks is permitted and at least a portion of the refresh block is refreshed during a certain interval. In another aspect, the externally generated access is permitted and at least a portion of the current second possible refresh block is refreshed during the same certain interval if: i) the memory block of the externally generated access contends with the current first possible refresh block and ii) the current first and second possible refresh blocks are different ones of the N memory blocks.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: May 9, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chuan-Yu Wu, Jia-Ming Yang, Chris Huang
  • Patent number: 7043617
    Abstract: A system is capable of receiving Fast Page mode, Extended Data Out mode, Burst Extended Data Out mode, or a combination of these memory devices. A method of determining the type of memory present allows the system to adjust internal memory access signals in accordance with the type of memory installed. The system may be shipped with a first type of memory, and then upgraded to a second type of memory by the user to improve overall system performance. A first bank of memory may be of a first type, and a second bank may be of another type. The user may make cost versus performance decisions when upgrading memory types or capacities.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: May 9, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Brett L. Wiliams
  • Patent number: 7038964
    Abstract: Access of multiple data processing circuits to a common memory having several banks is managed, the memory being connected to one or several circuits for processing ordinary data and to a circuit for processing priority data. A method of managing access includes producing an access demand of a circuit for processing ordinary data to a bank of the memory, starting the realization of the demanded access, subsequently producing an access demand of the circuit for processing priority data to another bank of the memory, preparing, during the realization of the access demanded by the ordinary data processing circuits, the other bank of the memory, and interrupting the access in the course of realization as soon as said preparation is completed.
    Type: Grant
    Filed: May 21, 2002
    Date of Patent: May 2, 2006
    Assignee: Koninklijke Philips Electronics N.V.
    Inventors: Stephane Mutz, Hugues De Perthuis, Thierry Gourbilleau
  • Patent number: 7035161
    Abstract: An I/O interface circuit immediately close to a bank having a plurality of memory cells and an I/O circuit is directly connected to data line pairs via a switching circuit. Another I/O interface circuit is connected to other data line pairs via switching circuits and data bus pairs. Consequently the number of lines of the data bus pairs provided within the chip of the semiconductor integrated circuit is half of the number in the prior art, and the chip area can be reduced.
    Type: Grant
    Filed: December 10, 2003
    Date of Patent: April 25, 2006
    Assignee: OKI Electric Industry Co., Ltd.
    Inventor: Mineo Noguchi
  • Patent number: 7035962
    Abstract: A memory system having at least one memory subsystem and using a packet protocol communicated over a command and address bus and at least one data bus. The memory subsystems are pipelined to achieve wide data paths and to support a high number of memory devices, such as dynamic random access memory devices, per data bus. The packet protocol is defined to compensate for the delay stages of the pipelined memory subsystem in order to optimize the access time of the memory devices.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: April 25, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Kevin J. Ryan
  • Patent number: 7028209
    Abstract: A bus repeater with voltage conversion and multiplexing circuits for use between devices with incompatible voltage levels communicating over inter-integrated circuit (I2C) buses. Bi-directional data and clock lines are passed through the circuit from one bus to the other, blocked so they are not passed on, or modified before being passed on, depending on the current transaction. The repeater is placed between two separate I2C buses and communicates between the two buses. To accommodate the slow-slave requirements of an I2C bus, the duration of signals on the clock line may be modified.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: April 11, 2006
    Assignee: Intel Corporation
    Inventors: Daniel A. Mosley, Michael J. McTague
  • Patent number: 7028156
    Abstract: In a system in which read data tracking and caching is used to recover from data corruption, a first request to read data from a primary data mirror is received from a computer system. Data is read from the primary data mirror in response to receiving the first request. Additionally data from a mirrored copy of the primary data mirror is read. Data read from the primary data mirror is returned to the computer system. Data read from the mirrored copy is stored into a memory device. If a second request is received from the computer system to read the same data of the first request, data stored in the memory device may be returned in response thereto.
    Type: Grant
    Filed: July 1, 2003
    Date of Patent: April 11, 2006
    Assignee: VERITAS Operating Corporation
    Inventors: Oleg Kiselev, Ronald S. Karr
  • Patent number: 7024578
    Abstract: A memory apparatus includes a memory module array having several memory modules. Each memory module has a synchronization connection for receiving a synchronization signal for synchronizing the memory module relative to the other memory modules in the memory module array. This enables combining data bursts read from the memory modules into a data stream.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: April 4, 2006
    Assignee: Infineon Technologies AG
    Inventor: Wolfgang Nikutta
  • Patent number: 7024515
    Abstract: Methods and apparatus are disclosed for use with an associative memory, such as for, but not limited to implementing access control list and quality of service features in a communications or computing device. Multiple lists, such as access control lists, may be manipulated to typically produce a single list of entries with continuation indications, or the lists might be provided from another source. An associative memory is programmed with entries with each entry typically including a corresponding continuation level indication or flag. One or more lookup words are then generated and provided to the associative memory for a particular packet (or other entity) corresponding to the different continuation levels. In one implementation, a modified version of the Order Dependent Merge technique is used to generate the list of entries and to identify the corresponding continuation level or other continuation indication and the corresponding action to be performed for each entry.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: April 4, 2006
    Assignee: Cisco Technology, Inc.
    Inventors: Yixing Ruan, Chran Ham Chang, Pranav Dharwadkar, Hari Lalgudi
  • Patent number: 7020736
    Abstract: A method and apparatus for sharing memory space of multiple memory units by multiple processing units are described. In an embodiment, a method includes storing a set of data across more than one of at least two memory units upon determining that the number of sets of data is static. The method also includes storing the set of data within a single memory unit of the at least two memory units upon determining that the set of data is dynamic.
    Type: Grant
    Filed: December 18, 2000
    Date of Patent: March 28, 2006
    Assignee: Redback Networks Inc.
    Inventor: Ravikrishna Cherukuri
  • Patent number: 7020739
    Abstract: An object of the present invention is to provide a memory controller that can perform a series of data write operations so as to complete the data writing at high speed. A memory controller includes means for dividing the physical blocks into a plurality of groups, means for forming a plurality of virtual blocks by virtually combining a plurality of physical blocks each of which belongs to a different group, and means for assigning adjacent host addresses to different physical blocks belonging to the same virtual block. Thus, when a host computer issues a request to access the plurality of successive host addresses, the physical blocks to be accessed are different physical blocks. Since the physical blocks to be accessed can therefore operate independently, a series of operations can be performed in parallel.
    Type: Grant
    Filed: December 5, 2001
    Date of Patent: March 28, 2006
    Assignee: TDK Corporation
    Inventors: Naoki Mukaida, Kenzo Kita, Yukio Terasaki
  • Patent number: 7020737
    Abstract: A memory device for multichannel continuous or fixed burst mode operation includes multiple burst address counter circuits and associated control logic to minimize latency which would otherwise occur in multichannel operation.
    Type: Grant
    Filed: February 13, 2003
    Date of Patent: March 28, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Giuliano Gennaro Imondi, Maurizio Di Zenzo, Mario Antonio Fazio
  • Patent number: 7020757
    Abstract: A memory subsystem includes multiple memory modules coupled by point-to-point links. A memory controller is coupled by a point-to-point link to a first memory module, which is turn is coupled by another point-to-point link to another memory module. Further memory modules may be coupled by respective point-to-point links in the memory subsystem. In some arrangements, each memory module tracks commands issued to other memory modules, such as more upstream memory modules. Also, in one example implementation, a clock is embedded within a data stream transmitted over a point-to-point link, so that an external clock is not employed in this example implementation.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: March 28, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Michael Ruhovets, Christopher C. Wanner
  • Patent number: 7020758
    Abstract: The invention relates to methods and associated systems for managing application workloads and data storage resources. Data storage resources my be mapped to logical addresses associated with applications based on the I/O activity associated with those addresses. Techniques are disclosed for determining the I/O capacity of a data storage resource for a given workload and allocating resources according to administrator requirements. Various physical devices may be mapped to logical addresses by defining a composite volume for the application. The invention may be implemented as a transparent layer between the application and the data storage resource, for example, in the file system.
    Type: Grant
    Filed: September 18, 2002
    Date of Patent: March 28, 2006
    Assignee: Ortera Inc.
    Inventor: David C. Fisk
  • Patent number: 7017002
    Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems. The master communicates to the plurality of memory devices in each memory subsystem through the respective buffer device via each point-to-point link.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: March 21, 2006
    Assignee: Rambus, Inc.
    Inventors: Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern
  • Patent number: 7017017
    Abstract: In some embodiments, a memory controller includes first and second memory channel interfaces and memory access control circuitry. The memory access control circuitry is to send first and second primary data sections to the first and second memory channel interfaces, respectively, and send first and second redundant data sections to the second and first memory channel interfaces, respectively. The first and second redundant data sections are redundant with respect to the first and second primary data sections, respectively. Other embodiments are described and claimed.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: March 21, 2006
    Assignee: Intel Corporation
    Inventors: Eric J. Dahlen, Warren R. Morrow, Peter D. Vogt
  • Patent number: 7010654
    Abstract: Methods and systems for re-ordering commands to access memory are disclosed. Embodiments may receive a first command to access a memory bank of the memory and determine a penalty associated with the first command based upon a conflict with an access to the memory bank. The penalty, in many embodiments, may be calculated so the penalty expires when the memory bank and a data bus associated with the memory bank are available to process the first command. Then, the first command is queued and dispatched to an available sequencer after the penalty expires. After the first command is serviced, unexpired penalties of subsequent commands may be updated to reflect a conflict with the first command. Further embodiments select a command to dispatch from the commands with expired penalties, based upon priorities associated with the commands such as the order in which the commands were received and the command types.
    Type: Grant
    Filed: July 24, 2003
    Date of Patent: March 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Herman L. Blackmon, Joseph A. Kirscht, James A. Marcella, Brian T. Vanderpool
  • Patent number: 7010656
    Abstract: In some embodiments, an electronic device includes a processor, a physical memory coupled to the processor, and a storage medium coupled to the processor. The storage medium may store instructions which when executed by the processor cause the processor to: survey at least a portion of the physical memory, determine an amount of free memory space and used memory space based on the survey of the physical memory, determine if a consolidation of used memory space should be performed, and, if so determined, consolidate the used memory space, and reduce the power provided to at least a portion of the physical memory following the consolidation of used memory space. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: March 7, 2006
    Assignee: Intel Corporation
    Inventor: Vivek G. Gupta
  • Patent number: 7010642
    Abstract: A memory system architecture/interconnect topology that includes at least one point-to-point link between a master, and at least one memory subsystem. The memory subsystem includes a buffer device coupled to a plurality of memory devices. The memory system may be upgraded through dedicated point-to-point links and corresponding memory subsystems.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: March 7, 2006
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern
  • Patent number: 7007130
    Abstract: A system that has a system memory controller and a memory module. The memory module includes a memory module controller coupled to the system memory controller and a plurality of memory devices coupled to the memory module controller.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: February 28, 2006
    Assignee: Intel Corporation
    Inventor: Thomas J. Holman
  • Patent number: 7003639
    Abstract: A memory controller controls access to, and the power state of a plurality of dynamic memory devices. A cache in the memory controller stores entries that indicate a current power state for a subset of the dynamic memory devices. Device state lookup logic responds to a memory access request by retrieving first information from an entry, if any, in the cache corresponding to a device address in the memory access request. The device state lookup logic generates a miss signal when the cache has no entry corresponding to the device address. It also retrieves second information indicating whether the cache is currently storing a maximum allowed number of entries for devices in a predefined mid-power state. Additional logic converts the first and second information and miss signal into at least one command selection signal and at least one update control signal. Cache update logic updates information stored in the cache in accordance with the at least one update control signal.
    Type: Grant
    Filed: June 21, 2004
    Date of Patent: February 21, 2006
    Assignee: Rambus Inc.
    Inventors: Ely K. Tsern, Ramprasad Satagopan, Richard M. Barth, Steven C. Woo
  • Patent number: 7003640
    Abstract: An information server with power-aware adaptation that enables power reduction while minimizing the performance impact of power reduction. An information server according to the present techniques includes a transaction prioritizer that determines which of a set of memory subsystems in the information server is to cache a set of data associated with each incoming information access transaction and further includes a power manager that performs a power adaptation in the information server in response to a set of ranks assigned to the memory subsystems. An association of priorities of the incoming information access transactions to appropriately ranked memory subsystems and the judicious selection of memory subsystems for power adaptation enhances the likelihood that higher priority cached data is not lost during power adaptation.
    Type: Grant
    Filed: July 28, 2003
    Date of Patent: February 21, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Robert N. Mayo, Parthasarathy Ranganathan, Robert J. Stets, Jr., Deborah A. Wallach
  • Patent number: 7003618
    Abstract: A computer system includes a controller device having an interface disposed on a circuit board. A first socket is disposed on the circuit board and receives a first memory module having a first integrated circuit buffer device. The first memory module has a first plurality of integrated circuit memory devices coupled to the first integrated circuit buffer device. A first point-to-point link is coupled to the interface of the controller device. When the first memory module is received by the first socket, the first integrated circuit buffer device receives control information, address information, and data from the controller device over the first point-to-point link. A second socket is disposed on the circuit board and receives a second memory module having a second integrated circuit buffer device. The second memory module has a second plurality of memory devices coupled to the second integrated circuit buffer device.
    Type: Grant
    Filed: March 11, 2005
    Date of Patent: February 21, 2006
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern
  • Patent number: 7003622
    Abstract: A semiconductor memory includes a redundant RAM disposed independently of at least one regular RAM, the redundant RAM having redundant memory elements by which defective memory elements of the regular RAM can be replaced, and a control block for selecting either at least the regular RAM or the redundant RAM according to an address applied thereto, and for reading data from a memory cell of the selected RAM specified by the address. A plurality of regular RAMs can be disposed and the redundant RAM includes redundant memory elements by which defective memory elements of an arbitrary one of the plurality of regular RAMs can be replaced. The control block selects either one of the plurality of regular RAMs or the redundant RAM according to an address applied thereto, and reads data from a memory cell of the selected RAM specified by the address.
    Type: Grant
    Filed: June 12, 2002
    Date of Patent: February 21, 2006
    Assignee: Renesas Technology Corp.
    Inventors: Hirofumi Shinohara, Yoshiki Tsujihashi, Takeshi Hashizume
  • Patent number: 7003630
    Abstract: A method and apparatus within a processing environment is provided for proxy management of a plurality of proxy caches connected to a plurality of processing elements or cores within a unified memory environment. The proxy management system includes a proxy processor, such as a RISC core, that monitors data transfers or ownership transfers between the processing elements. If the proxy processor determines that a data transfer in one of the proxy caches will affect the coherency within another proxy cache, the proxy processor executes proxy management instructions such as invalidate, flush, prefetch to the appropriate proxy caches to insure coherency between the proxy caches and the unified memory.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: February 21, 2006
    Assignee: MIPS Technologies, Inc.
    Inventor: Kevin D. Kissell
  • Patent number: 7000062
    Abstract: A system comprises a master device and a first integrated circuit buffer device. A first plurality of integrated circuit memory devices are coupled to the first integrated circuit buffer device. A first plurality of signal lines are coupled to the first integrated circuit buffer device and the master device, wherein the first plurality of signal lines communicate control information, address information and data from the master device to the first integrated circuit buffer device. A second plurality of signal lines are coupled to the first integrated circuit buffer device. A second integrated circuit buffer device is coupled to the second plurality of signal lines, the second integrated circuit buffer device receives the control information, the address information and the data from the first integrated circuit buffer device over the second plurality of signal lines. A second plurality of integrated circuit memory devices are coupled to the second integrated circuit buffer device.
    Type: Grant
    Filed: February 10, 2005
    Date of Patent: February 14, 2006
    Assignee: Rambus Inc.
    Inventors: Richard E. Perego, Stefanos Sidiropoulos, Ely Tsern
  • Patent number: 7000089
    Abstract: The assignment of an address to a transaction for serialization purposes is disclosed. A simulated address is assigned to a transaction of a first type. The simulated address may be determined by selecting a mask based on one or more bits of a command type attribute of the transaction, and performing a logical OR operation on the highest bits of the mask with a number of bits determined by concatenating various bits of various attributes of the transaction. The lowest bits of the resulting simulated address can be incremented for each transaction assigned a simulated address having the same highest bits. The transaction is serialized relative to other transactions of the first type, such as I/O-related transactions, utilizing a serialization approach for transactions of a second type. The serialization approach may be an existing approach already used to serialize transactions of the second type, such as coherent transactions.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: February 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: William Durr, Bruce M. Gilbert, Robert Joersz
  • Patent number: 6996607
    Abstract: A storage subsystem that directly interfaces with a network, provides connections for routers with a conventional multi-path function, and performs access load balancing among a plurality of input/output ports. Each channel controller is assigned with a channel controller network address, and a storage device is assigned with a storage device address (different from the network addresses of the channel controllers). Upon receiving a packet addressed to the storage device address from an external network device, a pseudo storage load routing function responds by notifying the external network device that the packet has been transmitted to the storage device with the storage device address, while performing input/output processing indicated by the packet for the storage device with the storage device address.
    Type: Grant
    Filed: July 19, 2004
    Date of Patent: February 7, 2006
    Assignee: Hitachi, Ltd.
    Inventor: Makio Mizuno
  • Patent number: 6993637
    Abstract: A memory system for multiple processors includes a unified memory including a plurality of memory banks, and a memory controller coupled to the unified memory. The memory controller receives requests from the multiple processors, each of the requests including information of a memory address. The memory controller selects one of the memory banks by asserting a request signal only for a memory bank including the requested memory address, and provides the requesting processor with a requested memory operation on the selected memory bank.
    Type: Grant
    Filed: November 7, 2002
    Date of Patent: January 31, 2006
    Assignee: LSI Logic Corporation
    Inventor: Mark J. Kwong
  • Patent number: 6986081
    Abstract: In a block interleaving apparatus, a block deinterleaving apparatus, a block interleaving method, and a block deinterleaving method for performing block interleaving and block deinterleaving by using a single plane of a storage unit having a storage area of one block, in order to realized further reductions in circuit scale and power consumption, a comparison reference value of a comparator 123 included in an address generation unit 103 for generating addresses of a storage unit 104 is set at a minimum value which appears in the output of a multiplier 111 and is larger than L×M?1, thereby reducing the scale of the comparator.
    Type: Grant
    Filed: March 14, 2000
    Date of Patent: January 10, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Senichi Furutani
  • Patent number: 6985992
    Abstract: Methods and apparatus for performing wear leveling in a non-volatile memory system are disclosed. According to one aspect of the present invention, a method for allocating non-volatile memory that is divided into elements includes grouping the elements into a first group, a second group, and a third group. The first group includes erased elements with relatively low wear and the second group includes erased elements with relatively high wear. The method also includes determining when a first element included in the third group is to be replaced by a second element included in the first group. Contents of the first element are copied into the second element obtained from the first group. The contents are then erased from the first element, and the second element is associated with the third group. Associating the second element with the third group includes substantially disassociating the second element from the first group.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: January 10, 2006
    Assignee: SanDisk Corporation
    Inventors: Robert C. Chang, Bahman Qawami, Farshid Sabet-Sharghi
  • Patent number: 6983345
    Abstract: A computer-implemented method of realizing an associative memory capable of storing a set of documents and retrieving one or more stored documents similar to an inputted query document, said method comprising: coding each document or a part of it through a corresponding feature vector consisting of a series of bits which respectively code for the presence or absence of certain features in said document; arranging the feature vectors in a matrix; generating a query feature vector based on the query document and according to the rules used for generating the feature vectors corresponding to the stored documents such that the query vector corresponds in its length to the width of the matrix; storing the matrix column-wise; for those columns of the matrix where the query vector indicates the presence of a feature, bitwise performing one or more of preferably hardware supported logical operations between the columns of the matrix to obtain one or more additional result columns coding for a similarity measure betwe
    Type: Grant
    Filed: August 20, 2001
    Date of Patent: January 3, 2006
    Assignee: SER Solutions, Inc.
    Inventors: Gannady Lapir, Harry Urbschat
  • Patent number: 6981122
    Abstract: A memory system and a method for operating a memory system are provided. The memory system includes a set of memory banks, logic for calculating a first address in each memory bank from the set of memory banks and a controller receiving a transfer address from a computing device. The controller includes logic for selecting a memory bank from the set of memory banks based on the transfer address and the first addresses of the memory banks, and for mapping the transfer address to a target address in the selected memory bank based on a first address in the selected memory bank. As a result, the set of memory banks has a contiguous memory space.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: December 27, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Thomas A. Volpe, Michael S. Allen, Aaron Bauch
  • Patent number: 6981068
    Abstract: A peripheral card having a Personal Computer (“PC”) card form factor and removably coupled externally to a host system is further partitioned into a mother card portion and a daughter card portion. The daughter card is removably coupled to the mother card. In the preferred embodiment, a low cost flash “floppy” is accomplished with the daughter card containing only flash EEPROM chips and being controlled by a memory controller residing on the mother card. Other aspects of the invention includes a comprehensive controller on the mother card able to control a predefined set of peripherals on daughter cards connectable to the mother card; relocation of some host resident hardware to the mother card to allow for a minimal host system; a mother card that can accommodate multiple daughter cards; daughter cards that also operates directly with hosts having embedded controllers; daughter cards carrying encoded data and information for decoding it; and daughter cards with security features.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: December 27, 2005
    Assignee: SanDisk Corporation
    Inventors: Eliyahou Harari, Daniel C. Guterman, Robert F. Wallace
  • Patent number: 6976145
    Abstract: A method and apparatus are disclosed in a data processing system for automatically replicating a first data storage subsystem's configuration data on a second data storage subsystem. Storage subsystems are peripherals of the data processing system and not standalone computer systems. Storage subsystem are inaccessible directly by users. A first data storage subsystem is specified as a parent subsystem. The first data storage subsystem is configured using a first configuration data. A second data storage subsystem is specified that is to be configured the same as the first data storage subsystem. The first or second data storage subsystem automatically initiates a transfer of a copy of the first configuration data from the first data storage subsystem to the second data storage subsystem. The second data storage subsystem configures itself using the copy of the first configuration data such that the second data storage subsystem is configured the same as the first data storage subsystem.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: December 13, 2005
    Assignee: Storage Technology Corporation
    Inventor: Barry Lynn Bradford
  • Patent number: 6970968
    Abstract: A memory module controller for providing interface between a system memory controller and a plurality of memory devices on a memory module. The memory module includes first interface circuitry and control logic. The first interface circuitry is configured to receive from the system memory controller a first memory transaction in a first format. The control logic is coupled to the first interface circuitry and configured to convert the first memory transaction into a second memory transaction in a second format for the plurality of memory devices. The second format of the second memory transaction is different than the first format of the first memory transaction.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: November 29, 2005
    Assignee: Intel Corporation
    Inventor: Thomas J. Holman
  • Patent number: 6968419
    Abstract: A memory module that has a plurality of memory devices and a memory module controller configured to receive a memory transaction from a first memory bus and to control access to the plurality of memory devices.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: November 22, 2005
    Assignee: Intel Corporation
    Inventor: Thomas J. Holman
  • Patent number: 6968402
    Abstract: Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache line. A buffer may store chunks of the first cache line in a first chunk order and may store chunks of the second cache line in a second chunk order. A control unit may present a requester via the second interface with one or more chunks of the first cache line from the buffer.
    Type: Grant
    Filed: May 22, 2003
    Date of Patent: November 22, 2005
    Assignee: Intel Corporation
    Inventors: David R. Jackson, Stephen W. Kiss, Miles F. Schwartz
  • Patent number: 6968440
    Abstract: In one embodiment, there is disclosed a system and method for mapping memory addresses to system memory by establishing the size and location of each memory rank within the system memory, establishing a total size of said system memory, and fitting each said memory rank into the system memory block by using a highest power of 2 fitting rule for each iteration such that each highest power of 2 for each iteration controls the allocation of memory ranks for each such iteration.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: November 22, 2005
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Christopher M. Brueggen
  • Patent number: 6965969
    Abstract: An apparatus or system may comprises cache control circuitry coupled to a processor, and a plurality of independently accessible memory banks (228) coupled to the cache control circuitry. Some of the banks may have non-uniform latencies, organized into two or more spread bank sets (246). A method may include accessing data in the banks, wherein selected banks are closer to the cache control circuitry and/or processor than others, and migrating a first datum (445) to a closer bank from a further bank upon determining that the first datum is accessed more frequently than a second datum, which may be migrated to the further bank (451).
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: November 15, 2005
    Assignee: Board of Regents, The University of Texas Systems
    Inventors: Doug Burger, Stephen W. Keckler, Changkyu Kim