Abstract: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.

Abstract: A composite memory device, a data processing method and a data processing program can efficiently and selectively use a nonvolatile solid-state memory and a recording medium. The composite medium device includes a nonvolatile solid-state memory and a recording medium and is adapted to combine the data area of the recording medium and the data area of the nonvolatile solid-state memory and manage them as totally or partly integrated data area by means of a predetermined file system. The composite memory device is connected to a host appliance by way of an interface section.

Abstract: A system and method for facilitating the adjustment of timing parameters between a memory controller operating in a first clock domain and a memory device operating in a second clock domain. A write pointer and a read pointer are monitored to provide a write-read pointer offset representing the timing between when read data is made available by the memory device and when the read data is retrieved by the memory controller. Based on the write-read pointer offset, adjustment to different timing parameters can be made.

Abstract: A memory device includes a plurality of memory modules and a memory management module. A memory module of the plurality of memory modules includes a plurality of memory cells and a memory millimeter wave (MMW) transceiver. The memory management module determines a main memory configuration for at least some of the plurality of memory modules. The memory management module also determines physical addresses for the main memory configuration and determines a MMW communication resource table that includes an allocation mapping of one or more MMW communication resources to one or more of the at least some of the plurality of memory modules.

Abstract: Systems and a method for storing data are provided. The protected memory system includes a memory array including a plurality of memory modules each separately located with respect to each other and a memory controller configured to receive data to be stored from the data acquisition unit, store the received data in corresponding memory locations in each of the plurality of memory modules wherein the stored data including error checking information, read data from a first one of the plurality of memory modules until a data error is detected at a first memory location, read data from a second memory location of a second one of the plurality of memory modules wherein the data read from the second memory location corresponds to the data read from the first memory location, and replace the data read from the first memory location with the data read from the second memory location.

Abstract: Systems and methods are disclosed herein, including those that operate to monitor a first set of operational parameters associated with a memory vault, to adjust a second set of operational parameters associated with the memory vault, and to perform alerting and reporting operations to a host device.

Abstract: A system controller communicates with devices in a serial interconnection. The system controller sends a read command, a device address identifying a target device in the serial interconnection and a memory location. The target device responds to the read command to read data in the location identified by the memory location. Read data is provided as an output signal that is transmitted from a last device in the serial interconnection to a data receiver of the controller. The data receiver establishes acquisition instants relating to clocks in consideration of a total flow-through latency in the serial interconnection. Where each device has a clock synchronizer, a propagated clock signal through the serial interconnection is used for establishing the acquisition instants. The read data is latched in response to the established acquisition instants in consideration of the flow-through latency, valid data is latched in the data receiver.

Abstract: Example embodiments for configuring a non-volatile memory device may comprise configuring M physical partitions of the non-volatile memory into two or more banks, wherein the two or more banks respectively comprise one or more of the M physical partitions, and wherein at least a first of the M physical partitions comprises a first size and wherein at least a second of the M physical partitions comprises a second size.

Abstract: A system is provided that facilitates read access in a memory device. The system comprises a plurality of row addresses buffers that store high order addresses associated with one or more software threads. The system further comprises a plurality of row data buffers. The row data buffers are each associated with at least one row address buffer and store row data within the range of the high order addresses of the row address buffers. The system increase memory device performance by limiting the latency associated with context switching. The plurality of row address buffers and row data buffers enables software threads to associate with one or more buffers and maintain efficient subsequent memory accesses despite context switching.

Abstract: A data packet access control apparatus and a data packet access control method are disclosed. RAM resources in a data packet processing chip are used to implement a Bypass FIFO. The Bypass FIFO is used as a first-level cache for small amount of data, and an external RAM of the data packet processing chip is used as a second-level cache for large amount of data. In this way, some data packets are read and written within the chip and not all data packets have to be read and written through the external RAM. A data packet reading/writing operation may be performed to the external RAM by a BANK interleave mode.

Abstract: A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank.

Abstract: Disclosed are methods and devices, among which is a method for configuring an electronic device. In one embodiment, an electronic device may include one or more memory locations having stored values representative of the capabilities of the device. According to an example configuration method, a configuring system may access the device capabilities from the one or more memory locations and configure the device based on the accessed device capabilities.

Abstract: A dual-chip package is disclosed which includes at least two memory chips each of which may contain buffer and flash memories having different address systems from each other. Each memory chip may include a register for storing first and second flag signals each indicative of selections of corresponding memory chips, a comparator circuit for comparing the first and second flag signals in the register with a reference signal to generate a flash access signal and a buffer access signal, and a controller for controlling the buffer memory and the flash memory in response to the flash access signal and the buffer access signal.

Abstract: A network storage system includes an address adjusting module that includes a segmented packet receiver module that receives M sections of a segmented packet, where M is an integer greater than one. A bank identification (ID) overwriter module overwrites a bank ID of at least one of the M sections of the packet with a control bank ID that is different than the bank ID.

Abstract: A digital media recorder includes a first storage device associated with the digital media recorder and an interface for removably attaching a second storage device to the digital media recorder. Each of the first and second storage devices are configured to store media data representing programming from a media source. The digital media recorder is configured with logic for prioritizing the storage of the media data to one of the first and second storage devices before storing the media data to the other of the first and second storage devices.

Abstract: A system and method for monitoring the storage estate of an organization using an interactive website that is configured to produce and display a novel set of key performance indicators (KPIs) related to the storage estate, including KPIs related to data collected from at least one of storage area network data and network attached storage data. In one embodiment, the novel set of KPIs includes one or more of protection efficiency, application efficiency, and snapshot overhead, where protection efficiency is calculated as a ratio of logical addressable data storage volume to total physical volume of data storage for storage area network data of the organization, application efficiency is calculated as a fraction of disk storage allocated to end user devices that is actually used by the end user devices for storage area network data, and snapshot overhead is calculated as a ratio of a volume of storage allocated for replicated copies of data to allocated storage for network attached storage data.

Abstract: A system and method for resolving request collision in a single-port static random access memory (SRAM) are disclosed. A first SRAM part and a second SRAM part of the single-port SRAM are accessed in turn. When request collision occurs, data is temporarily stored in a first or second shadow bank associated with the first or the second SRAM part which is under access. The temporarily stored data is then transferred, at a later time, to an associated one of the first/second SRAM parts while the other one of the first/second SRAM parts is being accessed.

Abstract: Systems and methods for re-mapping memory transactions are described. In an embodiment, a method includes receiving a memory request from a hardware subsystem to a memory, replacing a first identifier with a modified identifier in the memory request, and transmitting the memory request to the memory through a processor complex. The method further includes receiving a response from the memory, determining that the response corresponds to the memory request, replacing the modified identifier with the first identifier in the response, and transmitting the response to the hardware subsystem. In some embodiments, a system may be implemented as a system-on-a-chip (SoC). Devices suitable for using these systems include, for example, desktop and laptop computers, tablets, network appliances, mobile phones, personal digital assistants, e-book readers, televisions, and game consoles.

Abstract: The invention discloses a memory management system and a memory management method are disclosed. The memory management system includes a first memory, at least one secondary memory, and a memory management device. The first memory includes a normal access memory bank and at least one switching access memory bank. The secondary memory includes at least one secondary access memory bank corresponding to the switching access memory bank. The memory management device reads/writes the normal access memory bank or the secondary access memory bank.

Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.

Abstract: A memory system includes: a memory that has plural banks; a memory controller that includes a request queue and a bank monitor and controls access to the memory; a master group including plural masters that can request access to the memory; and a system bus which is connected between the memory controller and the master group and in which an arbiter is arranged, wherein the request queue has a scheduling function for receiving access requests issued from the master group through the system bus and appropriately rearranging the received access requests and provides the arbiter with queue information, the bank monitor monitors information concerning respective banks of the memory and provides the arbiter with the bank information, and the arbiter arbitrates requests issued in parallel from the masters of the master group on the basis of the queue information and the bank information provided thereto and transmits the information to the memory controller as access control information.

Abstract: In one embodiment of the invention, a memory integrated circuit is provided including an address decoder to selectively access memory cells within a memory array; a mode register with bit storage circuits to store an enable bit and at least one sub-channel select bit; and control logic. The control logic is coupled to a plurality of address signal lines, the address decoder, and the mode register. In response to the enable bit and the at least one sub-channel select bit, the control logic selects one or more of the address signal lines to capture independent address information to support independent sub-channel memory accesses into the memory array. The control logic couples the independent address information into the address decoder.

Abstract: A method of performing cascaded flashcopy (FC) including starting a flashcopy map when a target disk is already a source of an active FC map. A computer storage system includes a configuration that allows a flashcopy (FC) map to be started when a target disk is already the source of an active FC map.

Abstract: A method of authenticating at least one piece of content provided to an image forming apparatus in which at least one consumable is disposed includes determining whether the at least one consumable includes authentication information of the at least one piece of content, displaying the at least one piece of content on a user interface according to a license policy corresponding to the authentication information, selecting at least one piece of content from the at least one piece of content displayed on the user interface, and executing the selected at least one piece of content.

Abstract: A bank select device has a plurality of addressable locations and a plurality of storage locations correlated to each other so that each storage location is correlated to plural addressable locations and each addressable location is correlated to one storage location. Each storage location contains a respective bank select. The addressable locations and storage locations are grouped into interleave patterns such that, for each pattern, there are Q storage locations and 2A addressable locations arranged in L sequential loops each containing Q sequentially addressable locations and a remainder loop containing R sequentially addressable locations, where L·Q+R=2A. A shunt defines a non-zero offset for each interleave so that each interleave commences with a different bank select and a complete rotation of all of the interleaves addresses each of the memory banks an equal number of times. The shunt (S) may be selected as mod(2A,Q), ?Q+mod(2A,Q), ±1 or ±prime to , where ?<S<+.

Abstract: A memory system includes logical banks divided into sub-banks or collections of sub-banks. The memory system responds to memory-access requests (e.g., read and write) directed to a given logical bank by sequentially accessing sub-banks or collections of sub-banks. Sequential access reduces the impact of power-supply spikes induced by memory operations, and thus facilitates improved system performance. Some embodiments of the memory system combine sequential sub-bank access with other performance-enhancing features, such as wider power buses or increased bypass capacitance, to further enhance performance.

Abstract: The exemplary embodiments provide a multi-context configurable memory controller comprising: an input-output data port array comprising a plurality of input queues and a plurality of output queues; at least one configuration and control register to store, for each context of a plurality of contexts, a plurality of configuration bits; a configurable circuit element configurable for a plurality of data operations, each data operation corresponding to a context of a plurality of contexts, the plurality of data operations comprising memory address generation, memory write operations, and memory read operations, the configurable circuit element comprising a plurality of configurable address generators; and an element controller, the element controller comprising a port arbitration circuit to arbitrate among a plurality of contexts having a ready-to-run status, and the element controller to allow concurrent execution of multiple data operations for multiple contexts having the ready-to-run status.

Abstract: A semiconductor memory apparatus includes, inter alia, a master chip and a plurality of slave chips. Each of the slave chips includes a plurality of banks. A first reception signal, a first timing signal, a bank address signal, and a slice selection signal to the slave chips may be provided by a master chip. The slave chips include a slice determining unit configured to compare the slice selection signal and a slice code and generate a slice enable signal, and a bank selecting unit configured to receive the bank address signal in response to the first reception signal and the slice enable signal and generate a bank enable signal in response to the bank address signal and the first timing signal.

Abstract: A memory module, a memory system including a memory controller and a memory module and methods thereof. The example memory module may include a plurality of memory units each having an interface and at least one memory device. An example write operation method may include receiving a packet command at a given one of a plurality of memory units, each of the plurality of memory units including an interface and at least one memory device, extracting a command signal, an address and write data from the received packet command if the received packet command corresponds to a write operation, transferring the extracted write data to at least one memory device via write/read data lines internal to the given one memory unit and writing the transferred write data at the at least one memory device.

Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

Abstract: Systems and methods for controlling memory access operations are disclosed. The system may include one or more requestors performing requests to memory devices. Within a memory controller, a request queue receives requests from a requestor, a bank decoder determines a destination bank, and the request is placed in an appropriate bank queue. An ordering unit determines if the current request can be reordered relative to the received order and generates a new memory cycle order based on the reordering determination. The reordering may be based on whether there are multiple requests to the same memory page, multiple reads, or multiple writes. A memory interface executes each memory request in the memory cycle order. A data buffer holds write data until it is written to the memory and read data until it is returned to the requestor. The data buffer also may hold memory words used in read-modify-write operations.

Abstract: Disclosed is a method of storage tiering with minimal use of DRAM memory for header overhead that utilizes the beginning of the volume to store frequently accessed or hot data. A solid state storage device is placed at the beginning of a tiered volume and is used to store frequently accessed data. When data becomes less frequently accessed it is moved to a cold data storage area on a hard disk drive in the tiered volume. The data exchange is performed on a one-to-one basis reducing the amount and use of DRAM.

Abstract: A memory system is provided includes a host processor, and a plurality of cascade connected memory cards connected to the host processor. Each of the memory cards stores a same default relative card address (RCA) prior to initialization of the memory system. The host processor is configured to sequentially access each memory card using the default RCA, and to change the default RCA to a unique RCA upon each sequential access.

Abstract: In an embodiment, a system comprises a first memory module interface unit (MMIU) configured to couple to a first one or more memory modules, and a second MMIU configured to couple to a second one or more memory modules. The first MMIU is configured to operate the first one or more memory modules at a first frequency and the second MMIU is configured to concurrently operate the second one or more memory modules at a second operating frequency different from the first operating frequency.

Abstract: A non-volatile memory system and a method for reading data therefrom are provided. The data comprises a first sub-data and a second sub-data. The non-volatile memory system comprises a first storage unit and a second storage unit, adapted for storing the two sub-data respectively. The first storage unit reads a first command from the controller, and stores the first sub-data temporarily as the first temporary sub-data according to the first command. The second storage unit reads a second command from the controller, and stores the second sub-data temporarily as the second temporary sub-data according to the second command. The first temporary sub-data is read from the first storage unit. Then, the first storage unit reads a third command from the controller. The second temporary sub-data is also read from the second storage unit while reading the third command. The time for reading data from the non-volatile memory system is reduced.

Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.

Abstract: A memory device is configured to operate in first and second data input/output modes. The memory device includes a first electrode pad, a second electrode pad, a clock signal line, a first switching unit, and a second switching unit. The clock signal line is configured to transmit a clock to an integrated circuit inside the memory device. The first switching unit switches to electrically connect the first electrode pad and the clock signal line in response to a control signal occurring for the first data input/output mode. The second switching unit switches to electrically connect the second electrode pad and the clock signal line in response to an inverse signal of the control signal occurring for the second data input/output mode.

Abstract: A digital signal processor (DSP) co-processor according to a clustered architecture with local memories. Each cluster in the architecture includes multiple sub-clusters, each sub-cluster capable of executing one or two instructions that may be specifically directed to a particular DSP operation. The sub-clusters in each cluster communicate with global memory resources by way of a crossbar switch in the cluster. One or more of the sub-clusters has a dedicated local memory that can be accessed in a random access manner, in a vector access manner, or in a streaming or stack manner. The local memory is arranged as a plurality of banks. In response to certain vector access instructions, the input data may be permuted among the banks prior to a write, or permuted after being read from the banks, according to a permutation pattern stored in a register.

Abstract: The present invention provides a method of increasing DDR memory bandwidth in DDR SDRAM modules. DDR memory has an inherent feature called the Variable Early Read command, where the read command is issued one CAS latency before the termination of an ongoing data burst By using the Variable Early Read command the effect of the CAS latency is minimized in terms of the effect on bandwidth. The enhanced bandwidth technology achieved with this invention optimizes the remaining two access latencies (tRP and tRCD) for optimal bandwidth. These optimizations in the SPD allow for much better bandwidth in real world applications.

Abstract: For address generation, a block size and a skip value are obtained, and at least one address, at least one increment value, and a step value are initialized. For a count index not in excess of a block size, iteratively performed are: selection of an output address for output from at least one phase responsive to at least the at least one address; first update of the at least one address as being equal to summation of the at least one increment and the at least one address modulo the block size; and second update of the at least one increment as being equal to summation of the at least one increment and the step value modulo the block size. The selection and the first and second updates are iteratively repeated responsive to increments of the count index to output a sequence of addresses.

Abstract: A flash memory based storage device may utilize magnetoresistive random access memory (MRAM) as at least one of a device memory, a buffer, or high write volume storage. In some embodiments, a processor of the storage device may compare a logical block address of a data file to a plurality of logical block addresses stored in a write frequency file buffer table and causes the data file to be written to the high write volume MRAM when the logical block address of the data file matches at least one of the plurality of logical block addresses stored in the write frequency file buffer table. In other embodiments, upon cessation of power to the storage device, the MRAM buffer stores the data until power is restored, after which the processor causes the buffered data to be written to the flash memory under control of the flash memory controller.

Abstract: A system includes a memory controller adapted to output address signals, command signals and select signals; a plurality of memory modules; and a plurality of buses each corresponding to one of the memory modules. Each bus is adapted to transmit corresponding ones of the address signals, the command signals, and the select signals to the corresponding memory module. Each of the memory modules includes: a plurality of memory devices; and a register adapted to receive and buffer the corresponding command and address signals transmitted to the memory module, and adapted to transmit the buffered command signal to the memory devices which are to be accessed, in response to the corresponding select signal for accessing the memory devices.

Abstract: A memory architecture is presented. The memory architecture comprises a first memory and a second memory. The first memory has at least a bank with a first width addressable by a single address. The second memory has a plurality of banks of a second width, said banks being addressable by components of an address vector. The second width is at most half of the first width. The first memory and the second memory are coupled selectively and said first memory and second memory are addressable by an address space. The invention further provides a method for transposing a matrix using the memory architecture comprising following steps. In the first step the matrix elements are moved from the first memory to the second memory. In the second step a set of elements arranged along a warped diagonal of the matrix is loaded into a register. In the fourth step the set of elements stored in the register are rotated until the element originating from the first row of the matrix is in a first location of the register.

Abstract: A data storage system includes a first circuit board, a plurality of sockets coupled to the first circuit board, an connector coupled to each of the sockets for coupling each of the sockets to external circuitry, and a plurality of memory modules, each memory module disposed within one of the sockets. The memory module includes a circuit board, an integrated circuit device having configurable blocks, DRAM devices that form parallel channels of DRAM memory and flash memory devices that form parallel channels of flash memory. The memory module also includes an interface electrically coupled to the integrated circuit device for coupling input and output between the integrated circuit device and external circuitry.

Abstract: A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and second physical addresses of the memory correspond to memory locations that store data and a corresponding ECC, respectively. The method further comprises translating the logical address into the first and second physical addresses, accessing the data over a data path, separately accessing the ECC over the same data path, and checking the integrity of the data using the ECC.

Abstract: This invention provides a storage system coupled to a computer that executes data processing jobs by running a program, comprising: an interface; a storage controller; and disk drives. The storage controller is configured to: control spinning of disk in the disk drives; receive job information which contains an execution order of the job and a load attribute of the job from the computer before the job is executed; select a logical volume to which none of the storage areas are allocated when requested by the computer to provide a logical volume for storing a file that is used temporarily by the job to be executed; select which storage area to allocate to the selected logical volume based on at least one of the job execution order and the job load attribute; allocate the selected storage area to the selected logical volume; and notify the computer of the selected logical volume.

Abstract: A semiconductor memory device comprises a memory unit having a first and a second port and including plural banks; a bank address conversion circuit operative to convert a first bank address fed from external into a second bank address different from the first bank address and operative to supply the first bank address to one of the first and second ports and supply the second bank address to the other of the first and second ports; and a write data conversion circuit operative to convert input data fed from external into write data different from the input data and operative to supply the input data to one of the first and second ports and supply the converted write data to the other of the first and second ports.

Abstract: Memory apparatus and methods utilizing multiple bit lanes may redirect one or more signals on the bit lanes. A memory agent may include a redrive circuit having a plurality of bit lanes, a memory device or interface, and a fail-over circuit coupled between the plurality of bit lanes and the memory device or interface.

Abstract: A method and system for the selective broadcasting of commands to a subset of a plurality of devices connected in series to a memory controller, where each of the plurality of devices has a unique identification number (ID). The memory controller designates the subset of devices to execute the command, excluding the non-selected devices from executing the command. The memory controller encodes the ID numbers of the designated devices into a single coded address, and sends the command along with the coded address in a packet to the series connected devices. Each device receives the packet in a serial bitstream and decodes the coded address using its ID number in order to determine whether it is selected or not. If the device is selected, the command is executed. Otherwise, the packet is forwarded without executing the command.

Abstract: Disclosed is a memory device including self-ID information. The memory device has a storage unit for storing information related to the memory device, such as a manufacturing factory, a manufacturing date, a wafer number, coordinates on a wafer and the like. Each bank of the memory device stores self-ID information related to the memory device and outputs the self-ID information out of a chip when an address is applied thereto during a test mode.