For Multiple Memory Modules (e.g., Banks, Interleaved Memory) Patents (Class 711/5)
  • Management method and a management system for volume
    Patent number: 8006063
    Abstract: It is made possible to update information registered in a database of iSNS, SLP and the like in response to a configurational change in a storage device, and for a host computer to discover a disk volume. In response to changes in contents of operation to alter a storage configuration such as in creating or deleting a volume or LUN, contents of the alteration are reflected in the database of iSNS or SLP. Also, in response to a change in setting of LUN masking, a discovery domain of iSNS or attribute values of SLP are updated so that the host computer can discover the disk volume. Also, objects and services are reregistered periodically according to a registration period of iSNS or lifetime of SLP to prevent registered contents from expiring.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: August 23, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Yasuyuki Mimatsu, Masayuki Yamamoto
  • Memory devices with buffered command address bus
    Patent number: 8006057
    Abstract: Circuits and methods are provided that alleviate overloading of the command address bus and limit decreases in command address bus bandwidth to allow increased numbers of memory modules to be included in a computer system. A plurality of switches is coupled between the command address bus (which is coupled to the memory controller) and a respective plurality of memory modules. Each switch provides command address bus data only to its respective memory module. Preferably, only one switch does so at a time, limiting the loading seen by the memory controller.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: August 23, 2011
    Assignee: Round Rock Research, LLC
    Inventor: Paul A. LaBerge
  • MEMORY CONTROLLER, METHOD OF CONTROLLING MEMORY ACCESS, AND COMPUTING APPARATUS INCORPORATING MEMORY CONTROLLER
    Publication number: 20110202704
    Abstract: A computing apparatus for accessing a multiple bank memory is provided. The computing apparatus includes a processor, a memory and a memory controller which is configured to store data in a data buffer by accessing the memory in an aligned word unit and output, in response to a request for an unaligned memory access by the processor, requested data by extracting the request data from the data buffer.
    Type: Application
    Filed: January 13, 2011
    Publication date: August 18, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woong Seo, Soo-Jung Ryu, Yoon-Jin Kim, Young-Chul Cho, II-Hyun Park, Tae-Wook Oh
  • Semiconductor storage device
    Patent number: 8001319
    Abstract: A semiconductor storage apparatus is coupled with a system bus to receive a write request accompanied with first and second blocks of data, which are stored in nonvolatile semiconductor memories. A control device sends a first erase command to one of the nonvolatile memories to initiate a first internal erase operation of data within the nonvolatile memories. After the first erase command has been sent, the control device sends a second erase command to another one of the nonvolatile memories, to initiate a second internal erase operation of data within the other nonvolatile memory.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: August 16, 2011
    Assignee: Solid State Storage Solutions, Inc.
    Inventors: Kenichi Kaki, Kunihiro Katayama, Takashi Tsunehiro
  • Structure for hub for supporting high capacity memory subsystem
    Patent number: 7996641
    Abstract: A design structure is provided for a hub for use in a high-capacity memory subsystem in which memory modules arranged in one or more clusters, each attached to a respective hub which in turn is attached to a memory controller. Within a cluster, data is interleaved so that each data access command accesses all modules of the cluster. The hub communicates with the memory modules at a lower bus frequency, but the distributing of data among multiple modules enables the cluster to maintain the composite data rate of the memory-controller-to-hub bus. Preferably, the memory system employs buffered memory chips having dual-mode operation, one of which supports a cluster configuration in which data is interleaved and the communications buses operate at reduced bus width and/or reduced bus frequency to match the level of interleaving.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gerald K. Bartley, John M. Borkenhagen, Philip Raymond Germann
  • Enhanced microprocessor or microcontroller
    Patent number: 7996647
    Abstract: A processor device has a data memory with a linear address space, the data memory being accessible through a plurality of memory banks. At least a subset of the memory banks are organized such that each memory bank of the subset has at least a first and second memory area, wherein no consecutive memory block is formed by the second memory areas of a plurality of consecutive memory banks. An address adjustment unit is provided which, when a predefined address range is used, translates an address within the predefined address range to access said second memory areas such that through the address a plurality of second memory areas form a continuous linear memory block.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: August 9, 2011
    Assignee: Microchip Technology Incorporated
    Inventors: Jerrold S. Zdenek, Joseph Julicher, Sean Steedman, Vivien Delport
  • Efficient encoding for detecting load dependency on store with misalignment
    Patent number: 7996646
    Abstract: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: August 9, 2011
    Assignee: Apple Inc.
    Inventors: Tse-yu Yeh, Daniel C. Murray, Po-Yung Chang, Anup S. Mehta
  • Electronic device using memory to expand storage capacity
    Patent number: 7996613
    Abstract: The present invention discloses an electronic device using a memory to expand storage capacity, and the device includes a main board and a data storage module. The main board includes at least one interface card slot, and the data storage module includes at least one storage interface card, and a plurality of memory slots disposed on the storage interface card for movably inserting a memory. The memory is for storing data, and the storage interface card is inserted into the interface card slot. With the memory slot on the storage interface card, the memory can be expanded conveniently, and the storage capacity can be increased dynamically as needed. The invention also enhances the security, performance, and vibration resisting function of the data storage.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: August 9, 2011
    Assignee: Portwell Inc.
    Inventor: Jen-Chun Wang
  • Mapping address bits to improve spread of banks
    Patent number: 7996597
    Abstract: A device may include a group of requestors issuing requests, a memory that includes a set of memory banks, and a control block. The control block may receive a request from one of the requestors, where the request includes a first address. The control block may perform a logic operation on a high order bit and a low order bit of the first address to form a second address, identify one of the memory banks based on the second address, and send the request to the identified memory bank.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: August 9, 2011
    Assignee: Juniper Networks, Inc.
    Inventors: Anjan Venkatramani, Srinivas Perla, John Keen
  • Device for misaligned atomics for a highly-threaded x86 processor
    Patent number: 7996632
    Abstract: A multithreaded processor with a banked cache is provided. The instruction set includes at least one atomic operation which is executed in the L2 cache if the atomic memory address source data is aligned. The core executing the instruction determines whether the atomic memory address source data is aligned. If it is aligned, the atomic memory address is sent to the bank that contains the atomic memory address source data, and the operation is executed in the bank. In one embodiment, if the instruction is mis-aligned, the operation is executed in the core.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 9, 2011
    Assignee: Oracle America, Inc.
    Inventors: Greg F. Grohoski, Mark A. Luttrell, Manish Shah
  • Parallel memory device rank selection
    Patent number: 7996602
    Abstract: A translator of an apparatus in an example selects one or more ranks of parallel memory devices from a plurality of available ranks of parallel memory devices in a plurality of double data rate registered and/or unbuffered dual in-line memory modules (DDR registered and/or unbuffered DIMMs) through employment of a native fully buffered dual in-line memory module protocol (native FB-DIMM protocol).
    Type: Grant
    Filed: April 30, 2007
    Date of Patent: August 9, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Lidia Warnes, Teddy Lee, Ricardo Ernesto Espinoza-Ibarra, Dennis Carr, Michael Bozich Calhoun
  • MEMORY MODULE AND MEMORY MODULE SYSTEM
    Publication number: 20110179213
    Abstract: A memory module and a memory module system are provided. The memory module system includes a plurality of memory modules each module comprising a plurality of memory blocks and a plurality of corresponding routers each storing a channel identification (ID) and a module ID corresponding to one or more memory blocks; and a controller configured to access the memory modules. During initialization, the controller reads and stores the channel ID and the module ID from each of the routers. The controller outputs a channel ID and a module ID that correspond to one or more memory blocks to be accessed.
    Type: Application
    Filed: March 29, 2011
    Publication date: July 21, 2011
    Inventor: Jeon Taek IM
  • Data transmission method, serial bus system, and switch-on unit for a passive station
    Patent number: 7984217
    Abstract: In a serial bus system data in the form of telegrams, representing process images of control tasks of the active station, are transmitted to the connected passive stations, and the process data are allocated to the process images in the passive station.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: July 19, 2011
    Assignee: Beckhoff Automation GmbH
    Inventors: Hans Beckhoff, Holger Buttner
  • Systems for providing performance monitoring in a memory system
    Patent number: 7984222
    Abstract: Systems for providing performance monitoring in a memory system. The memory system includes a memory controller, a plurality of memory devices, a memory bus and a memory hub device. The memory controller receives and responds to memory access requests. The memory bus is in communication with the memory controller. The memory hub device is in communication with the memory bus. The memory hub device includes a memory interface for transferring one or more of address, control and data information between the memory hub device and the memory controller via the memory bus. The memory hub device also includes a memory device interface for communicating with the memory devices. The memory hub device further includes a performance monitor for monitoring and reporting one or more of memory bus utilization, memory device utilization, and performance characteristics over defined intervals during system operation.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: July 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Kevin C. Gower, Carl E. Love, Dustin J. VanStee
  • MEMORY MANAGEMENT USING PACKET SEGMENTING AND FORWARDING
    Publication number: 20110173369
    Abstract: Systems, devices and methods according to these exemplary embodiments provide for memory management techniques and systems for storing data. Data is segmented for storage in memory. According to one exemplary embodiment, each fragment is routed via a different memory bank and forwarded until they reach a destination memory bank wherein the fragments are reassembled for storage. According to another exemplary embodiment, data is segmented and stored serially in memory banks.
    Type: Application
    Filed: June 16, 2010
    Publication date: July 14, 2011
    Applicant: TELEFONAKTIEBOLAGET L M ERICSSON (PUBL)
    Inventors: Martin JULIEN, Robert BRUNNER
  • Flash memory controller having reduced pinout
    Patent number: 7978516
    Abstract: Disclosed is a flash memory controller connected to a flash memory module. The pin-out of the flash memory controller combines ready-busy and chip-select signals. In one embodiment, the flash memory module is made up of a set of banks, each consisting of a plurality of devices, with each bank sharing a single chip-select/ready-busy connection to the controller.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: July 12, 2011
    Assignee: Pliant Technology, Inc.
    Inventors: Aaron K. Olbrich, Douglas A. Prins
  • Storage system including a fast storage device for storing redundant data
    Patent number: 7979632
    Abstract: A computer storage system includes a controller, a first storage device and a second storage device including at least one fast storage device. The controller is configured to perform data operations. The first storage device stores data, and the second storage device stores data redundant to the data stored in the first storage device.
    Type: Grant
    Filed: September 6, 2002
    Date of Patent: July 12, 2011
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Guillermo Alvarez, Mustafa Uysal, Arif Merchant, John Wilkes
  • Memory access method
    Patent number: 7979622
    Abstract: A memory access method intended for a memory required to provide an interval of a predetermined number of clock cycles or longer between successive occurrences of access when the same bank is successively accessed, and that eliminates an idle time between successive occurrences of access to allow for improved performance. Pieces of data are written into 0th, the first, the second, and the third banks, respectively. No idle time is caused between successive occurrences of access because different banks are successively accessed. Since a burst length of each of the pieces of data is eight, an interval of 16 cycles which is longer than 15 cycles is provided between a start of writing of first data and a start of second writing of data. Accordingly, no idle time is caused also between completion of writing of the first data and start of writing of the second data.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: July 12, 2011
    Assignee: MegaChips Corporation
    Inventor: Akira Okamoto
  • SHARING PHYSICAL MEMORY LOCATIONS IN MEMORY DEVICES
    Publication number: 20110167193
    Abstract: A memory structure includes a plurality of address banks where each address bank is operative to store a memory address. In certain embodiments, at least two of the address banks share physical memory locations for at least one redundant most significant bit. Additionally, at least two of the address banks in certain embodiments share physical memory locations for at least one redundant most significant bit and at least one redundant least significant bit. At least two of the address banks in certain embodiments also share physical memory locations for at least one redundant interior bit.
    Type: Application
    Filed: December 30, 2010
    Publication date: July 7, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Sujeet Ayyapureddi
  • System and method for storing data in a virtualized high speed memory system
    Publication number: 20110167192
    Abstract: A system and method for providing high-speed memory operations is disclosed. The technique uses virtualization of memory space to map a virtual address space to a larger physical address space wherein no memory bank conflicts will occur. The larger physical address space is used to prevent memory bank conflicts from occurring by moving the virtualized memory addresses of data being written to memory to a different location in physical memory that will eliminate a memory bank conflict.
    Type: Application
    Filed: December 15, 2009
    Publication date: July 7, 2011
    Inventors: Sundar Iyer, Shang-Tse Chuang
  • Method and apparatus for accessing memory in a computer system architecture supporting heterogeneous configurations of memory structures
    Patent number: 7970980
    Abstract: A computer system includes at least one processor, multiple memory modules embodying a main memory, a communications medium for communicating data between the at least one processor and main memory, and memory access control logic which controls the routing of data and access to memory. The communications medium and memory access control logic are designed to accommodate a heterogenous collection of main memory configurations, in which at least one physical parameter is variable for different configurations. The bits of the memory address are mapped to actual memory locations by assigning fixed bit positions to the most critical physical parameters across multiple different module types, and assigning remaining non-contiguous bit positions to less critical physical parameters. In the preferred embodiment, the computer system employs a distributed memory architecture.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: June 28, 2011
    Assignee: International Business Machines Corporation
    Inventors: Philip Rogers Hillier, III, Joseph Allen Kirscht, Jamie Randall Kuesel
  • Adaptive deterministic grouping of blocks into multi-block units
    Patent number: 7970985
    Abstract: The present invention presents techniques for the linking of physical blocks of a non-volatile memory into composite logical structures or “metablocks”. After determining an initial linking of good physical blocks into metablocks, a record of the linking is maintained in the non-volatile memory where it can be readily accessed when needed. In one set of embodiments, the initially linking is deterministically formed according to an algorithm and can be optimized according to the pattern of any bad blocks in the memory. As additional bad blocks arise, the linking is updated using by replacing the bad blocks in a linking with good blocks, preferably in the same sub-array of the memory as the block that they are replacing.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: June 28, 2011
    Assignee: SanDisk Corporation
    Inventors: Carlos J. Gonzalez, Alan Douglas Bryce, Sergey Anatolievich Gorobets, Alan David Bennett
  • Storage system using flash memories and wear-leveling method for the same system
    Patent number: 7970986
    Abstract: A storage system using flash memories includes a storage controller and plural flash memory modules as storage media. Each flash memory module includes at least one flash memory chip and a memory controller for leveling erase counts of blocks belonging to the flash memory chip. The storage controller combines the plural flash memory modules into a first logical group, translates a first address used for accessing the flash memory modules belonging to the first logical group to a second address used for handling the first address in the storage controller, and combines the plural first logical groups into a second logical group.
    Type: Grant
    Filed: April 22, 2010
    Date of Patent: June 28, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Katsuya Tanaka, Kentaro Shimada
  • ADAPTIVE ADDRESS MAPPING WITH DYNAMIC RUNTIME MEMORY MAPPING SELECTION
    Publication number: 20110153908
    Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Applicant: Intel Corporation
    Inventors: Andre Schaefer, Matthias Gries
  • Memory system and method having point-to-point link
    Patent number: 7966446
    Abstract: A memory system includes a controller for generating a control signal and a primary memory for receiving the control signal from the controller. A secondary memory is coupled to the primary memory, the secondary memory being adapted to receive the control signal from the primary memory. The control signal defines a background operation to be performed by one of the primary and secondary memories and a foreground operation to be performed by the other of the primary and secondary memories. The primary memory and the secondary memory are connected by a point-to-point link. At least one of the links between the primary and secondary memories can be an at least partially serialized link. At least one of the primary and secondary memories can include an on-board internal cache memory.
    Type: Grant
    Filed: June 13, 2006
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Joo-Sun Choi
  • Reconfigurable memory module and method
    Patent number: 7966444
    Abstract: A computer system includes a controller coupled to a plurality of memory modules each of which includes a memory hub and a plurality of memory devices divided into a plurality of ranks. The memory hub is operable to configure the memory module to simultaneously address any number of ranks to operate in a high bandwidth mode, a high memory depth mode, or any combination of such modes.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: June 21, 2011
    Assignee: Round Rock Research, LLC
    Inventors: Terry R. Lee, Joseph M. Jeddeloh
  • Memory systems including memory devices coupled together in a daisy-chained arrangement
    Patent number: 7966443
    Abstract: A memory system having a plurality of memory devices and a memory controller. The memory devices are coupled to one another in a chain. The memory controller is coupled to the chain and configured to output a memory access command that is received by each of the memory devices in the chain and that selects a set of two or more of the memory devices to be accessed.
    Type: Grant
    Filed: November 1, 2007
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kevin P. Grundy, Para K. Segaram
  • MAINTAINING DATA COHERENCE BY USING DATA DOMAINS
    Publication number: 20110138101
    Abstract: A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 9, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kattamuri Ekanadham, Il Park, Pratap Pattnaik
  • METHOD AND SYSTEM FOR CONCURRENT BACKGROUND AND FOREGROUND OPERATIONS IN A NON-VOLATILE MEMORY ARRAY
    Publication number: 20110138100
    Abstract: A method and system for permitting host write operations in one part of a flash memory concurrently with another operation in a second part of the flash memory is disclosed. The method includes receiving data at a front end of a memory system, selecting at least one of a plurality of subarrays in the memory system for executing a host write operation, and selecting at least one other subarray in which to execute a second operation. The write operation and second operation are then executed substantially concurrently. The memory system includes a plurality of subarrays, each associated with a separate subarray controller, and a front end controller adapted to select and initiate concurrent operations in the subarrays.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 9, 2011
    Inventor: Alan Sinclair
  • System and method for managing storage networks and providing virtualization of resources in such a network
    Patent number: 7958305
    Abstract: This invention is a system and method for managing one or more data storage networks using a new architecture. A method for handling logical to physical mapping is included in one embodiment with the new architecture. A method for handling errors is included in another embodiment with the new architecture.
    Type: Grant
    Filed: May 14, 2010
    Date of Patent: June 7, 2011
    Assignee: EMC Corporation
    Inventors: Fernando Oliveira, Bradford B. Glade, Jeffrey A. Brown, Peter J. McCann, David Harvey, James A. Wentworth, III, Walter M. Caritj, Matthew Waxman, Lee W. VanTine
  • Address reduction for data storage enclosures
    Patent number: 7958263
    Abstract: A data storage enclosure management system of a plurality of service processors is configured to communicate externally via a pair of FC-AL loops. Lead and subsidiary service processors are defined and lead service processors connect to ones of the FC-AL loops with an FC-AL address, and the lead and subsidiary service processors are connected by a secondary communication link. The lead service processor(s) employ an identifier unassociated with the FC-AL address to differentiate communications of the lead service processor from communications of an associated subsidiary service processor, the lead service processor serving as a proxy for the associated subsidiary service processor with respect to the FC-AL address and communicating with the associated subsidiary service processor via the secondary communication link.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: June 7, 2011
    Assignee: International Business Machines Corporation
    Inventors: John Charles Elliott, Robert Akira Kubo, Gregg Steven Lucas
  • Directed auto-refresh synchronization
    Patent number: 7953921
    Abstract: In a directed auto-refresh (DARF) mode, refresh commands are issued by a controller, and refresh row and bank addresses are maintained internally to a memory module. A bank address counter internal to the memory is initialized to a first predetermined value upon entering DARF mode. The memory refreshes the currently addressed bank in response to a DARF command, and increments the bank address counter in a predetermined sequence. The controller tracks the bank address, and may issue one or more memory access commands while a DARF operation is being performed, if the memory access and the refresh are directed to different banks. Upon exiting a self-refresh mode, the bank address counter assumes a second predetermined value. The second predetermined value may be fixed, or may be n+1, where n is the value of the bank address counter when self-refresh mode is initiated.
    Type: Grant
    Filed: April 27, 2005
    Date of Patent: May 31, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Robert Michael Walker, Perry Willmann Remaklus, Jr.
  • SEMICONDUCTOR DEVICE
    Publication number: 20110107005
    Abstract: A renewal of an internal address generated by an internal address generator that is used for a refresh operation of information in a memory unit including a plurality of memory cells is preformed during a refresh operation before an activated word line connected to the memory cell corresponding to the internal address is inactivated in the refresh operation.
    Type: Application
    Filed: October 22, 2010
    Publication date: May 5, 2011
    Inventor: Yuji NAKAOKA
  • Multiprocessor system and method thereof
    Publication number: 20110107006
    Abstract: A multiprocessor system and method thereof are provided.
    Type: Application
    Filed: January 10, 2011
    Publication date: May 5, 2011
    Inventors: Yun-Hee Shin, Han-Gu Sohn, Young-Min Lee, Ho-Cheol Lee, Soo-Young Kim, Dong-Hyuk Lee, Chang-Ho Lee
  • Memory module and memory system
    Patent number: 7934047
    Abstract: A memory module includes a plurality of ranks that each include a first pin group and a second pin group for receiving external pin signals, and a rank selecting unit included in each of the plurality of ranks, the rank selecting unit configured to output different rank pin signals to each rank by using signals of the first pin group.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: April 26, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventor: Joong-Ho Lee
  • Memory system having low power consumption
    Patent number: 7930492
    Abstract: A memory system selectively sets signaling modes based on stack position information. The memory system includes a memory module having at least one semiconductor memory device and a memory controller configured to set a signaling mode based on stack position information of each of the semiconductor memory devices. A signaling between the memory controller and each of the semiconductor memory devices is performed in a differential signaling mode, and a signaling among the semiconductor memory devices is performed in a single-ended signaling mode. Accordingly, the memory system has reduced power consumption.
    Type: Grant
    Filed: January 4, 2008
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoe-Ju Chung, Jung-Bae Lee, Joo-Sun Choi
  • Determining operation mode for semiconductor memory device
    Patent number: 7930465
    Abstract: A semiconductor memory device capable of determining an operation mode by using states of data pins, and an operation mode determining method for the same are disclosed. The semiconductor memory device includes at least one MRS input pad, at least one data input pad, and an operation mode determining circuit. The operation mode determining circuit generates an operation mode determining signal, when an MRS command input through the MRS input pad corresponds to a predetermined MRS command and data signals input through the data input pad or pads include a predetermined combination. Accordingly, the efficiency in the manufacturing and producing processes may be improved by determining the operation mode of the semiconductor memory device in a module assembly process.
    Type: Grant
    Filed: October 21, 2005
    Date of Patent: April 19, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seok-Il Kim, Young-Man Ahn, Byung-Se So, Seung-Jin Seo
  • APPARATUS TO ACCESS MULTI-BANK MEMORY
    Publication number: 20110087821
    Abstract: A method of controlling access to a multi-bank memory, and an apparatus to perform the method, is provided. For the access control, a stride register is provided to store stride values determined by a processor during a run time. A memory controller controls access to a logical block in row and column directions, in an interleaved manner, the logical block having a width determined according to the stride values stored in the stride register. Accordingly, simultaneous access to a plurality of pieces of data at successive addresses adjacent in the row and column directions may be made.
    Type: Application
    Filed: October 12, 2010
    Publication date: April 14, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Woong SEO, Soo-Jung Ryu, Yoon-Jin Kim, Young-Chul Cho, Il-Hyun Park, Tae-Wook Oh
  • Method and apparatus for fine edge control on integrated circuit outputs
    Patent number: 7925912
    Abstract: A device for adjusting the timing of at least one edge of an output pulse created in response to a reference pulse is disclosed. Such a device may include a first memory circuit having two or more first memory cells and a second memory circuit also having two or more second memory cells. The first memory circuit may be configured to periodically sample the reference pulse at the rising edges of a first sample clock while the second memory circuit may be configured to periodically sample the reference pulse at the falling edges of the first sample clock. A combinatorial logic circuit may also be included to produce the output pulse having at least one adjusted edge based on a set of timing instructions and timing information provided by the first and/or second memory circuits.
    Type: Grant
    Filed: July 31, 2007
    Date of Patent: April 12, 2011
    Assignee: Marvell International Ltd.
    Inventors: Roy G. Moss, Douglas G. Keithley, Richard N. Woolley
  • Systems and Methods for Addressing Physical Memory
    Publication number: 20110078359
    Abstract: One embodiment of the present invention sets forth a technique for computing dynamic random access memory (DRAM) addresses from linear physical addresses for memory subsystems implementing integral power of two virtual page sizes, and an arbitrary number of available partitions. Each DRAM address comprises a row address, column address, bank address, and partition address. The linear physical address is used to generate to the DRAM address in units of a DRAM bank size. Address scrambling may be implemented to overcome transient access contention to specific DRAM pages by multiple client modules.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 31, 2011
    Inventor: James M. VAN DYKE
  • DATA HANDLING SYSTEM COMPRISING MEMORY BANKS AND DATA REARRANGEMENT
    Publication number: 20110078360
    Abstract: It is an object of the invention to provide a memory architecture that can handle data interleaving efficiently. This and other objects are achieved by the system according to the invention. The data handling system, is configured for receiving at an input a plurality of commands. The system comprises: a plurality of memory banks; a distributor connected to the input and having a plurality of distributor outputs. Each specific one of the plurality of memory banks (106) is connected to a specific one of the plurality of distributor outputs. The distributor comprises a permutator for designating for each specific command a specific distributor output. The distributor distributes the specific command to the specific designated distributor output. The permutator has a control input and the designating is reconfigurable under the control of reconfiguration data received at the control input.
    Type: Application
    Filed: May 19, 2009
    Publication date: March 31, 2011
    Applicant: NXP B.V.
    Inventors: Erik Rijshouwer, Cornelis Hermanus van Berkel
  • Storage device with transaction logging capability
    Patent number: 7913030
    Abstract: In one aspect, a system for indexing transactions over a shared bus is described. In various embodiments, the system includes a host controller and a plurality of storage devices in communication with the bus. Each of the storage devices is configured to store data. The bus facilitates communications between the host controller and the plurality of storage devices. A selected one of the storage devices is configured to function as a transaction indexer to monitor the bus and index and store selected transaction information associated with operations that occur over the bus. While the host controller may be arranged to configure the transaction indexer, the transaction monitoring, indexing and storing are performed substantially automatically by the transaction indexer without requiring further instructions from the host controller.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: March 22, 2011
    Assignee: SanDisk IL Ltd.
    Inventors: Nir Perry, Polina Marimont, Alain Nochimowski
  • Multi-column addressing mode memory system including an integrated circuit memory device
    Patent number: 7907470
    Abstract: A memory system includes a master device, such as a graphics controller or processor, and an integrated circuit memory device operable in a dual column addressing mode. The integrated circuit memory device includes an interface and column decoder to access a row of storage cells or a page in a memory bank. During a first mode of operation, a first row of storage cells in a first memory bank is accessible in response to a first column address. During a second mode of operation, a first plurality of storage cells in the first row of storage cells is accessible in response to a second column address during a column cycle time interval. A second plurality of storage cells in the first row of storage cells is accessible in response to a third column address during the column cycle time interval. The first and second pluralities of storage cells are concurrently accessible from the interface.
    Type: Grant
    Filed: February 24, 2009
    Date of Patent: March 15, 2011
    Assignee: RAMBUS Inc.
    Inventors: Frederick A. Ware, Lawrence Lai, Chad A. Bellows, Wayne S. Richardson
  • Memory module and on-line build-in self-test method thereof for enhancing memory system reliability
    Patent number: 7908530
    Abstract: A memory module including a plurality of memory banks, a memory control unit, and a built-in self-test (BIST) control unit is provided. The memory banks store data. The memory control unit accesses the data in accordance with a system command. The BIST control unit generates a BIST command to the memory control unit when a BIST function is enabled in the memory module. While the system command accessing the data in a specific memory bank exists, the memory command control unit has the priority to execute the system command instead of the BIST command testing the specific memory bank. Memory reliability of a system including the memory module is enhanced without reducing the system effectiveness.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: March 15, 2011
    Assignee: Faraday Technology Corp.
    Inventor: Cheng-Chien Chen
  • System and method for memory allocation management
    Patent number: 7900010
    Abstract: A memory manager for a system, a system that includes the memory manager and a method of using thereof are provided. The memory manager manages memory allocations in at least a memory. The memory manger comprises, a first unit configured for receiving a plurality of requests from one or more components of one or more applications of a system. The memory manager also includes a second unit configured for optimizing memory allocations for the plurality of requests.
    Type: Grant
    Filed: July 9, 2007
    Date of Patent: March 1, 2011
    Assignee: Ittiam Systems (P) Ltd.
    Inventors: Vikas K. Prasad, Sudheer Kumar Vootla
  • Embedded system and page relocation method therefor
    Patent number: 7900018
    Abstract: Provided are an embedded system and a method for relocating memory pages therefor. The embedded system includes a processor, a data relocating circuit for receiving a logical address from the processor, mapping the received logical address to a physical address to locate a valid page in a predetermined bank, and generating a bank power control signal according to whether or not a corresponding memory bank includes valid pages, and a memory including a plurality of memory banks addressed by a physical address outputted from the data relocating circuit and a plurality of switching means for selectively supplying a power voltage to each of memory banks in response to the bank power control signal.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: March 1, 2011
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Young-Su Kwon, Bon-Tae Koo, Nak-Woong Eum
  • Memory module system and method for operating a memory module
    Patent number: 7899984
    Abstract: A memory module system, a memory module, a buffer device, a memory module printed circuit board, and to a method for operating a memory module is disclosed. In one embodiment, the memory module system includes at least a first, a second, and a third memory module. The first memory module is connected with the second memory module via a first connection and with the third memory module via a second connection, and is designed and equipped such that data, address, and/or control signals received by the first memory module are transmitted to the second memory module via the first connection and to the third memory module via the second connection.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: March 1, 2011
    Assignee: Qimonda AG
    Inventor: Gerhard Risse
  • Semiconductor device, memory system and control method of the semiconductor device
    Patent number: 7895484
    Abstract: A semiconductor device including a logic circuit and a test circuit is provided which comprises: a logic signal terminal that supplies a signal to the logic circuit; a latch circuit that latches a signal based on a synchronization signal from the test circuit; a first selection circuit that supplies an external signal from the logic signal terminal to one of the logic circuit and the latch circuit selectively based on a test mode signal; and a second selection circuit that supplies one of the external signal and a signal from the test circuit selectively to a memory.
    Type: Grant
    Filed: August 5, 2008
    Date of Patent: February 22, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Tanaka, Yuji Nakagawa
  • DATA PACKET ACCESS CONTROL APPARATUS AND METHOD THEREOF
    Publication number: 20110040923
    Abstract: A data packet access control apparatus and a data packet access control method are disclosed. RAM resources in a data packet processing chip are used to implement a Bypass FIFO. The Bypass FIFO is used as a first-level cache for small amount of data, and an external RAM of the data packet processing chip is used as a second-level cache for large amount of data. In this way, some data packets are read and written within the chip and not all data packets have to be read and written through the external RAM. A data packet reading/writing operation may be performed to the external RAM by a BANK interleave mode.
    Type: Application
    Filed: August 5, 2010
    Publication date: February 17, 2011
    Applicant: Hangzhou H3C Technologies Co., Ltd.
    Inventor: Kai REN
  • Motherboard and interface control method of memory slot thereof
    Patent number: 7890687
    Abstract: The invention provides a motherboard and an interface control method of a memory slot thereof. The motherboard includes a plurality of slot groups, a bus, and an interface controller. Each of the slot groups includes a first memory slot and a second memory slot connected with the bus. The first memory slot and the second memory slot form two different access addresses. The interface controller transmits a plurality of pin control signals to the corresponding slot groups to make the two access addresses of the first memory slot and the second memory slot of a using slot group of the slot groups different from the two access addresses of the first memory slot and the second memory slot of each of the other slot groups. Then, the interface controller accesses the using slot group via the bus.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: February 15, 2011
    Assignee: ASUSTeK Computer Inc.
    Inventors: Ming-Jen Lee, Tung-Chang Wu