Free Address Space Management (epo) Patents (Class 711/E12.006)
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Publication number: 20130054923Abstract: Memory leak detection can be automated by assigning and recording an increasing sequence number to each memory allocation requested by an action. Call stacks associated with the action are also recorded. Several repetitions of the action can be executed. Allocations that occur in each action and that have similar or matching callstacks are defined as leaks. Allocations that do not have matches can be ignored.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: MICROSOFT CORPORATIONInventors: Benjamin W. Bradley, Calvin Hsia
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Publication number: 20130054926Abstract: The subject disclosure relates to analyzing memory allocations for one or more computer-implemented processes. In particular, in conjunction with employing tags for tracking memory allocation commands, currently allocated memory can be examined for various characteristics of inefficient memory use. For example, as memory is initially allocated, a predetermined bit pattern can be written to the newly allocated memory. Thus, detection of the predetermined bit pattern can be indicative of wasted memory use. Moreover, additional features can be provided to both analyze data and present views associated with that analysis relating to identification of memory fragmentation, over-allocation, sparse memory use, duplication of allocations, multiple module loads, and so forth.Type: ApplicationFiled: August 24, 2011Publication date: February 28, 2013Applicant: MICROSOFT CORPORATIONInventor: Calvin Hsia
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Patent number: 8356134Abstract: A memory device includes a nonvolatile memory and a controller. The nonvolatile memory includes a storage area having a plurality of memory blocks each including a plurality of nonvolatile memory cells, and a buffer including a plurality of nonvolatile memory cells and configured to temporarily store data, and in which data is erased for each block. If a size of write data related to one write command is not more than a predetermined size, the controller writes the write data to the buffer.Type: GrantFiled: December 13, 2007Date of Patent: January 15, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Takafumi Ito, Hidetaka Tsuji
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Publication number: 20130007403Abstract: A computing system determines whether memory data pertaining to a block of dynamically allocated memory within an inferior process memory space satisfies one or more criteria in heuristics data. The computing system identifies a category to assign to the block of dynamically allocated memory based on the determination of whether the memory data satisfies the criteria and generates a reliability score for the block of dynamically allocated memory indicating a level of reliability of the identified category. The computing system categorizes the block of dynamically allocated memory based on a comparison of the reliability score and a previous reliability score of the block of the dynamically allocated memory.Type: ApplicationFiled: June 30, 2011Publication date: January 3, 2013Inventor: David Hugh Malcolm
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Publication number: 20120317388Abstract: An abstraction for storage class memory is provided that hides the details of the implementation of storage class memory from a program, and provides a standard channel programming interface for performing certain actions, such as controlling movement of data between main storage and storage class memory or managing storage class memory.Type: ApplicationFiled: June 10, 2011Publication date: December 13, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Peter D. Driever, Charles W. Gainey, JR., Steven G. Glassen, Thomas B. Mathias, Kenneth J. Oakes, Peter G. Sutton, Peter K. Szwed, Elpida Tzortzatos, Harry M. Yudenfriend
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Patent number: 8332611Abstract: The present invention relates to methods for managing memory. More particularly, but not exclusively, the present invention relates to methods for managing memory across a plurality of partitions. A first method is disclosed which allocates memory across a plurality of partitions and includes the steps of: establishing a pool of free memory 27; allocating some of the free memory 30 to a target partition when required; identifying memory 40 within one or more source partitions to replace the allocated free memory; cleaning 42 the identified memory; and adding the cleaned memory to the pool 50. A second method for allocating memory across a plurality of partitions is also disclosed.Type: GrantFiled: September 29, 2005Date of Patent: December 11, 2012Assignee: Hewlett-Packard Development Company, L.P.Inventor: Muppirala Kishore Kumar
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Patent number: 8321638Abstract: System, method and computer program product for allocating physical memory to processes. The method includes enabling a kernel to free memory in a physical memory space corresponding to arbitrarily sized memory allocations released by processes or applications in a virtual memory space. After freeing the memory, the system determines whether freed physical memory in the physical memory space spans one or more fixed size memory units (e.g., page frames). The method further includes designating a status of the one or more page frames as available for reuse; the freed page frames marked as available for reuse being available for backing a new process without requiring the kernel to delete data included in the freed memory released by the process.Type: GrantFiled: March 6, 2009Date of Patent: November 27, 2012Assignee: Red Hat, Inc.Inventors: Henri Han van Riel, Adriaan DM van de Ven
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Patent number: 8281103Abstract: A method and apparatus for allocating storage addresses are disclosed. The method includes: receiving a storage address allocation request; searching a level-2 bitmap in a hierarchical bitmap in bidirectional mode; outputting an idle bit according to the result of searching in the level-2 bitmap; obtaining a storage address according to the output idle bit, and allocating the storage address. The apparatus includes: a first receiving module, configured to receive a storage address allocation request; a first searching module, configured to search a level-2 bitmap in a hierarchical bitmap in bidirectional mode for an idle bit, wherein the hierarchical bitmap includes N level-1 bitmaps and the level-2 bitmap; and an allocating module, configured to: obtain a storage address according to the output idle bit in the level-2 bitmap, and allocate the obtained storage address.Type: GrantFiled: February 9, 2010Date of Patent: October 2, 2012Assignee: Huawei Technologies Co., Ltd.Inventors: Xinwei Han, Wan Lam, Naidong Ning
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Patent number: 8214577Abstract: A method of memory management includes allocating a portion of a memory as a memory heap including a plurality of segments, each segment having a segment size; performing one or more memory allocations for objects in the memory heap; creating a free list array and class-size array in a metadata section of the memory heap, the class-size array being created such that each element of the size-class array is related a particular one of the plurality of segments and the free list array being created such that each element of the free list array is related to a different size class; and initializing the heap when it is determined that the heap may be destroyed, initializing including clearing the free list array.Type: GrantFiled: January 6, 2012Date of Patent: July 3, 2012Assignee: International Business Machines CorporationInventors: Hiroshi Inoue, Hideaki Komatsu
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Patent number: 8180956Abstract: A method controlling a memory card including a nonvolatile semiconductor memory including plural write areas. The method: formats the plural write areas; creates a temporary file entry describing a reserved region size including a free part of the plural write areas and a start position of the reserved region; writes a file in the reserved region from the start position after creating the temporary file entry; when the file has been completely written, determines size of the file written and writes a final file entry describing the start position and file size; when the file has not been completely written, references the temporary file entry to recognize the start position; detects a final position in the reserved region; determines size of the unfinished file using the start position and final position; changes the temporary file entry to a final entry describing the start position and unfinished file size.Type: GrantFiled: October 12, 2011Date of Patent: May 15, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takafumi Ito, Hiroyuki Sakamoto
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Patent number: 8166243Abstract: A problem to be solved is to enable the user to read out data stored in a logical unit in a power saving state in a short time in a storage system having a power saving function such as stopping the spindle of the HDD. To solve the problem, candidate document file information is read out according to the keywords inputted by the user from a search system, a predetermined number of document file names are extracted from the highest candidates in the candidate document file information, and the power saving function of the logical units actually storing the extracted document files is controlled (switch the state from the power saving state to the normal operation state).Type: GrantFiled: February 6, 2009Date of Patent: April 24, 2012Assignee: Hitachi, Ltd.Inventor: Tsunehiro Tobita
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Patent number: 8145870Abstract: The present invention provides an improved method, system, and computer program product that can optimize cache utilization. In one embodiment, a kernel service creates a storage map, and sending said storage map to an application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating a cache map. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating an indication of one or more storage locations that have been allocated to store information for the application. In one embodiment of the present invention, the step of the kernel service creating the storage map may further comprise the kernel service creating the storage map in response to receiving a request for the storage map from the application.Type: GrantFiled: December 7, 2004Date of Patent: March 27, 2012Assignee: International Business Machines CorporationInventors: Andrew Dunshea, Diane Garza Flemming
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Patent number: 8131926Abstract: A generic storage container system is provided for a grid-based storage architecture, comprising a generic storage container comprising a plurality of storage domains along one axis against a plurality of rows of stripes along another axis defining a preselected storage capacity, and configuration information allocating the stripes in response to a storage format specified by an allocation request. A method is provided for storing the data, comprising: providing the generic storage container; providing configuration information adapted for selectively allocating the stripes in relation to a data storage format; specifying a desired storage format; and allocating the stripes in response to the desired format.Type: GrantFiled: October 20, 2004Date of Patent: March 6, 2012Assignee: Seagate Technology, LLCInventors: Clark Edward Lubbers, Randy L. Roberson, Diana Shen
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Patent number: 8127101Abstract: Provided is a file server providing a file service to a host computer, including an interface coupled to the host computer; a processor; a memory; and an interface coupled to a disk drive. The file server is configured to calculate a capacity of storage areas in the memory, which is required to provide the file service; execute a first memory check in which the storage areas having the calculated capacity are tested; execute, after the first memory check is completed, a second memory check in which remaining storage areas in the memory are tested; and start, in a period after the first memory check is completed and before the second memory check is completed, providing the file service.Type: GrantFiled: October 1, 2008Date of Patent: February 28, 2012Assignee: Hitachi, Ltd.Inventors: Takayuki Fukatani, Akiyoshi Hashimoto
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Patent number: 8117404Abstract: In one embodiment, a processor comprises a circuit coupled to receive an indication of a memory operation to be executed in the processor. The circuit is configured to predict whether or not the memory operation is misaligned. A number of accesses performed by the processor to execute the memory operation is dependent on whether or not the circuit predicts the memory operation as misaligned. In another embodiment, a misalignment predictor is coupled to receive an indication of a memory operation, and comprises a memory and a control circuit coupled to the memory. The memory is configured to store a plurality of indications of memory operations previously detected as misaligned during execution in a processor. The control circuit is configured to predict whether or not a memory operation is misaligned responsive to a comparison of the received indication and the plurality of indications stored in the memory.Type: GrantFiled: August 10, 2005Date of Patent: February 14, 2012Assignee: Apple Inc.Inventors: Tse-Yu Yeh, Po-Yung Chang, Eric Hao
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Patent number: 8108649Abstract: A method of operating a memory system includes allocating a portion of a memory unit in a computing system as a memory heap. The heap includes a metadata section and a plurality of segments, each segment having a segment size.Type: GrantFiled: June 13, 2008Date of Patent: January 31, 2012Assignee: International Business Machines CorporationInventors: Hiroshi Inoue, Hideaki Komatsu
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Patent number: 8108644Abstract: The storage control apparatus of the present invention saves a table for managing a virtual volume in a pool and keeps the state of the table in the latest state. A first dynamic mapping table (DMT) that manages a first virtual volume is saved in a first pool. Upon receipt of a write command relating to an unused virtual slot from a write command issuing device, a first virtual volume control unit assigns an unused real slot in the first pool to the virtual slot and updates the first DMT. The first virtual volume control unit discriminates the validity of the received data and, in cases where “0” data are received, releases the assigned real slot, updates the first DMT once again, and discards the received data. In cases where the received data are valid data, de-staging is performed following a DMT update.Type: GrantFiled: February 26, 2008Date of Patent: January 31, 2012Assignee: Hitachi, Ltd.Inventors: Masataka Innan, Hideo Tabuchi
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Patent number: 8099548Abstract: A portable multifunction computing device optimizes cache storage when processing media files and the like. During a playback operation, the device caches as many media items as possible such that during playback media items are retrieved from cache rather than from a hard disk memory. The device monitors memory requirements of other programs and applications currently in use on the device to insure sufficient cache memory is available for such programs and applications.Type: GrantFiled: March 23, 2006Date of Patent: January 17, 2012Assignee: Microsoft CorporationInventor: Darren R. Davis
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Patent number: 8095726Abstract: Embodiments of the invention relate to associating a source string with a target content unit stored on a content addressable storage (CAS) system. This may be accomplished, in some embodiments, by storing on the CAS system an associative content unit that includes the source string in its binding part and includes the target content unit in its non-binding part.Type: GrantFiled: March 31, 2008Date of Patent: January 10, 2012Assignee: EMC CorporationInventors: Mark O'Connell, Michael Kilian
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Patent number: 8086810Abstract: Various embodiments for rapid defragmentation of storage volumes in a computing environment are provided. A plurality of source data sets is copied from the fragmented storage volume to a plurality of target data sets on an additional storage volume. The plurality of source data sets is placed on the additional storage volume as the plurality of target data sets in an unfragmented order. A first volume serial number (VOLSER) of the fragmented storage volume is swapped with a second VOLSER of the additional storage volume. The fragmented storage volume is varied offline, and the additional storage volume is varied online. The computing environment recognizes the additional storage volume having the plurality of target data sets placed in the unfragmented order.Type: GrantFiled: January 15, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Harold Steven Huber, David Charles Reed, Max Douglas Smith
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Publication number: 20110307677Abstract: In a device for managing data buffers in a memory space distributed over a plurality of memory elements, the memory space is allocatable by memory pages, each buffer including one or more memory pages. The buffers are usable by at least one processing unit for the execution of an application, the application being executed by a plurality of processing units executing tasks in parallel. The memory elements are accessible in parallel by the processing units. The device includes means for allocating buffers to the tasks during the execution of the application and means for managing access rights to the buffers. The means for managing the access rights to the buffers include means for managing access rights to the pages in a given buffer, to verify that writing to a given page does not modify data currently being read from the page or that reading from a given page does not access data currently being written to the page, in such a way as to share the buffer between unsynchronized tasks.Type: ApplicationFiled: October 20, 2009Publication date: December 15, 2011Applicant: Commissariat A L'Energie Atomique Et Aux Energies AlternativesInventors: Raphael David, Nicolas Ventroux
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Patent number: 8065473Abstract: A method for controlling a memory card which includes a nonvolatile semiconductor memory whose memory area includes a plurality of write areas is disclosed. A first area which is a part of the plurality of write areas is set in accordance with management executed by a first file system. The first file system sequentially writes data along a direction in which addresses of the plurality of write areas increase. A second area which is a part of the plurality of write areas is set in accordance with management executed by a second file system. The second file system writes data in an order which does not depend on the addresses.Type: GrantFiled: June 10, 2010Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takafumi Ito, Hiroyuki Sakamoto
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Patent number: 8060689Abstract: A method includes configuring a flash memory device including a first memory sector having a primary memory sector correspondence, a second memory sector having an alternate memory sector correspondence, and a third memory sector having a free memory sector correspondence, copying a portion of the primary memory sector to the free memory sector, erasing the primary memory sector, and changing a correspondence of each of the first memory sector, the second memory sector, and the third memory sector.Type: GrantFiled: May 4, 2010Date of Patent: November 15, 2011Assignee: Pitney Bowes Inc.Inventors: Wesley A. Kirschner, Gary S. Jacobson, John A. Hurd, G. Thomas Atthens, Steven J. Pauly, Richard C. Day, Jr.
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Patent number: 8051269Abstract: A computer program product and apparatus for reallocating memory in a logically partitioned environment. The invention comprises a Performance Enhancement Program (PEP) and a Reallocation Program (RP). The PEP allows an administrator to designate several parameters and identify donor and recipient candidates. The RP compiles the performance data for the memory and calculates a composite parameter. For each memory block in the donor candidate pool, the RP compares the composite parameter to the donor load threshold to determine if the memory is a donor. For each memory block in the recipient candidate pool, the RP compares the composite parameter to the recipient load threshold to determine if the memory is a recipient. The RP calculates the recipient workload ratio and allocates the memory from the donors to the recipients. The RP monitors and update the workload statistics based on either a moving window or a discrete window sampling system.Type: GrantFiled: November 25, 2008Date of Patent: November 1, 2011Assignee: International Business Machines CorporationInventors: Rick Allen Hamilton, II, James Wesley Seaman
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Patent number: 8051265Abstract: An apparatus for managing memory in a real-time embedded system and a method of allocating, deallocating and managing memory in a real-time embedded system. The apparatus includes a defragmentation unit performing a defragmentation task according to a predetermined priority to collect together memory fragments, and a memory manager allocating or deallocating a predetermined area of memory upon request of a task, and calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task. The method of managing memory in a real-time embedded system includes determining whether the conditions under which the memory is used vary, and if the condition vary, calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task according to the memory fragmentation rate.Type: GrantFiled: May 20, 2008Date of Patent: November 1, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-don Lee, Jeong-joon Yoo
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Patent number: 8037258Abstract: A design structure is provided for a dual-mode memory chip supporting a first operation mode in which received data access commands contain chip select data to identify the chip addressed by the command, and control logic in the memory chip determines whether the command is addressed to the chip, and a second operation mode in which the received data access command addresses a set of multiple chips. Preferably, the first mode supports a daisy-chained configuration of memory chips. Preferably the second mode supports a hierarchical interleaved memory subsystem, in which each addressable set of chips is configured as a tree, command and write data being propagated down the tree, the number of chips increasing at each succeeding level of the tree.Type: GrantFiled: March 21, 2008Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, John M. Borkenhagen, Philip Raymond Germann
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Patent number: 8037272Abstract: A design structure is provided for a memory module containing an interface for receiving memory access commands from an external source, in which a first portion of the interface receives memory access data at a first bus frequency and a second portion of the interface receives memory access data at a second different bus frequency. Preferably, the memory module contains a second interface for re-transmitting memory access data, also operating at dual frequency. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports dual-speed buses for receiving and re-transmitting different parts of data access commands, and another of which supports conventional daisy-chaining.Type: GrantFiled: March 21, 2008Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, John M. Borkenhagen, Philip Raymond Germann
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Patent number: 8037270Abstract: A design structure is provided for a memory module containing a first interface for receiving data access commands and a second interface for re-transmitting data access commands to other memory modules, the second interface propagating multiple copies of received data access commands to multiple other memory modules. The memory module is preferably used in a high-capacity memory subsystem organized in a tree configuration in which data accesses are interleaved. Preferably, the memory module has multiple-mode operation, one of which supports multiple replication of commands and another of which supports conventional daisy-chaining.Type: GrantFiled: March 21, 2008Date of Patent: October 11, 2011Assignee: International Business Machines CorporationInventors: Gerald K. Bartley, John M. Borkenhagen, Philip Raymond Germann
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Patent number: 7975123Abstract: To provide a computer system, a management computer and a storage system, and a storage area allocation amount controlling method for improving I/O performance of the host computer. In a computer system comprising a storage system comprising one or more storage devices with storage areas, a host computer which uses a storage area of the storage device, and a management computer for dynamically allocating the storage area in response to an input/output request from the host computer; wherein the management computer monitors dynamic allocation of a real storage area to a storage area in the storage system, and calculates allocation increment amount to the allocated storage area based on the allocation frequency and the total amount of allocation.Type: GrantFiled: August 10, 2009Date of Patent: July 5, 2011Assignee: Hitachi, Ltd.Inventors: Daisuke Shinohara, Masayuki Yamamoto, Yasunori Kaneda
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Patent number: 7930489Abstract: Techniques for optimizing configuration partitioning are disclosed. In one particular exemplary embodiment, the techniques may be realized as a system for configuration partitioning comprising a module for providing one or more policy managers, a module for providing one or more applications, the one or more applications assigned to one or more application groups, a module for associating related application groups with one or more blocks, and a module for assigning each of the one or more blocks to one of the one or more policy managers, wherein if one or more of the one or more blocks cannot be assigned to a policy manager, breaking the one or more blocks into the one or more application groups and assigning the one or more application groups to one of the one or more policy managers.Type: GrantFiled: March 28, 2008Date of Patent: April 19, 2011Assignee: Symantec CorporationInventors: Sachin Vaidya, Tushar Bandopadhyay
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Patent number: 7908454Abstract: Tools and techniques for application-specific heap management are described herein. The tools may provide machine-readable storage media containing machine-readable instructions for profiling an application to facilitate managing heap memory associated with the application, and for managing requests from the application to allocate or deallocate from the heap memory based on the profiling. The tools may also receive requests from the application to allocate buffers, and may determine whether an instance-level memory pool, which is associated with a portion of the application, contains enough free buffers to satisfy the request. Finally, the tools may receive requests from the application to deallocate buffers, and in response to the request, may deallocate the requested buffers into the instance-level memory pool. The tools may also determine whether the instance-level memory pool contains a number of free buffers that exceeds a threshold.Type: GrantFiled: June 26, 2007Date of Patent: March 15, 2011Assignee: Microsoft CorporationInventors: Yiu-Ming Leung, Jiannan Zheng
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Patent number: 7904669Abstract: An information processing device for executing a data recording process for a flash memory having a primary data storage region and a data storage region includes a control unit operable to detect a data recording state of the primary data storage region of the flash memory, and when the data recording state is a predefined state, to execute a data connecting process of connecting data recorded in the primary data storage region and a data writing process of writing the connected data in the data storage region.Type: GrantFiled: November 14, 2006Date of Patent: March 8, 2011Assignee: Sony CorporationInventor: Atsushi Mae
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Patent number: 7904688Abstract: The invention relates to methods and apparatus for offloading the workload from a computer system's CPU, memory and/or memory controller. Methods and apparatus for managing board memory on a FPGA board on behalf of applications executing in one or more FPGAs are disclosed.Type: GrantFiled: December 21, 2005Date of Patent: March 8, 2011Assignee: Trend Micro IncInventors: Kuo-Sheng Kuo, Kai-Chau Yang, Yen-Tsung Chia
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Patent number: 7890730Abstract: Embodiments described herein disclose methods and devices for expanding the storage capacity in a storage device, including the steps of: creating at least one partition in a storage memory of the storage device; designating a reserved-storage area and an enabled-storage area in at least one partition; storing a partition size in a FAT of the storage memory; and upon authorization, increasing the partition size to include sectors in the reserved-storage area, thereby expanding the storage capacity in a storage device. Preferably, the reserved-storage area is not accessible by a host system. Preferably, the partition size is determined from a partition range stored in a master boot record in the storage memory. Most preferably, the partition range is determined from an enabled capacity stored in a memory-management area in the storage memory, and wherein the memory-management area is not accessible by a host system.Type: GrantFiled: December 23, 2007Date of Patent: February 15, 2011Assignee: SanDisk IL LtdInventors: Micha Rave, Eitan Mardiks
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Patent number: 7886107Abstract: A data processor that erases data stored in a storage device includes an erase information storage unit that stores an erase information indicating a description of an erasing process having been performed, corresponding to an erase-specified area, after the erasing process for the erase-specified area, being an area specified to be subjected to the erasing process, is performed.Type: GrantFiled: January 3, 2007Date of Patent: February 8, 2011Assignee: Fuji Xerox Co., Ltd.Inventor: Nobukazu Miyoshi
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Patent number: 7870359Abstract: A method for managing computer memory, in accordance with the present invention, includes maintaining multiple sets of free blocks of memory wherein a free block is added to a set based on its size. In response to a request for a block of a request size, a set of blocks is searched for a free block which is at least as large as the request size but smaller than the request size plus a threshold. If such a block is found, the block is allocated in its entirety.Type: GrantFiled: October 18, 2007Date of Patent: January 11, 2011Assignee: International Business Machines CorporationInventors: James R. H. Challenger, Arun K. Iyengar
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Patent number: 7849263Abstract: A data storage system has a first set of storage devices, a second set of storage devices, and a controller. The controller is arranged to (i) activate a first set of storage devices and deactivate a second set of storage devices prior to an amount of storage capacity currently used in the data storage system reaching a predefined storage capacity threshold of the data storage system. The controller is further arranged to (i) monitor the amount of storage capacity currently used in the data storage system in view of the predefined storage capacity threshold, and (ii) maintain activation of the first set of storage devices and automatically activate the second set of storage devices in response to the amount of storage capacity currently used in the data storage system reaching the predefined storage capacity threshold.Type: GrantFiled: December 24, 2007Date of Patent: December 7, 2010Assignee: EMC CorporationInventor: F. William French
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Patent number: 7827373Abstract: A method includes executing one or more applications in an execution environment. The one or more applications are capable of requesting allocation of memory during execution. The method also includes allocating a plurality of memory blocks in a heap to the one or more executing applications. The plurality of memory blocks are allocated sequentially in the heap to the one or more executing applications. In addition, the method includes deallocating the plurality of memory blocks during a single deallocation. Memory blocks in multiple heaps could be allocated to the one or more executing applications. A particular memory block in a particular heap could be allocated to a particular executing application by pushing an indicator identifying the particular heap onto a stack. The particular memory block is allocated in the particular heap based on the indicator, and the indicator is popped from the stack after allocation.Type: GrantFiled: October 31, 2005Date of Patent: November 2, 2010Assignee: Honeywell International Inc.Inventors: Ziad M. Kaakani, Pratap Parashuram, Elliott H. Rachlin, Jethro F. Steinman
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Publication number: 20100262793Abstract: A method in one embodiment includes writing first data to a first memory device of a memory array at a first number of writes per unit time; writing second data to a second memory device of the memory array at a second number of writes per unit time; and skewing expected wearout times of the memory devices by making the second number of writes per unit time less than the first number of writes per unit time. A method in another embodiment includes writing first data to a first memory device of a memory array; writing second data to a second memory device of the memory array; and skewing expected wearout times of the memory devices by making a number of available storage units cm the second memory device less than a number of available storage units on the first memory device.Type: ApplicationFiled: April 8, 2009Publication date: October 14, 2010Inventor: Steven Robert Hetzler
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Publication number: 20100262752Abstract: A controller of a Solid State Device (SSD) defines a mapping from memory devices, such as flash packages, that make up the SSD to one or more storage virtual containers. The storage virtual containers are exposed to an operating system by the controller through an interface. The operating system may then make operation requests to the one or more storage virtual containers, and the controller may use the mapping to fulfill the operation requests from the corresponding flash packages. The storage virtual containers are mapped to the flash packages to take advantage of the parallelism of the flash packages in the SSD so that the controller may fulfill operation requests received from the operating system in parallel.Type: ApplicationFiled: April 8, 2009Publication date: October 14, 2010Applicant: Microsoft CorporationInventors: John D. Davis, Vijayan Prabhakaran
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Patent number: 7747812Abstract: A method includes configuring a flash memory device including a first memory sector having a primary memory sector correspondence, a second memory sector having an alternate memory sector correspondence, and a third memory sector having a free memory sector correspondence, copying a portion of the primary memory sector to the free memory sector, erasing the primary memory sector, and changing a correspondence of each of the first memory sector, the second memory sector, and the third memory sector.Type: GrantFiled: December 22, 2005Date of Patent: June 29, 2010Assignee: Pitney Bowes Inc.Inventors: Wesley A. Kirschner, Gary S. Jacobson, John A. Hurd, G. Thomas Athens, Steven J. Pauly, Richard C. Day, Jr.
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Publication number: 20100138626Abstract: A computationally implemented method, system, and product for managing maintenance activities in a storage control system are disclosed. A disk drive has a reservation status that is monitored. A reservation ID is assigned to a successful reservation request. The reservation ID of a drive request is compared to the reservation ID of a disk drive.Type: ApplicationFiled: December 2, 2008Publication date: June 3, 2010Inventors: James A. Lynn, Keith Kauffman
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Patent number: 7702850Abstract: A topology independent storage array. In a preferred embodiment the topology of the array is reconfigurable due to information control packets passed among storage nodes comprising the array. The topology of the array, as determine by the relationship between data sets stored within the array's storage nodes and storage maps of the storage node, can be reconfigured without requiring a complete duplication of the entire array. In especially preferred embodiments, the topology of the storage array follows a Z-10 or a Z-110 configuration where storage devices store one or more mirrored parts of a data set per storage device.Type: GrantFiled: July 1, 2005Date of Patent: April 20, 2010Inventors: Thomas Earl Ludwig, Charles William Frank
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Publication number: 20100095046Abstract: An invention is provided for improving performance in block based non-volatile memory when performing random small write operations. When requests for small page updates are received for a memory page currently storing data, the updated page data is written to a reserve memory page. The reserve memory page can be in the same memory block as the target memory page, or in an associated reserve memory block. In addition, the associated logical page address is temporarily remapped to the reserve page. Later, when time permits, the page data for the block can be reorganized into continuous pages in a new block.Type: ApplicationFiled: October 9, 2008Publication date: April 15, 2010Applicant: Denali Software, Inc.Inventors: Robert Alan Reid, Steven L. Shrader
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Publication number: 20100077158Abstract: A physical storage area that is allocated to an unused area of a virtual volume is removed. A management unit sends a request to a server computer to make every piece of data stored in a first logical volume migrate to a second logical volume. The server reads all the data out of the first logical volume and writes the data in the second logical volume. A storage system that includes the first logical volume and the second logical volume allocates a physical storage area to an area of the second logical volume where the data is to be written, and writes the data in the allocated physical storage area. The storage system then deletes the first logical volume.Type: ApplicationFiled: November 12, 2008Publication date: March 25, 2010Inventors: Masayasu ASANO, Koichi Murayama
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Publication number: 20100070684Abstract: A memory device preloads a command file and a plurality of response files. Whenever a host sends a command to the memory apparatus, the command assigns one of the response files; thereby the host can receive response of the memory apparatus by reading the assigned response file.Type: ApplicationFiled: December 30, 2008Publication date: March 18, 2010Applicant: INCOMM TECHNOLOGIES CO., LTD.Inventors: Hsiu-Hsien CHU, Pei-Tai CHEN
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Publication number: 20090210635Abstract: Intra-node data transfer in collective communications is facilitated. A memory object of one task of a collective communication is concurrently attached to the address spaces of a plurality of other tasks of the communication. Those tasks that attach the memory object can access the memory object as if it was their own. Data can be directly written into or read from an application data structure of the memory object by the attaching tasks without copying the data to/from shared memory.Type: ApplicationFiled: May 5, 2009Publication date: August 20, 2009Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert S. BLACKMORE, Bin JIA, Richard R. TREUMANN
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Publication number: 20090158008Abstract: A physical layer transport composite processing system used in a wireless communication system. A plurality of interconnected processing blocks are provided. The blocks are interconnected by a read data bus, a write data bus and a control bus. The blocks include a transport channel processing block, a composite channel processing block and a chip rate processing block. At least two of the blocks are capable of processing data for a plurality of wireless formats. A first set of parameters is programmed into the blocks for a particular wireless mode. The blocks are operated to process data in the particular wireless format mode.Type: ApplicationFiled: February 23, 2009Publication date: June 18, 2009Applicant: INTERDIGITAL TECHNOLOGY CORPORATIONInventors: Edward L. Hepler, Michael F. Starsinic, David S. Bass, Binish Desai, Alan M. Levi, George W. McClellan, Douglas R. Castor
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Publication number: 20090150633Abstract: An apparatus for managing memory in a real-time embedded system and a method of allocating, deallocating and managing memory in a real-time embedded system. The apparatus includes a defragmentation unit performing a defragmentation task according to a predetermined priority to collect together memory fragments, and a memory manager allocating or deallocating a predetermined area of memory upon request of a task, and calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task. The method of managing memory in a real-time embedded system includes determining whether the conditions under which the memory is used vary, and if the condition vary, calculating a memory fragmentation rate of the memory to determine a priority of the defragmentation task according to the memory fragmentation rate.Type: ApplicationFiled: May 20, 2008Publication date: June 11, 2009Applicant: Samsung Electronics Co., Ltd.Inventors: Jae-don Lee, Jeong-joon Yoo
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Publication number: 20090129588Abstract: An information processing apparatus capable of effectively preventing unauthorized use of content distributed through a network when playing the content. The information processing apparatus includes a tamper-resistant secure module, a receiving block, and a playback block. The secure module includes a key storage block for storing a decryption key, a decryption block, and an encryption block. The receiving block receives distribution data distributed through the network and transfers the data to the decryption block. The decryption block decrypts the distribution data to obtain content by using the decryption key. The encryption block divides the content to a plurality of split pieces of content and encrypts them by using a temporary encryption key. Information on a temporary decryption key is output each time the temporary encryption key is changed. The playback block decrypts the encrypted pieces of content by using the temporary decryption key and combines and plays them.Type: ApplicationFiled: October 26, 2007Publication date: May 21, 2009Applicant: FUJITSU LIMITEDInventors: Masakazu TAKAKUSU, Kiyoshi KOHIYAMA, Tetsuya SASAO