Using Pseudo-associative Means, E.g., Set-associative, Hashing, Etc. (epo) Patents (Class 711/E12.018)
  • Patent number: 10877839
    Abstract: A system, and corresponding method, is described for correcting an uncorrectable error in a coherent system. The uncorrectable error is detecting using an error detecting code, such as parity or SECDED. The cache controller or agent calculates a set of possible addresses. The directory is queried to determine which one of the set of possible addresses is the correct address. The agent and/or cache controller is updated with the correct address or way. The invention can be implemented in any chip, system, method, or HDL code that perform protection schemes and require ECC calculation, of any kind. Embodiments of the invention enable IPs that use different protections schemes to reduce power consumption and reduce bandwidth access to more efficiently correct errors and avoid a system restart when an uncorrectable error occurs.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: December 29, 2020
    Assignee: ARTERIS, INC.
    Inventor: Parimal Gaikwad
  • Patent number: 10324853
    Abstract: The present invention provides a cache method and a cache system. The cache method includes the following steps. An instruction issuing is scheduled based on a program flow information stored in a cache system. The program flow information includes an instruction sequence information and an instruction distance information. A time point for the instruction issuing is determined based on the instruction sequence information and the instruction distance information.
    Type: Grant
    Filed: March 30, 2015
    Date of Patent: June 18, 2019
    Assignee: SHANGHAI XINHAO MICROELECTRONICS CO., LTD.
    Inventor: Kenneth Chenghao Lin
  • Patent number: 10162005
    Abstract: A number of embodiments include an apparatus comprising a memory array including a first memory bank and a second memory bank and a serializer/de-serializer coupled to the first memory bank and the second memory bank. The serializer/de-serializer may be configured to receive a scan vector from the first memory bank, send the scan vector to a device under test, receive scan test responses from the device under test, and send the scan test responses to the second memory bank. Scan control logic may be coupled to the serializer/de-serializer and the device under test. The scan control logic may be configured to control operation of the serializer/de-serializer and send a scan chain control signal to the device under test, wherein the scan chain control signal is to initiate performance of a scan chain operation using the scan vector.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: December 25, 2018
    Assignee: Micron Technology, Inc.
    Inventor: Joshua E. Alzheimer
  • Patent number: 9886399
    Abstract: Data are stored using a writing method according to the property of the data in a storage device. An area defining unit defines, in a second memory, a system area for storing system information causing a system to operate and a cache area temporarily storing data of a first memory. A moving processing unit moves data stored in the cache area to the first memory at a predetermined point in time. An access control unit accesses the second memory in accordance with the definition with regard to access corresponding to the system area or the cache area, and read data from the first memory with regard to read-access corresponding to those other than the system area and the cache area.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: February 6, 2018
    Assignee: Sony Corporation
    Inventors: Ken Ishii, Keiichi Tsutsui, Ryoji Ikegaya
  • Patent number: 9817763
    Abstract: A method of establishing pre-fetch control information from an executable code is described. The method comprises inspecting the executable code to find one or more instructions corresponding to an unconditional change in program flow during an execution of the executable code when the executable code is retrieved from a non-volatile memory comprising a plurality of NVM lines.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: November 14, 2017
    Assignee: NXP USA, Inc.
    Inventors: Alistair Robertson, Nancy Amedeo, Mark Maiolani
  • Patent number: 9477479
    Abstract: A sequence of buffered instructions includes branch instructions. Branch prediction circuitry predicts if each branch instruction will result in a taken branch when executed. Normally, the fetch circuitry retrieves speculative instructions between the time that a source branch instruction is retrieved and the prediction if that source branch instruction will result in the taken branch. If the source branch instruction is predicted as taken, then the speculative instructions are discarded, and a count value indicates a number of instructions in the sequence between that source branch instruction and a subsequent branch instruction in the sequence that is also predicted as taken. Responsive to a subsequent occurrence of the source branch instruction predicted as taken, a throttled mode limits the number of instructions subsequently retrieved dependent on the count value, and then any further instructions are not retrieved for a number of clock cycles.
    Type: Grant
    Filed: June 11, 2014
    Date of Patent: October 25, 2016
    Assignee: ARM Limited
    Inventor: Peter Richard Greenhalgh
  • Patent number: 8990505
    Abstract: Devices, systems, methods, and other embodiments associated with a cache memory are described. In one embodiment, a cache tag array includes tag banks. The cache memory further includes a bank selector configured to receive an address and to apply a hash function that maps the address to one of the tag banks.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: March 24, 2015
    Assignee: Marvell International Ltd.
    Inventors: Sujat Jamil, R. Frank O'Bleness, David E. Miner, Joseph Delgross, Tom Hameenanttila
  • Patent number: 8977817
    Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple small sections, and each section is supplied with power from a separately controllable power supply. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. Incoming requests are grouped together based on which section of the system cache they target. When enough requests that target a given section have accumulated, the voltage supplied to the given section is increased to a voltage sufficient for access. Then, once the given section has enough time to ramp-up and stabilize at the higher voltage, the waiting requests may access the given section in a burst of operations.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: March 10, 2015
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Shinye Shiu
  • Patent number: 8966182
    Abstract: A pattern matching accelerator (PMA) for assisting software threads to find the presence and location of strings in an input data stream that match a given pattern. The patterns are defined using regular expressions that are compiled into a data structure comprised of rules subsequently processed by the PMA. The patterns to be searched in the input stream are defined by the user as a set of regular expressions. The patterns to be searched are grouped in pattern context sets. The sets of regular expressions which define the pattern context sets are compiled to generate a rules structure used by the PMA hardware. The rules are compiled before search run time and stored in main memory, in rule cache memory within the PMA or a combination thereof. For each input character, the PMA executes the search and returns the search results.
    Type: Grant
    Filed: February 8, 2011
    Date of Patent: February 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Giora Biran, Christoph Hagleitner, Timothy H. Heil, Russell D. Hoover, Jan Van Lunteren
  • Patent number: 8954693
    Abstract: A memory controller comprises a host interface block comprising a compression ratio calculator configured to determine whether a compression ratio of input data exceeds a predetermined compression ratio, and a compression block configured to compress the input data as a consequence of the host compression ratio calculator determining that the compression ratio exceeds the predetermined compression ratio.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: February 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Mankeun Seo, Daewook Kim, Hong Rak Son, Junjin Kong, Seonghoon Woo, Soonjae Won, Pilsang Yoon
  • Patent number: 8924649
    Abstract: A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a unified cache controller, and a control register to selectively mask off access by the unified cache controller to portions of the unified cache. Other embodiments are also described and claimed.
    Type: Grant
    Filed: February 3, 2014
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Timothy J. Callahan, Snigdha Jana, Nandan A. Kulkarni
  • Patent number: 8914580
    Abstract: In some embodiments, a cache may include a tag array and a data array, as well as circuitry that detects whether accesses to the cache are sequential (e.g., occupying the same cache line). For example, a cache may include a tag array and a data array that stores data, such as multiple bundles of instructions per cache line. During operation, it may be determined that successive cache requests are sequential and do not cross a cache line boundary. Responsively, various cache operations may be inhibited to conserve power. For example, access to the tag array and/or data array, or portions thereof, may be inhibited.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: December 16, 2014
    Assignee: Apple Inc.
    Inventors: Rajat Goel, Ian D. Kountanis
  • Patent number: 8862827
    Abstract: A cache manager receives a request for data, which includes a requested effective address. The cache manager determines whether the requested effective address matches a most recently used effective address stored in a mapped tag vector. When the most recently used effective address matches the requested effective address, the cache manager identifies a corresponding cache location and retrieves the data from the identified cache location. However, when the most recently used effective address fails to match the requested effective address, the cache manager determines whether the requested effective address matches a subsequent effective address stored in the mapped tag vector. When the cache manager determines a match to a subsequent effective address, the cache manager identifies a different cache location corresponding to the subsequent effective address and retrieves the data from the different cache location.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Brian Flachs, Barry L. Minor, Mark Richard Nutter
  • Patent number: 8856448
    Abstract: Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a potential invalidation of a data cache entry. The coherency information in association with the data cache entry is retained to track the potential invalidation to the data cache entry. The retained coherency information is kept separate from state bits that are utilized in cache access operations. An invalidate bit, associated with a data cache entry, may be utilized to represents a potential invalidation of the data cache entry. The invalidate bit is set in response to the coherency information, to track the potential invalidation of the data cache entry. A valid bit associated with the data cache entry is set in response to the active invalidate bit and a memory synchronization command. The set invalidate bit is cleared after the valid bit has been cleared.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: October 7, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Michael W. Morrow, James Norris Dieffenderfer
  • Patent number: 8832378
    Abstract: A method for selecting a cache way, the method includes: selecting an initially selected cache way out of multiple cache ways of a cache module for receiving a data unit; the method being characterized by including: searching, if the initially selected cache way is locked, for an unlocked cache way, out of at least one group of cache ways that are located at predefined offsets from the first cache way.
    Type: Grant
    Filed: April 11, 2008
    Date of Patent: September 9, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Rotem Porat, Moshe Anschel, Alon Eldar, Amit Gur, Shai Koren, Itay Peled
  • Patent number: 8806175
    Abstract: A hash table system having a first hash table and a second hash table is provided. The first hash table may be in-memory and the second hash table may be on-disk. Inserting an entry to the hash table system comprises inserting the entry into the first hash table, and, when the first hash table reaches a threshold load factor, flushing entries into the second hash table. Flushing the first hash table into the second hash table may comprise sequentially flushing the first hash table segments into corresponding second hash table segments. When looking up a key/value pair corresponding to a selected key in the hash table system, the system checks both the first and second hash tables for values corresponding to the selected key. The first and second hash tables may be divided into hash table segments and collision policies may be implemented within the hash table segments.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: August 12, 2014
    Assignee: Longsand Limited
    Inventors: Peter D. Beaman, Robert S. Newson, Tuyen M. Tran
  • Patent number: 8806173
    Abstract: A storage device includes first and second buffers. A request to write a new record from a host is received. A hash value (new S) of the new record is calculated. The hash value (new S) of the new record is checked to determine if the hash value exists in a second buffer. If the new S exists in the second buffer, the new record is compared with a record stored in the second buffer corresponding to the new S to check if the new record and the stored record in the second buffer match each other. If the new record and the stored record match each other, a pointer (a record number) is written as write data of the new record to the recording medium. The pointer points to the record already stored in any one of a recording medium and the second buffer.
    Type: Grant
    Filed: August 24, 2011
    Date of Patent: August 12, 2014
    Assignee: International Business Machines Corporation
    Inventor: Yutaka Oishi
  • Patent number: 8738858
    Abstract: A method, computer program product, and computing system for receiving a read request on a first cache system, wherein the read request identifies previously-written content included within a data array. The previously-written content identified in the read request is obtained from the data array. A read request content identifier is generated for the previously-written content identified in the read request. The read request content identifier associated with the previously-written content identified in the read request is compared to a plurality of content identifiers included within a content directory for the first cache system to determine if a matching content identifier exists. Each of the plurality of content identifiers is associated with a piece of previously-written content included within the first cache system.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 27, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Alex Veprinsky
  • Patent number: 8738857
    Abstract: A method, computer program product, and computing system for receiving a read request on a first cache system, wherein the read request identifies previously-written content included within a data array. A read request content identifier associated with the previously-written content identified in the read request is received from the data array. The read request content identifier associated with the previously-written content identified in the read request is compared to a plurality of content identifiers included within a content directory for the first cache system to determine if a matching content identifier exists. Each of the plurality of content identifiers is associated with a piece of previously-written content included within the first cache system.
    Type: Grant
    Filed: November 30, 2011
    Date of Patent: May 27, 2014
    Assignee: EMC Corporation
    Inventors: Roy E. Clark, Alex Veprinsky
  • Publication number: 20140136813
    Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs), multiple reference values, and multiple mask values from memory. A selecting circuit within the TM uses a starting bit position and a mask size to select a portion of the IV. The portion of the IV is a lookup key value (LKV). The LKV is masked by each mask value thereby generating multiple masked values. Each masked value is compared to a reference value thereby generating multiple comparison values. A lookup table generates a selector value based upon the comparison values. A result value is selected based on the selector value. The selected result value is then communicated to the processor via the bus.
    Type: Application
    Filed: November 13, 2012
    Publication date: May 15, 2014
    Applicant: Netronome Systems, Inc.
    Inventor: Gavin J. Stark
  • Publication number: 20140136787
    Abstract: Systems, methods, and other embodiments associated with speculating whether a read request will cause an access to a memory are described. In one embodiment, a method includes detecting, in a memory, a read request from a processor and speculating whether the read request will cause an access to a memory bank in the memory based, at least in part, on an address identified by the read request. The method selectively enables power to the memory bank in the memory based, at least in part, on speculating whether the read request will cause an access to the memory bank.
    Type: Application
    Filed: November 9, 2012
    Publication date: May 15, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Hoyeol CHO, Ioannis ORGINOS, Jinho KWACK
  • Patent number: 8713258
    Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for estimating the stack distance of an access to a cache. In one aspect, a method includes determining a current estimate value of the stack distance. For each of K buckets, a minimum value and a maximum value are initialized, wherein each bucket corresponds to a range of possible fingerprint values for accesses. A first access is processed, including: determining a first fingerprint value for the first access; identifying a first bucket for the first access based on the first fingerprint value; and determining that the first fingerprint value is between the minimum value and the maximum value for the first bucket, and in response, increasing the current estimate value and adjusting the minimum value or the maximum value for the first bucket.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: April 29, 2014
    Assignee: Google Inc.
    Inventor: Robert Cypher
  • Patent number: 8694732
    Abstract: A method and system for precisely tracking lines evicted from a region coherence array (RCA) without requiring eviction of the lines from a processor's cache hierarchy. The RCA is a set-associative array which contains region entries consisting of a region address tag, a set of bits for the region coherence state, and a line-count for tracking the number of region lines cached by the processor. Tracking of the RCA is facilitated by a non-tagged hash table of counts represented by a Region Victim Hash (RVH). When a region is evicted from the RCA, and lines from the evicted region still reside in the processor's caches (i.e., the region's line-count is non-zero), the RCA line-count is added to the corresponding RVH count. The RVH count is decremented by the value of the region line count following a subsequent processor cache eviction/invalidation of the region previously evicted from the RCA.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: April 8, 2014
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Bell, Jason F. Cantin
  • Publication number: 20140095777
    Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple small sections, and each section is supplied with power from a separately controllable power supply. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. Incoming requests are grouped together based on which section of the system cache they target. When enough requests that target a given section have accumulated, the voltage supplied to the given section is increased to a voltage sufficient for access. Then, once the given section has enough time to ramp-up and stabilize at the higher voltage, the waiting requests may access the given section in a burst of operations.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: APPLE INC.
    Inventors: Sukalpa Biswas, Shinye Shiu
  • Publication number: 20140095794
    Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Jaideep MOSES, Ravishankar IYER, Ramesh G. ILLIKKAL, Sadagopan SRINIVASAN
  • Publication number: 20140089590
    Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and individual ways are powered down when cache activity is low. A maximum active way configuration register is set by software and determines the maximum number of ways which are permitted to be active. When searching for a cache line replacement candidate, a linear feedback shift register (LFSR) is used to select from the active ways. This ensures that each active way has an equal chance of getting picked for finding a replacement candidate when one or more of the ways are inactive.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Applicant: APPLE INC.
    Inventors: Sukalpa Biswas, Shinye Shiu, Rong Zhang Hu
  • Patent number: 8650370
    Abstract: A non-transitory computer-readable medium storing an data storing program executed by an archive device including a first storage unit for storing data and a second storage unit for storing hash value determined from the data, the program causing the archive device to execute a process includes receiving hash value determined from data to be stored from an external device which requests storage of the data, comparing the received hash value with the hash value stored in the second storage unit, and transmitting request information for transmitting the data corresponding to the received hash value to the external device which transmits the hash value when the received hash value has not been stored in the second storage unit.
    Type: Grant
    Filed: July 12, 2010
    Date of Patent: February 11, 2014
    Assignee: Fujitsu Limited
    Inventor: Noboru Ooguri
  • Patent number: 8645629
    Abstract: A persistent cacheable high volume manufacturing (HVM) initialization code is generally presented. In this regard, an apparatus is introduced comprising a processing unit, a unified cache, a unified cache controller, and a control register to selectively mask off access by the unified cache controller to portions of the unified cache. Other embodiments are also described and claimed.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: February 4, 2014
    Assignee: Intel Corporation
    Inventors: Timothy J. Callahan, Snigdha Jana, Nandan A. Kulkarni
  • Publication number: 20140025881
    Abstract: Associative index extended (AIX) caches can be functionally implemented through a reconfigurable decoder that employs programmable line decoding. The reconfigurable decoder features scalability in the number of lines, the number of index extension bits, and the number of banks. The reconfigurable decoder can switch between pure direct mapped (DM) mode and direct mapped-associative index extended (DM-AIX) mode of operation. For banked configurations, the reconfigurable decoder provides the ability to run some banks in DM mode and some other banks in DM-AIX mode. A cache employing this reconfigurable decoder can provide a comparable level of latency as a DM cache with minimal modifications to a DM cache circuitry of an additional logic circuit on a critical signal path, while providing low power operation at low area overhead with SA cache-like miss rates. Address masking and most-recently-used-save replacement policy can be employed with a single bit overhead per line.
    Type: Application
    Filed: July 17, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajiv V. Joshi, Ajay N. Bhoj
  • Patent number: 8631207
    Abstract: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
    Type: Grant
    Filed: December 26, 2009
    Date of Patent: January 14, 2014
    Assignee: Intel Corporation
    Inventors: Zhen Fang, Meenakshisundara R. Chinthamani, Li Zhao, Milind B. Kamble, Ravishankar Iyer, Seung Eun Lee, Robert S. Chappell, Ryan L. Carlson
  • Publication number: 20140013025
    Abstract: A hybrid memory system includes a primary memory comprising a host memory space arranged as memory sectors corresponding to host logical block addresses (host LBAs). A secondary memory is implemented as a cache for the primary host memory. A hybrid controller is configured map the clusters of host LBAs to clusters of solid state drive (SSD) LBAs. The SSD LBAs correspond to a memory space of the cache. Mapping of the host LBA clusters to the SSD LBA clusters is fully associative such that any host LBA cluster can be mapped to any SSD LBA cluster.
    Type: Application
    Filed: July 6, 2012
    Publication date: January 9, 2014
    Applicant: SEAGATE TECHNOLOGY LLC
    Inventor: Sumanth Jannyavula Venkata
  • Publication number: 20140006714
    Abstract: An apparatus of an aspect includes a plurality of cores. The plurality of cores are logically grouped into a plurality of clusters. A cluster sharing map-based coherence directory is coupled with the plurality of cores and is to track sharing of data among the plurality of cores. The cluster sharing map-based coherence directory includes a tag array to store corresponding pairs of addresses and cluster identifiers. Each of the addresses is to identify data. Each of the cluster identifiers is to identify one of the clusters. The cluster sharing map-based coherence directory also includes a cluster sharing map array to store cluster sharing maps. Each of the cluster sharing maps corresponds to one of the pairs of addresses and cluster identifiers. Each of the cluster sharing maps is to indicate intra-cluster sharing of data identified by the corresponding address within a cluster identified by the corresponding cluster identifier.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Naveen Cherukuri, Mani Azimi
  • Patent number: 8621182
    Abstract: Systems and methods for managing mapping information for objects maintained in a distributed storage system are provided. The distributed storage system can include a keymap subsystem that manages the mapping information according to object keys. Requests for specific object mapping information are directed to specific keymap coordinators within the keymap subsystem. Each keymap coordinator can maintain a cache for caching mapping information maintained at various information sources. Additionally, the keymap coordinators can optimize cache entries by maintaining selected mapping information while identifying object sources that correspond to differences from the selected mapping information.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: December 31, 2013
    Assignee: Amazon Technologies, Inc.
    Inventors: James Christopher Sorenson, III, Gunavardhan Kakulapati, Jason G. McHugh
  • Publication number: 20130346683
    Abstract: A cache subsystem apparatus and method of operating therefor is disclosed. In one embodiment, a cache subsystem includes a cache memory divided into a plurality of sectors each having a corresponding plurality of cache lines. Each of the plurality of sectors is associated with a sector dirty bit that, when set, indicates at least one of its corresponding plurality of cache lines is storing modified data of any other location in a memory hierarchy including the cache memory. The cache subsystem further includes a cache controller configured to, responsive to initiation of a power down procedure, determine only in sectors having a corresponding sector dirty bit set which of the corresponding plurality of cache lines is storing modified data.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Inventor: William L. Walker
  • Publication number: 20130346699
    Abstract: The present application describes embodiments of a method and apparatus for concurrently accessing dirty bits in a cache. One embodiment of the apparatus includes a cache configurable to store a plurality of lines. The lines are grouped into a plurality of subsets the plurality of lines. This embodiment of the apparatus also includes a plurality of dirty bits associated with the plurality of lines and first circuitry configurable to concurrently access the plurality of dirty bits associated with at least one of the plurality of subsets of lines.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Inventor: WILLIAM L. WALKER
  • Publication number: 20130339596
    Abstract: Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory. Based on determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory a cache set of the multi-set associative cache that contains a cache line referenced by the instruction fetch address is identified and only powering up a subset of cache. Based on the identified cache set not being powered up, selectively powering up the identified cache set of the multi-set associative cache and transmitting one or more instructions stored in the cache line referenced by the instruction fetch address to a processor.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brian R. Prasky, Anthony Saporito, Aaron Tsai
  • Publication number: 20130339613
    Abstract: Embodiments relate to storing data to a system memory. An aspect includes accessing successive entries of a cache directory having a plurality of directory entries by a stepper engine, where access to the cache directory is given a lower priority than other cache operations. It is determined that a specific directory entry in the cache directory has a change line state that indicates it is modified. A store operation is performed to send a copy of the specific corresponding cache entry to the system memory as part of a cache management function. The specific directory entry is updated to indicate that the change line state is unmodified.
    Type: Application
    Filed: June 13, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Blake, Pak-Kin Mak, Timothy C. Bronson, Hieu T. Huynh, Kenneth D. Klapproth, Vesselina K. Papazova
  • Publication number: 20130297879
    Abstract: A computer cache memory organization called Probabilistic Set Associative Cache (PAC) has the hardware complexity and latency of a direct-mapped cache but functions as a set-associative cache for a fraction of the time, thus yielding better than direct mapped cache hit rates. The organization is considered a (1+P)—way set associative cache, where the chosen parameter called Override Probability P determines the average associativity, for example, for P=0.1, effectively it operates as if a 1.1-way set associative cache.
    Type: Application
    Filed: May 1, 2012
    Publication date: November 7, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent Abali, John S. Dodson, Moinuddin K. Qureshi, Balaram Sinharoy
  • Patent number: 8572324
    Abstract: A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, a multiplicity of computer processors, each computer processor implementing a plurality of hardware threads of execution; and computer memory, the computer memory organized in pages and operatively coupled to one or more of the computer processors, the computer memory including a set associative cache, the cache comprising cache ways organized in sets, the cache being shared among the hardware threads of execution, each page of computer memory restricted for caching by one replacement vector of a class of replacement vectors to particular ways of the cache, each page of memory further restricted for caching by one or more bits of a replacement vector classification to particular sets of ways of the cache.
    Type: Grant
    Filed: April 12, 2012
    Date of Patent: October 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Russell D. Hoover, Eric O. Mejdrich
  • Patent number: 8560768
    Abstract: A method for reducing memory entries in a ternary content-addressable memory may include determining if a first entry and a second entry are associated with the same data value. The method may also include determining if the first entry can be masked such that searching the memory with the content value of either of the first entry or the second entry returns the same data value. The method may further include, in response to determining that the first entry and a second entry are associated with the same data value and determining that the first entry can be masked such that addressing the memory with the content value of either of the first entry or the second entry returns the same data value: (i) masking the first entry such that addressing the memory with the content value of either of the first entry or the second entry returns the same data value; and (ii) deleting the second entry.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: October 15, 2013
    Assignee: Fujitsu Limited
    Inventors: Arun Saha, Bijendra Singh
  • Publication number: 20130262768
    Abstract: A method for operating a cache that includes both robust cells and standard cells may include receiving a data to be written to the cache, determining whether a type of the data is unmodified data or modified data, and writing the data to robust cells or standard cells as a function of the type of the data. A processor includes a core that includes a cache including both robust cells and standard cells for receiving data, wherein the data is written to robust cells or standard cells as a function of whether a type of the data is determined to be unmodified data or modified data.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Christopher B. WILKERSON, Alaa R. ALAMELDEEN, Jaydeep P. KULKARNI
  • Publication number: 20130262772
    Abstract: A data processing system comprises data processing circuitry, a cache memory, and memory access circuitry. The memory access circuitry is operative to assign a memory address region to be allocated in the cache memory with a predefined initialization value. Subsequently, a portion of the cache memory is allocated to the assigned memory address region only after the data processing circuitry first attempts to perform a memory access on a memory address within the assigned memory address region. The allocated portion of the cache memory is then initialized with the predefined initialization value.
    Type: Application
    Filed: April 2, 2012
    Publication date: October 3, 2013
    Applicant: LSI CORPORATION
    Inventors: Alexander Rabinovitch, Leonid Dubrovin
  • Publication number: 20130246709
    Abstract: Embodiments related to fetching instructions and alternate versions achieving the same functionality as the instructions from an instruction cache included in a microprocessor are provided. In one example, a method is provided, comprising, at an example microprocessor, fetching an instruction from an instruction cache. The example method also includes hashing an address for the instruction to determine whether an alternate version of the instruction which achieves the same functionality as the instruction exists. The example method further includes, if hashing results in a determination that such an alternate version exists, aborting fetching of the instruction and retrieving and executing the alternate version.
    Type: Application
    Filed: March 13, 2012
    Publication date: September 19, 2013
    Applicant: NVIDIA CORPORATION
    Inventors: Ross Segelken, Alex Klaiber, Nathan Tuck, David Dunn
  • Publication number: 20130227209
    Abstract: Apparatus and method for placing data based on the content of the data in random access memory such that indexing operations are not required. A strong (e.g., cryptographic) hash is applied to a data element resulting in a signature. A weaker hash function is then applied to the signature to generate a storage location in memory for the data element. The weaker hash function assigns multiple data elements to the same storage location while the signature comprises a unique identifier for locating a particular data element at this location. In one embodiment a plurality of weak hash functions are applied successively to increase storage space utilization. In other embodiments, the assigned storage location can be determined by one or more attributes of the data element and/or the storage technology, e.g, long-lived versus short-lived data and/or different regions of the memory having different performance (e.g., access latency memory lifetime) characteristics.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: SimpliVity Corporation
    Inventors: John Michael CZERKOWICZ, Arthur J. Beaverson, Steven Bagby, Sowmya Manjanatha
  • Publication number: 20130185537
    Abstract: A hash table method and structure comprises a processor that receives a plurality of access requests for access to a storage device. The processor performs a plurality of hash processes on the access requests to generate a first number of addresses for each access request. Such addresses are within a full address range. Hash table banks are operatively connected to the processor. The hash table banks form the storage device. Each of the hash table banks has a plurality of input ports. Specifically, each of the hash table banks has less input ports than the first number of addresses for each access request. The processor provides the addresses to the hash table banks, and each of the hash table banks stores pointers corresponding to a different limited range of addresses within the full address range (each of the different limited range of addresses is less than the full address range).
    Type: Application
    Filed: January 18, 2012
    Publication date: July 18, 2013
    Applicant: International Business Machines Corporation
    Inventors: Bulent Abali, John J. Reilly
  • Publication number: 20130159629
    Abstract: A system and method are disclosed for storing data in a hash table. The method includes receiving data, determining a location identifier for the data wherein the location identifier identifies a location in the hash table for storing the data and the location identifier is derived from the data, compressing the data by extracting the location identifier; and storing the compressed data in the identified location of the hash table.
    Type: Application
    Filed: November 15, 2012
    Publication date: June 20, 2013
    Applicant: STEC, INC.
    Inventor: STEC, Inc.
  • Publication number: 20130151777
    Abstract: A mechanism is provided for dynamic cache allocation using a cache hit rate. A first cache hit rate is monitored in a first subset utilizing a first allocation policy of N sets of a lower level cache. A second cache hit rate is also monitored in a second subset utilizing a second allocation policy different from the first allocation policy of the N sets of the lower level cache. A periodic comparison of the first cache hit rate to the second cache hit rate is made to identify a third allocation policy for a third subset of the N-sets of the lower level cache. The third allocation policy for the third subset is then periodically adjusted to at least one of the first allocation policy or the second allocation policy based on the comparison of the first cache hit rate to the second cache hit rate.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Applicant: International Business Machines Corporation
    Inventors: David M. Daly, Benjiman L. Goodman, Stephen J. Powell, Aaron C. Sawdey, Jeffrey A. Stuecheli
  • Publication number: 20130151778
    Abstract: A mechanism is provided for dynamic cache allocation using bandwidth. A bandwidth between a higher level cache and a lower level cache is monitored. Responsive to bandwidth usage between the higher level cache and the lower level cache being below a predetermined low bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a first allocation policy. Responsive to bandwidth usage between the higher level cache and the lower level cache being above a predetermined high bandwidth threshold, the higher level cache and the lower level cache are set to operate in accordance with a second allocation policy.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Applicant: International Business Machines Corporation
    Inventors: David M. Daly, Benjiman L. Goodman, Stephen J. Powell, Aaron C. Sawdey, Jeffrey A. Stuecheli
  • Patent number: 8464024
    Abstract: Embodiments include methods, apparatus, and systems for virtual address hashing. One embodiment evenly distributes page-table entries throughout a hash table so applications do not generate a same hash index for mapping virtual addresses to physical addresses.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: June 11, 2013
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Thavatchai Makphaibulchoke, Linn Crosetto, Raghuram Kota
  • Publication number: 20130145097
    Abstract: An apparatus includes a cache memory that includes a state array configured to store state information. The state information includes a state that indicates updated corresponding to a particular address of the cache memory is not stored in the cache memory but is available from at least one of multiple sources external to the cache memory, where at least one of the multiple sources is a store buffer.
    Type: Application
    Filed: December 5, 2011
    Publication date: June 6, 2013
    Applicant: QUALCOMM INCORPORATED
    Inventors: Ajay Anant Ingle, Lucian Codrescu