Using Clearing, Invalidating, Or Resetting Means (epo) Patents (Class 711/E12.022)
  • Patent number: 9430026
    Abstract: Provided are an electronic control device and a microcomputer control method not only enabling smooth transmission and reception of signals by using a plurality of microcomputers but also capable of achieving, with a simpler configuration, reduction of power consumed by the microcomputers. As a mode for reducing power consumption, the electronic control device brings microcomputers from which a sleep request has been issued into a sleep state. The electronic control device is equipped with a low power consumption mode for bringing a communication bus driver into the sleep state after all microcomputers constituting the electronic control device have been transferred into the sleep state.
    Type: Grant
    Filed: November 9, 2011
    Date of Patent: August 30, 2016
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Naoki Matsushita
  • Patent number: 9021212
    Abstract: In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer.
    Type: Grant
    Filed: February 24, 2014
    Date of Patent: April 28, 2015
    Assignee: Hitachi, Ltd.
    Inventor: Nagamasa Mizushima
  • Patent number: 8990504
    Abstract: A cache page management method can include paging out a memory page to an input/output controller, paging the memory page from the input/output controller into a real memory, modifying the memory page in the real memory to an updated memory page and purging the memory page paged to the input/output controller.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Tara Astigarraga, Michael E. Browne, Joseph Demczar, Eric C. Wieder
  • Patent number: 8966184
    Abstract: An apparatus, system, and method are disclosed for managing eviction of data. A grooming cost module determines a grooming cost for a selected region of a nonvolatile solid-state cache. The grooming cost includes a cost of evicting the selected region of the nonvolatile solid-state cache relative to other regions. A grooming candidate set module adds the selected region to a grooming candidate set in response to the grooming cost satisfying a grooming cost threshold. A low cost module selects a low cost region within the grooming candidate set. A groomer module recovers storage capacity of the low cost region.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: February 24, 2015
    Assignee: Intelligent Intellectual Property Holdings 2, LLC.
    Inventor: David Atkisson
  • Patent number: 8949530
    Abstract: Systems and methods are disclosed for improving the performance of cache memory in a computer system by dynamically selecting an index for caching main memory while an application is running. A disclosed example of a memory system includes a cache including a data array, a primary tag array, and at least one secondary tag array. A currently selected index is used to index data bits to the data array and tag bits to the primary tag array. The performance of at least one candidate index is evaluated by indexing tag bits to the secondary tag array, without caching any data using the candidate index while the candidate index is under evaluation. If the candidate index has a better hit rate than the currently selected index, the memory system switches to using the candidate index to cache data.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Mvv A. Krishna, Shaul Yifrach
  • Patent number: 8930615
    Abstract: A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Junji Yano, Kosuke Hatsuda, Hidenori Matsuzaki
  • Patent number: 8909863
    Abstract: A request for application information can be received from an application running in a process. The application information can be requested from an information repository, and received back from the repository in a first format. The application information can be converted to a second format, and passed to the application in the second format. In addition, the application information can be saved in the second format in a cache in the process. Also, when application information has been cached in response to a request for the information for a first user object, and a subsequent request for the application information for a second user object is received, it can be determined whether the second user object is authorized to access the application information. If so, then the application information can be fetched from the cache and returned for use by the second user object.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: December 9, 2014
    Assignee: Microsoft Corporation
    Inventors: Matthew A. Neerincx, Zlatko V. Michailov, Chadwin J. Mumford
  • Patent number: 8886886
    Abstract: Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: November 11, 2014
    Assignee: Apple Inc.
    Inventors: Sukalpa Biswas, Shinye Shiu, James Wang, Robert Hu
  • Patent number: 8856448
    Abstract: Efficient techniques are described for tracking a potential invalidation of a data cache entry in a data cache for which coherency is required. Coherency information is received that indicates a potential invalidation of a data cache entry. The coherency information in association with the data cache entry is retained to track the potential invalidation to the data cache entry. The retained coherency information is kept separate from state bits that are utilized in cache access operations. An invalidate bit, associated with a data cache entry, may be utilized to represents a potential invalidation of the data cache entry. The invalidate bit is set in response to the coherency information, to track the potential invalidation of the data cache entry. A valid bit associated with the data cache entry is set in response to the active invalidate bit and a memory synchronization command. The set invalidate bit is cleared after the valid bit has been cleared.
    Type: Grant
    Filed: February 19, 2009
    Date of Patent: October 7, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Michael W. Morrow, James Norris Dieffenderfer
  • Patent number: 8788537
    Abstract: A computer readable medium stores a program causing a computer to execute a process including receiving an instruction for deleting an information group from a first memory; extracting, from the first memory, information regarding information groups having a parent-child relationship with a target information group to be deleted in accordance with the received instruction; extracting a user identification code associated with the target information group from a second memory; storing an identification code of the target information group, the information regarding the information groups, and the extracted user identification code in association with one another in a third memory; deleting the target information group from the first memory; and changing the structure information stored in the first memory to structure information obtained after the target information group has been deleted from the first memory, by changing the child information group as a child of the parent information group.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: July 22, 2014
    Assignee: Fuji Xerox Co., Ltd.
    Inventor: Haruki Matsui
  • Patent number: 8782338
    Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.
    Type: Grant
    Filed: October 1, 2013
    Date of Patent: July 15, 2014
    Assignee: STMicroelectronics (Rousset) SAS
    Inventor: Hubert Rousseau
  • Patent number: 8769212
    Abstract: A method and apparatus for providing a memory model for hardware attributes to support transactional execution is herein described. Upon encountering a load of a hardware attribute, such as a test monitor operation to load a read monitor, write monitor, or buffering attribute, a fault is issued in response to a loss field indicating the hardware attribute has been lost. Furthermore, dependency actions, such as blocking and forwarding, are provided for the attribute access operations based on address dependency and access type dependency. As a result, different scenarios for attribute loss and testing thereof are allowed and restricted in a memory model.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Gad Sheaffer, Shlomo Raikin, Vadim Bassin, Ehud Cohen, Oleg Margulis
  • Patent number: 8745334
    Abstract: An improved sectored cache replacement algorithm is implemented via a method and computer program product. The method and computer program product select a cache sector among a plurality of cache sectors for replacement in a computer system. The method may comprise selecting a cache sector to be replaced that is not the most recently used and that has the least amount of modified data. In the case in which there is a tie among cache sectors, the sector to be replaced may be the sector among such cache sectors with the least amount of valid data. In the case in which there is still a tie among cache sectors, the sector to be replaced may be randomly selected among such cache sectors. Unlike conventional sectored cache replacement algorithms, the improved algorithm implemented by the method and computer program product accounts for both hit rate and bus utilization.
    Type: Grant
    Filed: June 17, 2009
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventor: Daniel J. Colglazier
  • Patent number: 8745333
    Abstract: Systems and methods for backing up storage volumes are provided. One system includes a primary side, a secondary side, and a network coupling the primary and secondary sides. The secondary side includes first and second VTS including a cache and storage tape. The first VTS is configured to store a first portion of a group of storage volumes in its cache and migrate the remaining portion to its storage tape. The second VTS is configured to store the remaining portion of the storage volumes in its cache and migrate the first portion to its storage tape. One method includes receiving multiple storage volumes from a primary side, storing the storage volumes in the cache of the first and second VTS, migrating a portion of the storage volumes from the cache to storage tape in the first VTS, and migrating a remaining portion of the storage volumes from the cache to storage tape in the second VTS.
    Type: Grant
    Filed: June 18, 2013
    Date of Patent: June 3, 2014
    Assignee: International Business Machines Corporation
    Inventors: Norie Iwasaki, Katsuyoshi Katori, Hiroyuki Miyoshi, Takeshi Nohta, Eiji Tosaka
  • Publication number: 20140129778
    Abstract: An apparatus for use in telecommunications system comprises a cache memory shared by multiple clients and a controller for controlling the shared cache memory. A method of controlling the cache operation in a shared cache memory apparatus is also disclosed. The apparatus comprises a cache memory accessible by a plurality of clients and a controller configured to allocate cache lines of the cache memory to each client according to a line configuration. The line configuration comprises, for each client, a maximum allocation of cache lines that each client is permitted to access. The controller is configured to, in response to a memory request from one of the plurality of clients that has reached its maximum allocation of cache lines, allocate a replacement cache line to the client from cache lines already allocated to the client when no free cache lines in the cache are available.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: RESEARCH IN MOTION LIMITED
    Inventor: Simon John DUGGINS
  • Publication number: 20140129776
    Abstract: A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.
    Type: Application
    Filed: November 2, 2012
    Publication date: May 8, 2014
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: David A. Kaplan, Jeff Rupley, Tarun Nakra
  • Patent number: 8719493
    Abstract: An information handling system (IHS) includes a memory controller, a memory device, and firmware. A failing memory region and a spare memory region are included on the memory device. A memory buffer in the memory device is coupled to the failing memory region and the spare memory region. The memory buffer is operable to perform copy operations without instruction from the memory controller in order to copy data from the failing memory region to the spare memory region in response to firmware operations performed by the firmware. Firmware operations may include instructing the memory controller to produce additional refresh or calibration operation time periods, or providing an instruction to perform a data transfer operation to the spare memory region. The memory buffer is also operable to route requests from the memory controller to one of the failing memory region and the spare memory region during the copy operations.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: May 6, 2014
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, William Sauber
  • Patent number: 8713259
    Abstract: A method and apparatus for controlling re-acquiring lines of memory in a cache is provided. The method comprises storing at least one atomic instruction in a queue in response to the atomic instruction being retired, and identifying a target memory location associated with load and store portions of the atomic instruction. A line of memory associated with the target memory location is acquired and stored in a cache. Subsequently, if the line of acquired memory is evicted, then it is re-acquired in response to the atomic instruction becoming the oldest instruction stored in the queue. The apparatus comprises a queue and a cache. The queue is adapted for storing at least one atomic instruction in response to the atomic instruction being retired. A target memory location is associated with load and store portions of the atomic instruction.
    Type: Grant
    Filed: November 17, 2010
    Date of Patent: April 29, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventor: Christoper D. Bryant
  • Publication number: 20140115245
    Abstract: Aspects of the present disclosure disclose systems and methods for managing a level-two persistent cache. In various aspects, a solid-state drive is employed as a level-two cache to expand the capacity of existing caches. Any data stored in the level-two cache may be stored in a particular version or format of data known as “raw” data, in contrast to storing the data in a “cooked” version, as is typically stored in a level-one cache.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: Oracle International Corporation
    Inventors: Mark Maybee, Mark J. Musante, Victor Latushkin
  • Publication number: 20140115258
    Abstract: Implementations described and claimed herein provide systems and methods for allocating and managing resources for a deduplication table. In one implementation, an upper limit to an amount of memory allocated to a deduplication table is established. The deduplication table has one or more checksum entries, and each checksum entry is associates a checksum with unique data. A new checksum entry corresponding to new unique data is prevented from being added to the deduplication table where adding the new checksum entry will cause the deduplication table to exceed a size limit. The new unique data has a checksum that is different from the checksums in the one or more checksum entries in the deduplication table.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Lisa Week, Mark Maybee
  • Publication number: 20140115246
    Abstract: Aspects of the present disclosure disclose systems and methods for recognizing multiple and distinct references within a cache that identify or otherwise provide access to empty blocks of data. Multiple references identifying empty blocks of data are associated with a single block of empty data permanently stored in the cache. Subsequently, each time an empty block of data is added to the cache, a reference corresponding to the empty block is mapped to a generic empty block of data stored in the cache. When a reference is removed or deleted from the cache, only the reference is deleted; the single generic block of empty data continues to reside in the cache.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 24, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventor: Mark Maybee
  • Publication number: 20140115244
    Abstract: Aspects of the present disclosure disclose systems and methods for providing a level-two persistent cache. In various aspects, a solid-state drive is employed as a level-two cache to expand the capacity of existing caches. In particular, any data that is scheduled to be evicted or otherwise removed from a level-one cache is stored in the level-two cache with corresponding metadata in a manner that is quickly retrievable.
    Type: Application
    Filed: October 18, 2012
    Publication date: April 24, 2014
    Applicant: ORACLE INTERNATIONAL CORPORATION
    Inventors: Mark Maybee, Mark J. Musante, Victor Latushkin
  • Publication number: 20140108737
    Abstract: A method to eliminate the delay of a block invalidate operation in a multi CPU environment by overlapping the block invalidate operation with normal CPU accesses, thus making the delay transparent. A range check is performed on each CPU access while a block invalidate operation is in progress, and an access that maps to within the address range of the block invalidate operation will be trated as a cache miss to ensure that the requesting CPU will receive valid data.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Naveen Bhoria, Raguram Damodaran, Abhijeet Ashok Chachad
  • Publication number: 20140108732
    Abstract: Embodiments of the invention relate to optimizing the storage of data in a multi-cache level environment. In one aspect, data is classified into primary and secondary cache sections. Data is differentiated based on an inherent sharing characteristic of the data within a system comprising virtual machines. The data is then placed into the classified sections of the cache storage layer and/or persistent data, reflective of how the data is shared among virtual disk images access by virtual machines.
    Type: Application
    Filed: October 15, 2012
    Publication date: April 17, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: International Business Machines Corporation
  • Publication number: 20140108730
    Abstract: Systems and methods for non-blocking implementation of cache flush instructions are disclosed. As a part of a method, data is accessed that is received in a write-back data holding buffer from a cache flushing operation, the data is flagged with a processor identifier and a serialization flag, and responsive to the flagging, the cache is notified that the cache flush is completed. Subsequent to the notifying, access is provided to data then present in the write-back data holding buffer to determine if data then present in the write-back data holding buffer is flagged.
    Type: Application
    Filed: October 11, 2012
    Publication date: April 17, 2014
    Applicant: SOFT MACHINES, INC.
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Publication number: 20140101387
    Abstract: A cache management system employs a replacement policy in a manner that manages concurrent accesses to cache. The cache management system comprises a cache, a replacement policy storage for storing replacement statuses of cache lines of the cache, and an update module. The update module, comprising access filtering and a concurrent update handling, determines how updates to the replacement policy storage are handled. In a multi-threaded compute environment, a concurrent access to shared cache causes a selective update to the replacement policy storage.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Brian C. Grayson, Jyotsna S. Kartha, Kathryn C. Stacer
  • Publication number: 20140095794
    Abstract: A processor is described having cache circuitry and logic circuitry. The logic circuitry is to manage the entry and removal of cache lines from the cache circuitry. The logic circuitry includes storage circuitry and control circuitry. The storage circuitry is to store information identifying a set of cache lines within the cache that are in a modified state. The control circuitry is coupled to the storage circuitry to receive the information from the storage circuitry, responsive to a signal to flush the cache, and determine addresses of the cache therefrom so that the set of cache lines are read from the cache so as to avoid reading cache lines from the cache that are in an invalid or a clean state.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: Jaideep MOSES, Ravishankar IYER, Ramesh G. ILLIKKAL, Sadagopan SRINIVASAN
  • Publication number: 20140095800
    Abstract: Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Applicant: APPLE INC.
    Inventors: Sukalpa Biswas, Shinye Shiu, James Wang, Robert Hu
  • Patent number: 8683141
    Abstract: In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data s (latest data and past data) can be read for one designated logical address from a host computer.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: March 25, 2014
    Assignee: Hitachi, Ltd.
    Inventor: Nagamasa Mizushima
  • Publication number: 20140082293
    Abstract: Provided are techniques for handling a store buffer in conjunction with a processor, the store buffer comprising a free list; a merge window; and an evict list; and logic, for, upon receipt of a T_STORE operation, comparing a first address associated with the T_STORE operation with a plurality of addresses associated with previous T_STORE operations, wherein the previous T_STORE operations are part of the same transaction as the T_STORE operation and the entries corresponding to the previous T_STORE operations are stored in the merge window; in response to a match between the first address and a second address, associated with a second T_STORE operation, of the plurality of addresses, merging a first entry corresponding to the first T_STORE operation with a second entry corresponding to the second T_STORE operation; and consolidating results associated with the first T_STORE operation with results associated with the second T_STORE operation.
    Type: Application
    Filed: September 16, 2012
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. ALexander, Christian Jacobi, Gerrit Koch, Martin Recktenwald, Timothy J. Slegel, Hans-Werner Tast
  • Publication number: 20140082313
    Abstract: Embodiments relate to methods, systems and computer program products for evacuating a portion of a storage class memory. Upon receiving a request to evacuate the portion of the storage class memory a determination is made if the requested evacuation will result in a storage shortage. Based upon determining that the requested evacuation will not result in a storage shortage, the portion of the storage class memory is initialized for evacuation. After initialization is complete, evacuation of the plurality of address spaces of the portion of the storage class memory is preformed, wherein one or more of the plurality of address spaces are evacuated in parallel.
    Type: Application
    Filed: September 14, 2012
    Publication date: March 20, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Robert Miller, JR., Harris M. Morgenstern, Walter W. Otto, Steven M. Partlow, Thomas F. Rankin, Elpida Tzortzatos
  • Publication number: 20140075125
    Abstract: Methods and apparatuses for utilizing a cache hint mechanism in which a requesting agent can provide hints as to how data corresponding to a request should be cached in a system cache within a memory controller. The way the system cache responds to received requests is determined by the cache hint provided by the originating requesting agent. When a request is accompanied by a de-allocate cache hint, the system cache causes a cache line hit by the request to be de-allocated. For a request with a do not allocate cache hint, the system cache does not allocate a cache line if the request misses in the system cache, and the system cache maintains a given cache line in its current state if the requests hits the given cache line.
    Type: Application
    Filed: September 11, 2012
    Publication date: March 13, 2014
    Inventors: Sukalpa Biswas, Shinye Shiu, James Wang
  • Publication number: 20140075121
    Abstract: Techniques for conflict detection in hardware transactional memory (HTM) are provided. In one aspect, a method for detecting conflicts in HTM includes the following steps. Conflict detection is performed eagerly by setting read and write bits in a cache as transactions having read and write requests are made. A given one of the transactions is stalled when a conflict is detected whereby more than one of the transactions are accessing data in the cache in a conflicting way. An address of the conflicting data is placed in a predictor. The predictor is queried whenever the write requests are made to determine whether they correspond to entries in the predictor. A copy of the data corresponding to entries in the predictor is placed in a store buffer. The write bits in the cache are set and the copy of the data in the store buffer is merged in at transaction commit.
    Type: Application
    Filed: October 5, 2012
    Publication date: March 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Colin B. Blundell, Harold W. Cain, III, Jose E. Moreira
  • Publication number: 20140075124
    Abstract: Techniques for conflict detection in hardware transactional memory (HTM) are provided. In one aspect, a method for detecting conflicts in HTM includes the following steps. Conflict detection is performed eagerly by setting read and write bits in a cache as transactions having read and write requests are made. A given one of the transactions is stalled when a conflict is detected whereby more than one of the transactions are accessing data in the cache in a conflicting way. An address of the conflicting data is placed in a predictor. The predictor is queried whenever the write requests are made to determine whether they correspond to entries in the predictor. A copy of the data corresponding to entries in the predictor is placed in a store buffer. The write bits in the cache are set and the copy of the data in the store buffer is merged in at transaction commit.
    Type: Application
    Filed: September 7, 2012
    Publication date: March 13, 2014
    Applicant: International Business Machines Corporation
    Inventors: Colin B. Blundell, Harold Wade Cain, III, Jose Eduardo Moreira
  • Publication number: 20140068196
    Abstract: Web objects, such as media files are sent through an adaptation server which includes a transcoder for adapting forwarded objects according to profiles of the receiving destinations, and a cache memory for caching frequently requested objects, including their adapted versions. The probability of additional requests for the same object before the object expires, is assessed by tracking hits. Only objects having experienced hits in excess of a hit threshold are cached, the hit threshold being adaptively adjusted based on the capacity of the cache, and the space required to store cached media files. Expired objects are collected in a list, and may be periodically ejected from the cache, or when the cache is nearly full.
    Type: Application
    Filed: August 28, 2012
    Publication date: March 6, 2014
    Inventors: Louis BENOIT, Sébastien CÔTÉ, Robert BUCHNAJZER
  • Publication number: 20140059298
    Abstract: In one embodiment, a method performed by one or more computing devices includes receiving at a host cache, a first request to prepare a volume of the host cache for creating a snapshot of a cached logical unit number (LUN), the request indicating that a snapshot of the cached LUN will be taken, preparing, in response to the first request, the volume of the host cache for creating the snapshot of the cached LUN depending on a mode of the host cache, receiving, at the host cache, a second request to create the snapshot of the cached LUN, and in response to the second request, creating, at the host cache, the snapshot of the cached LUN.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: DELL PRODUCTS L.P.
    Inventors: Marc David Olin, Michael James Klemm
  • Publication number: 20140059297
    Abstract: Methods and apparatuses for implementing a system cache within a memory controller. Multiple requesting agents may allocate cache lines in the system cache, and each line allocated in the system cache may be associated with a specific group ID. Also, each line may have a corresponding sticky state which indicates if the line should be retained in the cache. The sticky state is determined by an allocation hint provided by the requesting agent. When a cache line is allocated with the sticky state, the line will not be replaced by other cache lines fetched by any other group IDs.
    Type: Application
    Filed: August 27, 2012
    Publication date: February 27, 2014
    Inventors: Sukalpa Biswas, Shinye Shiu, James Wang
  • Publication number: 20140040560
    Abstract: An input/output memory management unit (IOMMU) having an “invalidate all” command available to clear the contents of cache memory is presented. The cache memory provides fast access to address translation data that has been previously obtained by a process. A typical cache memory includes device tables, page tables and interrupt remapping entries. Cache memory data can become stale or be compromised from security breaches or malfunctioning devices. In these circumstances, a rapid approach to clearing cache memory content is provided.
    Type: Application
    Filed: July 31, 2012
    Publication date: February 6, 2014
    Inventors: Andrew G. Kegel, Mark D. Hummel, Anthony Asaro
  • Publication number: 20140032850
    Abstract: Embodiments present a virtual disk image to applications such as virtual machines (VMs) executing on a computing device. The virtual disk image corresponds to one or more subparts of binary large objects (blobs) of data stored by a cloud service, and is implemented in a log structured format. Grains of the virtual disk image are cached by the computing device. The computing device caches only a subset of the grains and performs write operations without blocking the applications to reduce storage latency perceived by the applications. Some embodiments enable the applications that lack enterprise class storage to benefit from enterprise class cloud storage services.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 30, 2014
    Applicant: VMWARE, INC.
    Inventors: Thomas A. Phelan, Erik Cota-Robles, David William Barry, Adam Back
  • Publication number: 20140032851
    Abstract: In general, the disclosure is directed to techniques for choosing which pages to evict from the buffer pool to make room for caching additional pages in the context of a database table scan. A buffer pool is maintained in memory. A fraction of pages of a table to persist in the buffer pool are determined. A random number is generated as a decimal value of 0 to 1 for each page of the table cached in the buffer pool. If the random number generated for a page is less than the fraction, the page is persisted in the buffer pool. If the random number generated for a page is greater than the fraction, the page is included as a candidate for eviction from the buffer pool.
    Type: Application
    Filed: July 27, 2012
    Publication date: January 30, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Sam S. Lightstone, Adam J. Storm
  • Publication number: 20140032844
    Abstract: Systems and methods for flushing a cache with modified data are disclosed. Responsive to a request to flush data from a cache with modified data to a next level cache that does not include the cache with modified data, the cache with modified data is accessed using an index and a way and an address associated with the index and the way is secured. Using the address, the cache with modified data is accessed a second time and an entry that is associated with the address is retrieved from the cache with modified data. The entry is placed into a location of the next level cache.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Applicant: SOFT MACHINES, INC.
    Inventors: Karthikeyan Avudaiyappan, Mohammad Abdallah
  • Publication number: 20140025898
    Abstract: An information processing system and computer program storage product for managing objects stored in a shared memory cache. The system includes at least a plurality of cache readers accessing data from the shared memory cache. The system updates data in the shared memory cache using a cache writer. The system maintains a cache replacement process collocated with a cache writer. The cache replacement process makes a plurality of decisions on objects to store in the shared memory cache. Each of the plurality of cache readers maintains information on frequencies with which it accesses cached objects. Each of the plurality of cache readers communicates the maintained information to the cache replacement process. The cache replacement process uses the communicated information on frequencies to make at least one decision on replacing at least one object currently stored in the shared memory cache.
    Type: Application
    Filed: September 14, 2012
    Publication date: January 23, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Arun IYENGAR
  • Publication number: 20140019688
    Abstract: Disclosed herein are systems, methods, and computer readable storage media for a database system using solid state drives as a second level cache. A database system includes random access memory configured to operate as a first level cache, solid state disk drives configured to operate as a persistent second level cache, and hard disk drives configured to operate as disk storage. The database system also includes a cache manager configured to receive a request for a data page and determine whether the data page is in cache or disk storage. If the data page is on disk, or in the second level cache, it is copied to the first level cache. If copying the data page results in an eviction, the evicted data page is copied to the second level cache. At checkpoint, dirty pages stored in the second level cache are flushed in place in the second level cache.
    Type: Application
    Filed: July 13, 2012
    Publication date: January 16, 2014
    Applicant: iAnywhere Solutions
    Inventors: Pedram GHODSNIA, Reza SHERKAT, John C. SMIRNIOS, Peter BUMBULIS, Anil K. GOEL
  • Publication number: 20140006717
    Abstract: An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed with signatures that are associated with the plurality of cache lines. The apparatus may fill cache lines into the cache file with either low or high priority. Low priority lines may be chosen to be replaced by a replacement algorithm before high priority lines. In this way, the cache naturally may contain more high priority lines than low priority ones. This priority filling process may improve the performance of most replacement schemes including the best known schemes which are already doing better than LRU.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: INTEL CORPORATION
    Inventors: Simon C. STEELY, JR., William C. HASENPLAUGH, Aamer JALEEL, Joel S. EMER, Carole-Jean WU
  • Publication number: 20140006713
    Abstract: The present invention may provide a computer system including a plurality of tiles divided into multiple virtual domains. Each tile may include a router to communicate with others of said tiles, a private cache to store data, and a spill table to record pointers for data evicted from the private cache to a remote host, wherein the remote host and the respective tile are provided in the same virtual domain. The spill tables may allow for faster retrieval of previously evicted data because the home registry does not need to be referenced if requested data is listed in the spill table. Therefore, embodiments of the present invention may provide a distance-aware cache collaboration architecture without incurring extraneous overhead expenses.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Ahmad Ahmad SAMIH, Ren Wang, Christian Maciocco, Tsung-Yuan C. Tai
  • Publication number: 20140006698
    Abstract: In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Robert S. Chappell, Ravi Rajwar, Zhongying Zhang, Jason A. Bessette
  • Publication number: 20130346670
    Abstract: A method for controlling data write operation of a mass storage device is provided. The mass storage device has a controller and a memory unit. The method includes connecting the mass storage device to a host device, and receiving a voltage provided from the host device; sensing and monitoring whether the voltage is lower than a first predefined voltage; writing data to the mass storage device with a first frequency when the sensed voltage is higher than the first predefined voltage; and writing data to the mass storage device with a second frequency when the sensed voltage is lower than the first predefined voltage, wherein the second frequency is adjusted by decreasing the first frequency.
    Type: Application
    Filed: June 21, 2012
    Publication date: December 26, 2013
    Inventor: Chun-Chieh Wang
  • Patent number: 8615633
    Abstract: Technologies are generally for maintaining cache coherency within a multi-core processor. A first cache entry to be evicted from a first cache may be identified. The first cache entry may include a block of data and a first tag indicating an owned state. An owner eviction message for the first cache entry may be broadcasted from the first cache. A second cache entry in a second cache may be identified. The second cache entry may include the block of data and a second tag indicating a shared state. The broadcasted owner eviction message may be detected with the second cache. An ownership acceptance message for the second cache entry may be broadcasted from the second cache. The broadcasted ownership acceptance message may be detected with the first cache. The second tag in the second cache entry may be transformed from the shared state to the owned state.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: December 24, 2013
    Assignee: Empire Technology Development LLC
    Inventor: Yan Solihin
  • Publication number: 20130339569
    Abstract: Storage system(s) for providing storing data in physical storage in a recurring manner, method(s) of operating thereof, and corresponding computer program product(s). For example, a possible method can include for each recurrence: generating a snapshot of at least one logical volume; destaging all data corresponding to the snapshot which was accommodated in the cache memory prior to a time of generating the snapshot and which was dirty at the time of generating said snapshot, thus giving rise to destaged data group; and after the destaged data group has been successfully destaged, registering an indication that the snapshot is associated with an order preservation consistency condition for the at least one logical volume, thus giving rise to a consistency snapshot.
    Type: Application
    Filed: June 14, 2012
    Publication date: December 19, 2013
    Applicant: Infinidat Ltd.
    Inventors: Yechiel YOCHAI, Michael DORFMAN, Efri ZEIDNER
  • Publication number: 20130339618
    Abstract: Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set.
    Type: Application
    Filed: June 15, 2012
    Publication date: December 19, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Khary J. Alexander, Jonathan T. Hsieh, Christian Jacobi