Abstract: Embodiments relate to a transactional read footprint after a cache line eviction. An aspect includes executing one or more read instructions in an active transaction. A cross invalidate (XI) request for a target cache line is received, and it is determined if the target cache line is part of a congruence class in a local cache. It is further determined whether an extension flag associated with the congruence class is set. The extension flag is used to indicate that cache lines of the congruence class associated with the active transaction have been replaced based only on being least recently used and that the target cache line is not in the cache. Execution of the active transaction continues based on determining that the extension flag is not set. Execution of the active transaction is aborted based on determining that the extension flag is set.

Abstract: According to one embodiment, upon request from an information processor, a semiconductor storage controller writes pieces of data in predetermined units into storage locations in which no data has been written in erased areas within a semiconductor chip's storage area. A third table and a second table which is a subset thereof include physical addresses each indicating a storage location of each of pieces of the data within the semiconductor chip. The first table includes either information specifying a second table entry or information specifying a third table entry. The semiconductor storage controller records the first and the second tables into a volatile memory or records the first table into a volatile memory and the third table into a nonvolatile memory.

Abstract: A computational device maintains a first type of cache and a second type of cache. The computational device receives a command from the host to release space. The computational device synchronously discards tracks from the first type of cache, and asynchronously discards tracks from the second type of cache.

Abstract: A controller receives a request to perform staging or destaging operations with respect to an area of a cache. A determination is made as to whether one or more discard scans are being performed or queued for the area of the cache. In response to determining that one or more discard scans are being performed or queued for the area of the cache, the controller avoids satisfying the request to perform the staging or the destaging operations with respect to the area of the cache.

Abstract: A cache is maintained with write order numbers that indicate orders of writes into the cache, so that periodic partial flushes of the cache can be executed while maintaining write order consistency. A method of storing data into the cache includes receiving a request to write data into the cache, identifying lines in the cache for storing the data, writing the data into the lines of the cache, storing a write order number, and associating the write order number with the lines of the cache. A method of flushing a cache having cache lines associated with write order numbers includes the steps of identifying lines in the cache that are associated with either a selected write order number or a write order number that is less than the selected write order number, and flushing data stored in the identified lines to a persistent storage.

Abstract: A method for caching data in a storage medium implementing tiered data structures may include storing a first portion of critical data at the instruction of a storage control module. The first portion of critical data may be separated into data having different priority levels based upon at least one data utilization characteristic associated with a file system implemented by the storage control module. The method may also include storing a second portion of data at the instruction of the storage control module. The second storage medium may have at least one performance, reliability, or security characteristic different from the first storage medium.

Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) providing a cache having a plurality of cache entries, each entry adapted to store data, wherein the cache is adapted to be accessed by hardware and software in a first operational mode; (2) determining an absence of desired data in one of the plurality of cache entries; (3) determining a status based on a current operational mode and a value of hint-lock bits associated with the plurality of cache entries; and (4) determining availability of at least one of the cache entries based on the status, wherein availability of a cache entry indicates that data stored in the cache entry can be replaced. Numerous other aspects are provided.

Abstract: For a cache in which a plurality of frequently accessed data segments are temporarily stored, reference count information of the plurality of data segments, in conjunction with least recently used (LRU) information, is used to determine a length of time to retain the plurality of data segments in the cache according to a predetermined weight, where notwithstanding the LRU information, those of the plurality of data segments having a higher reference counts are retained longer than those having lower reference counts.

Abstract: A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.

Abstract: Methods, and apparatus to cause performance of such methods, for managing memory. The methods include requesting a particular unit of data from a first level of memory. If the particular unit of data is not available from the first level of memory, the methods further include determining whether a free unit of data exists in the first level of memory, evicting a unit of data from the first level of memory if a free unit of data does not exist in the first level of memory, and requesting the particular unit of data from a second level of memory. If the particular unit of data is not available from the second level of memory, the methods further include reading the particular unit of data from a third level of memory. The methods still further include writing the particular unit of data to the first level of memory.

Abstract: A storage device includes storage media and a controller to control access of the storage media. The controller receives an erase command used to specify an erase operation of at least one portion of the storage media. The erase command has a control field controllable by a requestor device that submitted the erase command to the storage device, where the control field has one or more portions settable to cause the storage device to perform one or more of: reporting a progress of the erase operation, and modifying an operational state of the erase operation.

Abstract: In one embodiment, a micro-processing system includes a hardware structure disposed on a processor core. The hardware structure includes a plurality of entries, each of which are associated with portion of code and a translation of that code which can be executed to achieve substantially equivalent functionality. The hardware structure includes a redirection array that enables, when referenced, execution to be redirected from a portion of code to its counterpart translation. The entries enabling such redirection are maintained within or evicted from the hardware structure based on usage information for the entries.

Abstract: Embodiments of the present invention provides for the execution of threads and/or workitems on multiple processors of a heterogeneous computing system in a manner that they can share data correctly and efficiently. Disclosed method, system, and article of manufacture embodiments include, responsive to an instruction from a sequence of instructions of a work-item, determining an ordering of visibility to other work-items of one or more other data items in relation to a particular data item, and performing at least one cache operation upon at least one of the particular data item or the other data items present in any one or more cache memories in accordance with the determined ordering. The semantics of the instruction includes a memory operation upon the particular data item.

Abstract: In response to executing a deallocate instruction, a deallocation request specifying a target address of a target cache line is sent from a processor core to a lower level cache. In response, a determination is made if the target address hits in the lower level cache. If so, the target cache line is retained in a data array of the lower level cache, and a replacement order field of the lower level cache is updated such that the target cache line is more likely to be evicted in response to a subsequent cache miss in a congruence class including the target cache line. In response to the subsequent cache miss, the target cache line is cast out to the lower level cache with an indication that the target cache line was a target of a previous deallocation request of the processor core.

Abstract: Existing multiprocessor computing systems often have insufficient memory coherency and, consequently, are unable to efficiently utilize separate memory systems. Specifically, a CPU cannot effectively write to a block of memory and then have a GPU access that memory unless there is explicit synchronization. In addition, because the GPU is forced to statically split memory locations between itself and the CPU, existing multiprocessor computing systems are unable to efficiently utilize the separate memory systems. Embodiments described herein overcome these deficiencies by receiving a notification within the GPU that the CPU has finished processing data that is stored in coherent memory, and invalidating data in the CPU caches that the GPU has finished processing from the coherent memory. Embodiments described herein also include dynamically partitioning a GPU memory into coherent memory and local memory through use of a probe filter.

Abstract: Systems and methods for managing a storage device are disclosed. Generally, in a host to which a storage device is operatively coupled, wherein the storage device includes a cache for storing one or more discardable files, a file is identified to be uploaded to an external location. A determination is made whether sufficient free space exists in the cache to pre-stage the file for upload to the external location and the file is stored in the cache upon determining that sufficient free space exists in the cache to pre-stage the file for upload to the external location, wherein pre-stating prepares a file for opportunistically uploading such file in accordance with an uploading policy.

Abstract: Provided are a computer program product, system, and method for managing data in a first cache and a second cache. A reference count is maintained in the second cache for the page when the page is stored in the second cache. It is determined that the page is to be promoted from the second cache to the first cache. In response to determining that the reference count is greater than zero, the page is added to a Least Recently Used (LRU) end of an LRU list in the first cache. In response to determining that the reference count is less than or equal to zero, the page is added to a Most Recently Used (LRU) end of the LRU list in the first cache.

Abstract: The storage controller of the present invention is able to reduce the amount of purge message communication and increase the processing performance of the storage controller. Each microprocessor creates and saves a purge message every time control information in the shared memory is updated. After a series of update processes are complete, the saved purge messages are transmitted to each microprocessor. To the control information, attribute corresponding to its characteristics is established, and cache control and purge control are executed depending on the attribute.

Abstract: A performance monitor records performance information for tagged instructions being executed at an instruction pipeline. For instructions resulting in a load or store operation, a cache access analyzer can decompose the address associated with the operation to determine which cache line, if any, of a cache is accessed by the operation, and which portion of the cache line is requested by the operation. The cache access analyzer records the cache line portion in a data record, and, in response to a change in instruction being executed, stores the data record for subsequent analysis.

Abstract: Mechanisms for generating checkpoints in a speculative versioning cache of a data processing system are provided. The mechanisms execute code within the data processing system, wherein the code accesses cache lines in the speculative versioning cache. The mechanisms further determine whether a first condition occurs indicating a need to generate a checkpoint in the speculative versioning cache. The checkpoint is a speculative cache line which is made non-speculative in response to a second condition occurring that requires a roll-back of changes to a cache line corresponding to the speculative cache line. The mechanisms also generate the checkpoint in the speculative versioning cache in response to a determination that the first condition has occurred.

Abstract: Storage and host devices are provided for overlapping storage areas for a hibernation file and cached data. In one embodiment, a storage device is provided that receives a command from a host device to evict cached data in a first address range of the memory. The storage device then receives a command from the host device to store a hibernation file in a second address range of the memory, wherein the second address range does not exist in the memory. The storage device maps the second address range to the first address range and stores the hibernation file in the first address range. In another embodiment, a host device is provided that sends a command to a first storage device to evict cached data in a first address range of the first storage device's memory. The host device then sends a command to the first storage device to store a hibernation file in the first address range.

Abstract: Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks stored in the storage system to demote from the first cache. A first stride is formed including the determined tracks to demote. A determination is made of a second stride in the second cache in which to include the tracks in the first stride. The tracks from the first stride are added to the second stride in the second cache. A determination is made of tracks in strides in the second cache to demote from the second cache. The determined tracks to demote from the second cache are demoted.

Abstract: A data processing system includes a plurality of processing units coupled by an interconnect fabric. In response to a data request, a victim cache line is selected for castout from a first lower level cache of a first processing unit, and a target lower level cache of one of the plurality of processing units is selected based upon architectural proximity of the target lower level cache to a home system memory to which the address of the victim cache line is assigned. The first processing unit issues on the interconnect fabric a lateral castout (LCO) command that identifies the victim cache line to be castout from the first lower level cache and indicates that the target lower level cache is an intended destination. In response to a coherence response indicating success of the LCO command, the victim cache line is removed from the first lower level cache and held in the second lower level cache.

Abstract: Systems and methods for backing up storage volumes are provided. One system includes a primary side, a secondary side, and a network coupling the primary and secondary sides. The secondary side includes first and second VTS including a cache and storage tape. The first VTS is configured to store a first portion of a group of storage volumes in its cache and migrate the remaining portion to its storage tape. The second VTS is configured to store the remaining portion of the storage volumes in its cache and migrate the first portion to its storage tape. One method includes receiving multiple storage volumes from a primary side, storing the storage volumes in the cache of the first and second VTS, migrating a portion of the storage volumes from the cache to storage tape in the first VTS, and migrating a remaining portion of the storage volumes from the cache to storage tape in the second VTS.

Abstract: Embodiments of an apparatus to reduce memory power consumption are presented. In one embodiment, the apparatus comprises a cache memory, a memory, and a control unit. In one embodiment, the memory includes a plurality of memory ranks. The control unit is operable to select one or more memory ranks among the plurality of memory ranks to be idle-prioritized memory ranks such that access frequency to the idle-prioritized memory ranks is reduced.

Abstract: According to one embodiment, an apparatus includes a storage module, a cache module, and a changing module. The cache module is configured to use a first cache data storage region in a storage region of a first storage device as a cache of the storage module, and to manage cache management information includes position information indicating a position of the first cache data storage region. The changing module is configured to store cache data stored in the first cache data storage region in a second cache data storage region in a storage region of a second storage device when it is requested to use the second cache data storage region as the cache of the storage module, and to update the position information.

Abstract: Methods for selecting a line to evict from a data storage system are provided. A computer system implementing a method for selecting a line to evict from a data storage system is also provided. The methods include selecting an uncached class line for eviction prior to selecting a cached class line for eviction.

Abstract: Methods for selecting a line to evict from a data storage system are provided. A computer system implementing a method for selecting a line to evict from a data storage system is also provided. The methods include selecting an uncached class line for eviction prior to selecting a cached class line for eviction.

Abstract: An information processing device includes a first storage section 2 that includes a plurality of cells to store data; a second storage section 3 that holds refresh intervals and the states of implementation of refresh operations for each of a plurality of the cells; and a control section that controls the refresh operation of each of the cells on the basis of the refresh intervals and the states of implementation of refresh operations held by the second storage section 3. The information processing device controls the refresh operation of each of the cells at refresh intervals set for respective cells.

Abstract: A mechanism is provided for weighted history allocation prediction. For each member in a plurality of members in a lower level cache, an associated reference counter is initialized to an initial value based on an operation type that caused data to be allocated to a member location of the member. For each access to the member in the lower level cache, the associated reference counter is incremented. Responsive to a new allocation of data to the lower level cache and responsive to the new allocation of data requiring the victimization of another member in the lower level cache, a member of the lower level cache is identified that has a lowest reference count value in its associated reference counter. The member with the lowest reference count value in its associated reference counter is then evicted.

Abstract: The present disclosure generally relates to cache memory systems and/or techniques to identify dead cache blocks in cache memory systems. Example systems may include a cache memory that is accessible by a cache client. The cache memory may include a plurality of storage locations for a first cache block, with a most recently used position location in the cache memory. A cache controller may be configured to predict whether the first cache block stored in the cache memory is identified as a dead cache block based on a cache burst of the first cache block. The cache burst may comprise a first access of the first cache block by a cache client and any subsequent contiguous accesses of the first cache block following the first access by the cache client while the first cache block is in a most recently used position of the cache set.

Abstract: The apparatus and method described herein are for handling shared memory accesses between multiple processors utilizing lock-free synchronization through transactional-execution. A transaction demarcated in software is speculatively executed. During execution invalidating remote accesses/requests to addresses loaded from and to be written to shared memory are tracked by a transaction buffer. If an invalidating access is encountered, the transaction is re-executed. After a pre-determined number of times re-executing the transaction, the transaction may be re-executed non-speculatively with locks/semaphores.

Abstract: Systems and methods for cache optimization are provided. The method comprises monitoring cache access rate for a plurality of cache tenants sharing same cache mechanism having an amount of data storage space, wherein a first cache tenant having a first cache size is allocated a first cache space within the data storage space, and wherein a second cache tenant having a second cache size is allocated a second cache space within the data storage space. The method further comprises determining cache profiles for at least the first cache tenant and the second cache tenant according to data collected during the monitoring; analyzing the cache profiles for the plurality of cache tenants to determine an expected cache usage model for the cache mechanism; and analyzing the cache usage model and factors related to cache efficiency or performance for the one or more cache tenants to dictate one or more occupancy constraints.

Abstract: A system and method for reading files stored on a storage system is disclosed. The method includes communicatively coupling one or more remote systems for reading files stored in storage with a first set of files according to a predetermined data format and in a cache memory with a second set of files, the second set of files being a subset of the first set of files. Next one or more remote systems are received at least one read request for reading a sequence of files. A determination is made, among the files of the sequence of files, whether one or more cached files are already stored in the cache memory and whether one or more remaining files are not already stored in the cache memory. Creating, within the one or more remaining files, an order according to which the remaining files should be read on the storage system.

Abstract: According to one aspect of the present disclosure, a system and technique for variable cache line size management is disclosed. The system includes a processor and a cache hierarchy, where the cache hierarchy includes a sectored upper level cache and an unsectored lower level cache, and wherein the upper level cache includes a plurality of sub-sectors, each sub-sector having a cache line size corresponding to a cache line size of the lower level cache. The system also includes logic executable to, responsive to determining that a cache line from the upper level cache is to be evicted to the lower level cache: identify referenced sub-sectors of the cache line to be evicted; invalidate unreferenced sub-sectors of the cache line to be evicted; and store the referenced sub-sectors in the lower level cache.

Abstract: Shared cache modules, systems, and methods are provided herein. The shared cache module is useable with at least one initiator on a serial attached small computer system interface system. The shared cache module includes a memory device and a memory interface. The memory device assigns each of the at least one initiator to a portion of a cache memory on the memory device. The memory interface indexes the assignment and communicates with the at least one initiator to perform a memory task.

Abstract: The population of data to be inserted into secondary data storage cache is controlled by determining a heat metric of candidate data; adjusting a heat metric threshold; rejecting candidate data provided to the secondary data storage cache whose heat metric is less than the threshold; and admitting candidate data whose heat metric is equal to or greater than the heat metric threshold. The adjustment of the heat metric threshold is determined by comparing a reference metric related to hits of data most recently inserted into the secondary data storage cache, to a reference metric related to hits of data most recently evicted from the secondary data storage cache; if the most recently inserted reference metric is greater than the most recently evicted reference metric, decrementing the threshold; and if the most recently inserted reference metric is less than the most recently evicted reference metric, incrementing the threshold.

Abstract: The use of heap memory is optimized by extending a cache implementation with a CacheInterface base class. An instance of a ReferenceToCache is attached to the CacheInterface base class. The cache implementation is registered to a garbage collector application. The registration is stored as a reference list in a memory. In response to an unsatisfied cache allocation request, a garbage collection cycle is triggered to check heap occupancy. In response to exceeding a threshold value, the reference list is traversed for caches to be cleaned based upon a defined space constraint value. The caches are cleaned in accordance with the defined space constraint value.

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

Abstract: An apparatus comprising a controller and a memory. The controller may be configured to generate (i) an index signal and (ii) an information signal in response to (i) one or more address signals and (ii) a data signal. The memory may be configured to store said information signal in one of a plurality of cache lines. Each of the plurality of cache lines has an associated one of a plurality of cache headers. Each of the plurality of cache headers includes (i) a first bit configured to indicate whether the associated cache line has all valid entries and (ii) a second bit configured to indicate whether the associated cache line has at least one dirty entry.

Abstract: A controller includes an identification information management table that manages identification information indicating, for each of addresses in second-management unit, whether one or more data in first management unit belonging to the addresses is stored in the second or the third storing area. When the controller executes a process of flushing data from the first storing area to the second storing area or the third storing area, the controller updates the identification information in the identification information management table. The controller executes a process of reading data from the second storing area or the third storing area by referring to the identification information. As a result, the speed of searches conducted in the management table is increased.

Abstract: Aspects of various embodiments are directed to memory circuits, such as cache memory circuits. In accordance with one or more embodiments, cache-access to data blocks in memory is controlled as follows. In response to a cache miss for a data block having an associated address on a memory access path, data is fetched for storage in the cache (and serving the request), while one or more additional lookups are executed to identify candidate locations to store data. An existing set of data is moved from a target location in the cache to one of the candidate locations, and the address of the one of the candidate locations is associated with the existing set of data. Data in this candidate location may, for example, thus be evicted. The fetched data is stored in the target location and the address of the target location is associated with the fetched data.

Abstract: A processor (10) of processes data using a cache circuit (12). The processor (20) is coupled to a functionally detachable device (19) via the cache circuit (12). When a cache line is loaded into cache memory (120), it is tested whether the cache line has an address within a detachable device address range allocated to the detachable device (19). If so, identification of the cache line, or a range of addresses that includes the address of the cache line is stored. When a flush command is received that requires write back cached data to the detachable device, the identification is used to select the cache line for selective write back to the detachable device. Thus less cache data needs to be invalidated when a device is functionally detached from the circuit.

Abstract: In a semiconductor memory computer equipped with a flash memory, use of backed-up data is enabled. The semiconductor memory computer includes an address conversion table for detecting physical addresses of at least two pages storing data by designating a logical address from one of logical addresses to be designated by a reading request. The semiconductor memory computer includes a page status register for detecting one page status allocated to each page, and page statuses to be detected include the at least following four statuses: (1) a latest data storage status, (2) a not latest data storage status, (3) an invalid data storage status, and (4) an unwritten status. By using the address conversion table and the page status register, at least two data (latest data and past data) can be read for one designated logical address from a host computer.

Abstract: A system and method for managing a data cache in a central processing unit (CPU) of a database system. A method executed by a system includes the processing steps of adding an ID of a page p into a page holder queue of the data cache, executing a memory barrier store-load operation on the CPU, and looking-up page p in the data cache based on the ID of the page p in the page holder queue. The method further includes the steps of, if page p is found, accessing the page p from the data cache, and adding the ID of the page p into a least-recently-used queue.

Abstract: A TTL value for a data object stored in-memory in a data grid is dynamically adjusted. A stale data tolerance policy is set. Low toleration for staleness would mean that eviction is certain, no matter the cost, and high toleration would mean that the TTL value would be set based on total cost. Metrics to report a cost to re-create and re-store the data object are calculated, and the TTL value is adjusted based on calculated metrics. Further factors, such as, cleanup time to evict data from a storage site, may be considered in the total cost.

Abstract: Systems, methods, and other embodiments associated with optimizing the use of replaceable memory cards and onboard memory as storage for data in cache are described. According to one embodiment, an apparatus includes a cache space manager configured to cause a cache processor to store data of a removable memory card of a memory device to an onboard memory of the memory device. The apparatus also includes an error rate monitor configured to monitor operating parameters of the removable memory card and to activate a cache processor to store the data from the removable memory card to the onboard memory when the operating parameters meet predetermined criteria.

Abstract: Disclosed is a memory system that includes a nonvolatile memory having a main region and a cache region; and a memory controller having migration manager managing a migration operation that moves data from cache region to the main region by referencing a Most Recently Used/Least Recently Used (MRU/LRU) list.

Abstract: A method and system are disclosed herein for performing operations on a parallel programming unit in a memory system. The parallel programming unit includes multiple physical structures (such as memory cells in a row) in the memory system that are configured to be operated on in parallel. The method and system perform a first operation on the parallel programming unit, the first operation operating on only part of the parallel programming unit and not operating on a remainder of the parallel programming unit, set a pointer to indicate at least one physical structure in the remainder of the parallel programming unit, and perform a second operation using the pointer to operate on no more than the remainder of the parallel programming unit. In this way, the method and system may realign programming to the parallel programming unit when partial writes to the parallel programming unit occur.

Abstract: Systems and methods are disclosed for improving the performance of cache memory in a computer system by dynamically selecting an index for caching main memory while an application is running. A disclosed example of a memory system includes a cache including a data array, a primary tag array, and at least one secondary tag array. A currently selected index is used to index data bits to the data array and tag bits to the primary tag array. The performance of at least one candidate index is evaluated by indexing tag bits to the secondary tag array, without caching any data using the candidate index while the candidate index is under evaluation. If the candidate index has a better hit rate than the currently selected index, the memory system switches to using the candidate index to cache data.