Decoding Instruction To Accommodate Variable Length Instruction Or Operand Patents (Class 712/210)
  • Publication number: 20130061024
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Application
    Filed: November 5, 2012
    Publication date: March 7, 2013
    Inventors: Yen-Kueng Chen, William W. Macy, JR., Matthew Holliman, Eric L. Debes, Minerva M. Yeung
  • Publication number: 20130061025
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Application
    Filed: November 5, 2012
    Publication date: March 7, 2013
    Inventors: Yen-Kueng Chen, William W. Macy, Matthew Holliman, Eric L. Debes, Minerva M. Yeung
  • Patent number: 8364934
    Abstract: A microprocessor architecture comprising a microprocessor operably coupled to a plurality of registers and arranged to execute at least one instruction. The microprocessor is arranged to determine a class of data operand. The at least one instruction comprises one or more codes in a register specifier that indicates whether relative addressing or absolute addressing is used in accessing a register. In this manner, absolute and relative register addressing is supported within a single instruction word.
    Type: Grant
    Filed: July 11, 2006
    Date of Patent: January 29, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventor: Martin Raubuch
  • Publication number: 20120331272
    Abstract: Method, apparatus, and program means for nonlinear filtering and deblocking applications utilizing SIMD sign and absolute value operations. The method of one embodiment comprises receiving first data for a first block and second data for a second block. The first data and said second data are comprised of a plurality of rows and columns of pixel data. A block boundary between the first block and the second block is characterized. A correction factor for a deblocking algorithm is calculated with a first instruction for a sign operation that multiplies and with a second instruction for an absolute value operation. Data for pixels located along said block boundary between the first and second block are corrected.
    Type: Application
    Filed: September 4, 2012
    Publication date: December 27, 2012
    Inventors: William W. Macy, JR., Huy V. Nguyen
  • Patent number: 8335910
    Abstract: An apparatus extracts instructions from a stream of undifferentiated instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length. Decoders generate an associated start/end mark for each instruction byte of a line from a first queue of entries each storing a line of instruction bytes. A second queue has entries each storing a line received from the first queue along with the associated start/end marks.
    Type: Grant
    Filed: October 1, 2009
    Date of Patent: December 18, 2012
    Assignee: VIA Technologies, Inc.
    Inventor: Thomas C. McDonald
  • Patent number: 8302083
    Abstract: An architecture includes a controller. The controller is configured to receive a microprogram. The microprogram is configured for performing at least one of hierarchical or a sequence of polynomial computations. The architecture also includes an arithmetic logic unit (ALU) communicably coupled to the controller. The ALU is controlled by the controller. Additionally, the microprogram is compiled prior to execution by the controller, the microprogram is compiled into a plurality of binary tables, and the microprogram is programmed in a command language in which each command includes a first portion for indicating at least one of a command or data transferred to the ALU, and a second portion for including a control command to the controller. The architecture and implementation of the programmable controller may be for cryptographic applications, including those related to public key cryptography.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: October 30, 2012
    Assignee: LSI Corporation
    Inventors: Anatoli A. Bolotov, Mikhail I. Grinchuk, Lav Ivanovic, Alexei Galatenko
  • Publication number: 20120265967
    Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing an instruction of an instruction set using a non-contiguous register specifier of a non-contiguous register specification. The instruction includes the non-contiguous register specifier.
    Type: Application
    Filed: March 21, 2012
    Publication date: October 18, 2012
    Applicant: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Robert K. Montoye, Brett Olsson, John-David Wellman
  • Publication number: 20120233444
    Abstract: A data processing system 2 includes a processor core 4 and a memory 6. The processor core 4 includes processing circuitry 12, 14, 16, 18, 26 controlled by control signals generated by decoder circuitry 24 which decodes program instructions. The program instructions include mixed operand size instructions (either load/store instructions or arithmetic instructions) which have a first input operand of a first operand size and a second input operand of a second input operand size where the second operand size is smaller than the first operand size. The processing performed first converts the second operand so as to have the first operand size. The processing then generates a third operand using as inputs the first operand of the first operand size and the second operand now converted to have the first operand size.
    Type: Application
    Filed: January 19, 2012
    Publication date: September 13, 2012
    Inventors: Nigel John Stephens, David James Seal
  • Publication number: 20120210100
    Abstract: A segmental allocation method of expanding RISC processor register includes the steps of a) setting an instruction format of the RISC processor, the destination register field being set having 6 bits to correspond to 64 registers and at least one source register field having at least 4 bits to correspond to at least 16 registers; b) providing two solutions to the problem resulting from that the instruction format in the step a) goes beyond range under some circumstances; and c) setting a register segment allocation algorithm having the steps of c1) providing and grouping a plurality of pseudo registers; c2) prioritizing the pseudo registers in each of the groups; c3) combining the groups pursuant to the priorities thereof; and c4) locating the physical register of lowest computational cost.
    Type: Application
    Filed: September 9, 2011
    Publication date: August 16, 2012
    Inventors: Rong-Guey CHANG, Yuan-Shin HWANG, Chia-Hsien SU
  • Publication number: 20120173852
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Application
    Filed: March 10, 2012
    Publication date: July 5, 2012
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Publication number: 20120159129
    Abstract: A computer, circuit, and computer-readable medium are disclosed. In one embodiment, the processor includes an instruction decoder unit that can decode a macro instruction into at least one micro-operation with a set of data fields. The resulting micro-operation has at least one data field that is in a compressed form. The instruction decoder unit has storage that can store the micro-operation with the compressed-form data field. The instruction decoder unit also has extraction logic that is capable of extracting the compressed-form data field into an uncompressed-form data field. After extraction, the instruction decoder unit also can send the micro-operation with the extracted uncompressed-form data field to an execution unit. The computer also includes an execution unit capable of executing the sent micro-operation.
    Type: Application
    Filed: December 17, 2010
    Publication date: June 21, 2012
    Inventors: Kameswar Subramaniam, Anthony Wojciechowski, Jonathan D. Combs
  • Publication number: 20120159128
    Abstract: In one embodiment, the present invention is directed to a bit processor that includes an execution unit to, responsive to an instruction for access of data of a first bit width, access data of a second bit width, the second bit width having a different number of bits than the first bit width when some of the data accessed includes non-stream data. Other embodiments are described and claimed.
    Type: Application
    Filed: December 16, 2010
    Publication date: June 21, 2012
    Inventors: Raul Gutierrez, Suryaprasad Kareenahalli, Daniel Nemiroff, Balaji Vembu
  • Patent number: 8205204
    Abstract: An multi-threading processor is provided. The multi-threading processor includes a first instruction fetch unit to receive a first thread and a second instruction fetch unit to receive a second thread. A multi-thread scheduler coupled to the instruction fetch units and a execution unit. The multi-thread scheduler determines the width of the execution unit and the execution unit executes the threads accordingly.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: June 19, 2012
    Assignee: Intel Corporation
    Inventors: Ken Shoemaker, Sailesh Kottapalli, Kin-Kee Sit
  • Patent number: 8195432
    Abstract: A media capture system, method, and computer program product are provided for assessing processing capabilities utilizing cascaded memories. In use, media data is captured from a system in accordance with predetermined criteria. Additionally, the media data is stored in a plurality of cascaded memories separate from the system. Further, the media data is used for assessing media processing capabilities of the system, based on the predetermined criteria.
    Type: Grant
    Filed: November 19, 2008
    Date of Patent: June 5, 2012
    Assignee: NVIDIA Corporation
    Inventors: William S. Herz, Jihua Yu, Hao Tang
  • Patent number: 8185725
    Abstract: In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: May 22, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Brian Michael Stempel, Rodney Wayne Smith
  • Patent number: 8179540
    Abstract: An image forming apparatus is provided that holds counter information obtained by integrating a consumption of a consumable that depends on usage of service provided by the image forming apparatus. A log corresponding to the usage of the service is set in job log information with a synchronization flag set off. The log in the job log information, for which the synchronization flag is set off, is set on. The counter information and the job log information are output after the synchronization flag for the log having the synchronization flag set off has been set on.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: May 15, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Junichi Hiruma, Nobuyuki Tonegawa
  • Publication number: 20120110307
    Abstract: A compressed instruction processing device has: a compressed instruction expanding circuit which expands a compressed instruction code that include a difference code between an instruction code being a compression object and a reference instruction code and which outputs an expanded instruction code; an instruction buffer storing the instruction code expanded by the compressed instruction expanding circuit; and an execution section executing the instruction code expanded by the compressed instruction expanding circuit, wherein the compressed instruction expanding circuit outputs the expanded instruction code by inputting the instruction code in the instruction buffer as the reference instruction code and adding the reference instruction code and the difference code in the compressed instruction code.
    Type: Application
    Filed: August 15, 2011
    Publication date: May 3, 2012
    Applicant: FUJITSU SEMICONDUCTOR LIMITED
    Inventor: Masayuki TSUJI
  • Patent number: 8161269
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Grant
    Filed: March 24, 2011
    Date of Patent: April 17, 2012
    Assignee: Intel Corporation
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Publication number: 20120079247
    Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.
    Type: Application
    Filed: September 15, 2011
    Publication date: March 29, 2012
    Inventors: Timothy D. Anderson, Duc Quang Bui, Eric Biscondi, Shriram D. Moharil, Mujibur Rahman, Soujanya Narnur, Peter Richard Dent, Ashish Rai Shrivastava
  • Patent number: 8131978
    Abstract: An original first instruction word (I1) to an original third instruction word (I3) include a bit field (L11) and a bit field (L12) to a bit field (L31) and a bit field (L32). An information word (IW) includes a set of some of bit fields belonging to a plurality of instruction words executed in the same cycle, which are the bit field (L12) of the original first instruction word (I1) to the bit field (L32) of the original third instruction word (I3). An instruction decoder (103) of a processor (100) decomposes the information word (IW) and restores the arrangements of the original first instruction word (I1) to the original third instruction word (I3) by combining the bit field (L11) to the bit field (L31) to the bit field (L12) to the bit field (L32). This can reduce the amount of memory consumption without degrading the instruction execution performance.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: March 6, 2012
    Assignee: NEC Corporation
    Inventor: Shorin Kyo
  • Patent number: 8127117
    Abstract: A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined disparate source register units from a register file structure is received within a processing unit. The instruction is then executed to combine corresponding half word units from the source register units and to input the half word units into respective portions of a resulting destination register unit. During the execution of the instruction, the predetermined source register units are identified and corresponding most significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective most significant portion of a resulting destination register unit.
    Type: Grant
    Filed: May 10, 2006
    Date of Patent: February 28, 2012
    Assignee: QUALCOMM Incorporated
    Inventors: Mao Zeng, Lucian Codrescu
  • Patent number: 8028153
    Abstract: A circuit arrangement and method support data dependent instruction decoding, whereby instructions are decoded, in part, using decode data that is stored in operand registers identified by such instructions. An instruction may include an opcode and at least one operand that identifies a register. During execution of the instruction, the instruction is first decoded using the opcode, and then decode data stored in the operand register is retrieved and used to further decode the instruction, e.g., to select from among a plurality of operations or instruction types associated with the same opcode.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: September 27, 2011
    Assignee: International Business Machines Corporation
    Inventors: Mark J Hickey, Adam J Muff, Matthew R Tubbs, Charles D Wait
  • Publication number: 20110219214
    Abstract: A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.
    Type: Application
    Filed: May 16, 2011
    Publication date: September 8, 2011
    Inventors: Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
  • Patent number: 8006071
    Abstract: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.
    Type: Grant
    Filed: March 31, 2004
    Date of Patent: August 23, 2011
    Assignee: Altera Corporation
    Inventor: James Loran Ball
  • Publication number: 20110173418
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Application
    Filed: March 24, 2011
    Publication date: July 14, 2011
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Patent number: 7979676
    Abstract: A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: July 12, 2011
    Assignee: Panasonic Corporation
    Inventors: Takeshi Kishida, Masaitsu Nakajima
  • Patent number: 7966476
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: June 21, 2011
    Assignee: Intel Corporation
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Patent number: 7962725
    Abstract: A pre-decoder in a variable instruction length processor indicates properties of instructions in pre-decode bits stored in an instruction cache with the instructions. When all the encodings of pre-decode bits associate with one length instruction are defined, a property of an instruction of that length may be indicated by altering the instruction to emulate an instruction of a different length, and encoding the property in the pre-decode bits associated with instructions of the different length. One example of a property that may be so indicated is an undefined instruction.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: June 14, 2011
    Assignee: QUALCOMM Incorporated
    Inventors: Rodney Wayne Smith, Brian Michael Stempel
  • Patent number: 7953955
    Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.
    Type: Grant
    Filed: December 14, 2010
    Date of Patent: May 31, 2011
    Assignee: Altera Corporation.
    Inventors: Sergei Yurievich Larin, Gerald George Pechanek, Thomas M. Conte
  • Patent number: 7945605
    Abstract: A new technique for accelerating the computational speed of a computer algorithm is provided. The inventive technique can be applied to video compression/decompression algorithms, optical character recognition algorithms, and digital camera zooming applications.
    Type: Grant
    Filed: December 28, 2009
    Date of Patent: May 17, 2011
    Assignee: Cipherflux, LLC
    Inventors: Jerzy Henryk Urbanik, Krzysztof Ryszard Kalita, Przemyslaw Bartlomiej Bezeg
  • Publication number: 20110083001
    Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.
    Type: Application
    Filed: December 14, 2010
    Publication date: April 7, 2011
    Applicant: Altera Corporation
    Inventors: Sergei Yurievich Larin, Gerald George Pechanek, Thomas M. Conte
  • Patent number: 7917734
    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 29, 2011
    Assignee: Intel Corporation
    Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
  • Patent number: 7908463
    Abstract: An extraction and decode mechanism for acquiring and processing instructions and the corresponding constant(s) embedded within the instructions. The extraction and decode mechanism may be included within a processing unit, and may comprise an instruction decode unit and at least one constant steer network. During operation, the instruction decode unit may obtain and decode instructions which are to be executed by the processing unit. For each instruction, the instruction decode unit may also determine the location of one or more constants embedded within the instruction. The constant steer network may receive the location information from the instruction decode unit. While the instruction decode unit decodes the instruction, the constant steer network may obtain the constant(s) embedded within the instruction based on the location information and store the constant(s). The constant(s) embedded within the instruction may be immediate or displacement (imm/disp) constant(s).
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: March 15, 2011
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Sean Lie
  • Patent number: 7895418
    Abstract: There is disclosed an operand queue for use in a floating point unit. The floating point unit comprises floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions that read operands from the external memory. The floating point also comprises an operand queue for storing a plurality of operands associated with one or more operations being processed in the floating point unit. The operand queue stores a first operand being written to an external memory by a floating point write instruction executed by a first one of the plurality of floating point processing units and supplies the first operand to a floating point read instruction executed by a second one of the plurality of floating point processing units subsequent to the execution of the floating point write instruction.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: February 22, 2011
    Assignee: National Semiconductor Corporation
    Inventor: Daniel W. Green
  • Patent number: 7895414
    Abstract: An instruction length determination device includes an instruction input unit having a memory space to store a plurality of N-bit data; an instruction fetch unit which fetches the plurality of N-bit data from the instruction input unit; an instruction length determination logic which compares concatenate bits of a first N-bit data with a predetermined value for determination of an instruction length; and an instruction concatenate unit which selectively concatenates a number of successive N-bit data based on the determination. The instruction length determination logic determines that the first N-bit data is a complete instruction when the concatenate bit of the first N-bit data is not equal to the predetermined value. Otherwise, the instruction length determination logic determines that a complete instruction is formed of last N-bit data finally fetched and all N-bit previously reserved.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: February 22, 2011
    Assignee: Sunplus Technology Co., Ltd.
    Inventor: Lian Sung
  • Patent number: 7882325
    Abstract: A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: February 1, 2011
    Assignee: Intel Corporation
    Inventors: Zeev Sperber, Robert Valentine, Ehud Cohen, Doron Orenstien, Benny Eitan
  • Patent number: 7865699
    Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: January 4, 2011
    Assignee: International Business Machines Corporation
    Inventors: Erik R Altman, Michael Gschwind, David A. Luick, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman
  • Patent number: 7844800
    Abstract: A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further processing. The remaining set are performed in sequence with the results being passed via a background channel 34 for further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.
    Type: Grant
    Filed: August 21, 2007
    Date of Patent: November 30, 2010
    Assignee: ARM Limited
    Inventors: Melanie Emanuelle Lucie Vincent, Florent Begon, Cedric Denis Robert Airaud, Norbert Bernard Eugene Lataille
  • Patent number: 7844654
    Abstract: An arithmetic unit of arbitrary-precision, including: a main processing unit, which splits up the first and the second arbitrary-precision values into N-bit (where N is a natural number) operands respectively in the-least-significant-bit-first order for computing with the arbitrary-precision data and consecutively outputting a series of pairs of the first and second N-bit operands; and an N-bit arithmetic unit, which performs computing with the N-bit operands, while requesting the main processing unit to feed the next N-bit operands each time the computation completes. The carry bit generated by the operation is fed to the next N-bit operation.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: November 30, 2010
    Assignee: Seiko Epson Corporation
    Inventor: Nobuo Karaki
  • Publication number: 20100299503
    Abstract: An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes.
    Type: Application
    Filed: October 1, 2009
    Publication date: November 25, 2010
    Applicant: VIA Technologies, Inc.
    Inventors: Thomas C. McDonald, John L. Duncan
  • Patent number: 7836278
    Abstract: A method and apparatus are contemplated for increasing the number of available instructions in an instruction set architecture. The new instructions extend the number of general-purpose registers and include three or more operands. A combination of an escape code field, an opcode field, an operation configuration field and an operation size field determines a unique new instruction operation. A source operand extension field includes bits to be combined with other fields in order to extend the number of source operand values for general-purpose registers.
    Type: Grant
    Filed: December 12, 2007
    Date of Patent: November 16, 2010
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ranganathan Sudhakar, Michael Frank, Debjit Dassarma
  • Publication number: 20100287359
    Abstract: A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor.
    Type: Application
    Filed: May 11, 2009
    Publication date: November 11, 2010
    Applicant: MIPS Technologies, Inc.
    Inventor: Erik K. Norden
  • Publication number: 20100268919
    Abstract: A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.
    Type: Application
    Filed: April 20, 2009
    Publication date: October 21, 2010
    Inventors: Shailender Chaudhry, Marc Tremblay
  • Patent number: 7818543
    Abstract: A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions, which are scheduled to be executed by a processing unit. The length decode unit may, for each instruction byte, estimate the start of a next variable length instruction following a current variable length instruction, and store a first pointer. A pre-pick unit may, for each instruction byte, use the first pointer to estimate the start of a subsequent variable length instruction following the next variable length instruction within the scan window, and store a second pointer. A pick unit may use a start pointer and related first and second pointers to determine the actual start of the variable length instructions within the scan window, and generate instruction pointers.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: October 19, 2010
    Assignee: GlobalFoundries Inc.
    Inventors: Gene W. Shen, Sean Lie
  • Patent number: 7818542
    Abstract: A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be associated with a plurality of variable length instructions, which are to be executed by the processing unit. The length decode unit may perform a length decode operation for each of the plurality of instruction bytes. For each instruction byte, the length decode unit may estimate the instruction length of a current variable length instruction associated with a current instruction byte. Furthermore, during the length decode operation, for each instruction byte, the length decode unit may estimate the start of a next variable length instruction based on the estimated instruction length of the current variable length instruction, and store a first pointer to the estimated start of the next variable length instruction.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: October 19, 2010
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Gene W. Shen, Sean Lie
  • Patent number: 7814299
    Abstract: A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: October 12, 2010
    Assignee: International Business Machines Corporation
    Inventors: Mark Joseph Hickey, Adam James Muff, Matthew Ray Tubbs, Charles David Wait
  • Patent number: 7797516
    Abstract: A set of low-cost microcontroller extensions facilitates Digital Signal Processing (DSP) applications by incorporating a Multiply-Accumulate (MAC) unit in a Central Processing Unit (CPU) of the microcontroller which is responsive to the extensions.
    Type: Grant
    Filed: March 16, 2007
    Date of Patent: September 14, 2010
    Assignee: ATMEL Corporation
    Inventors: Benjamin Francis Froemming, Emil Lambrache
  • Patent number: RE41751
    Abstract: A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1tA unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k?1)th unit field in the same parallel execution code.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: September 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Taketo Heishi, Tetsuya Tanaka, Nobuo Higaki, Shuichi Takayama, Kensuke Odani
  • Patent number: RE41959
    Abstract: The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: November 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Masato Suzuki, Hiroshi Kamiyama, Shinya Miyaji
  • Patent number: RE43248
    Abstract: Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: March 13, 2012
    Assignee: ARM Limited
    Inventor: Edward Colles Nevill