Decoding Instruction To Accommodate Variable Length Instruction Or Operand Patents (Class 712/210)
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Patent number: 7301541Abstract: A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.Type: GrantFiled: July 10, 2003Date of Patent: November 27, 2007Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris, Alexia Massalin
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Patent number: 7290120Abstract: A microprocessor having a power-saving fetch and decoding unit for fetching and decoding compressed program instructions and having a program instruction sequencer is disclosed. The microprocessor based on the inventive architecture has a power-saving fetch and decoding unit for fetching and decoding program instructions. The fetch and decoding unit has a program instruction memory which receives a sequential program instruction address addressing the next program instruction memory line which is to be read, having at least one program instruction memory line which can store an indicator flag, a long program instruction index, a short program instruction and a first source register address. A directory memory receives the long program instruction index (6) addressing the next directory memory line which is to be read.Type: GrantFiled: January 14, 2005Date of Patent: October 30, 2007Assignee: Infineon Technologies AGInventor: Lorenzo DiGregorio
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Patent number: 7290153Abstract: Included in this disclosure is a circuit for reducing power consumption in a microprocessor. The circuit comprises a microprocessor, at least one full instruction decoder configured to decode a present instruction, and at least one subset instruction decoder configured to determine whether the present instruction potentially needs a register. A memory element is also included and is configured to hold data from a previous instruction. A selector is included and configured to output either the previous instruction or the decoded present instruction, based on the subset instruction decoder.Type: GrantFiled: November 8, 2004Date of Patent: October 30, 2007Assignee: VIA Technologies, Inc.Inventor: Richard Duncan
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Patent number: 7284115Abstract: A processor supports a mode in which the default operand size is 32 bits, but which supports operand size overrides to 64 bits. Furthermore, the default operand size may automatically be overridden to 64 bits for instructions having an implicit stack pointer reference and for near branch instructions. The overriding of the default operand size may occur without requiring an operand size override encoding in these instructions. In one embodiment, the instruction set specifying the instructions may be a variable byte length instruction set (e.g. x86), and the operand size override encoding may be a prefix byte which increases the instruction length.Type: GrantFiled: September 8, 2004Date of Patent: October 16, 2007Assignee: Advanced Micro Devices, Inc.Inventor: Kevin J. McGrath
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Patent number: 7263621Abstract: The present disclosure illustrates a system for reducing power consumption in a computer processor. Included is a 16-bit instruction decoder for decoding instructions with 16-bit words, a 32-bit instruction decoder for decoding instructions with 32-bit words, a word length select for indicating a present instruction's word length, and a first selector for routing the instruction into the 16-bit decoder when the present instruction is 16-bits long. The first selector is also configured to route a previous instruction into the 16-bit decoder, maintaining the 16-bit decoder's present state. A second selector is configured to route the instruction into the 32-bit decoder when the present instruction is 32-bits long. The second selector is also configured to route a past instruction into the 32-bit decoder to maintain the 32-bit decoder's present state.Type: GrantFiled: November 15, 2004Date of Patent: August 28, 2007Assignee: VIA Technologies, Inc.Inventor: Richard Duncan
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Patent number: 7254696Abstract: A functional-level instruction-set computing (FLIC) architecture executes higher-level functional instructions such as lookups and bit-compares of variable-length operands. Each FLIC processing-engine slice has specialized processing units including a lookup unit that searches for a matching entry in a lookup cache. Variable-length operands are stored in execution buffers. The operand length and location in the execution buffer are stored in fixed-length general-purpose registers (GPRs) that also store fixed-length operands. A copy/move unit moves data between input and output buffers and one or more FLIC processing-engine slices. Multiple contexts can each have a set of GPRs and execution buffers. An expansion buffer in a FLIC slice can be allocated to a context to expand that context's execution buffer for storing longer operands.Type: GrantFiled: December 12, 2002Date of Patent: August 7, 2007Assignee: Alacritech, Inc.Inventors: Millind Mittal, Mehul Kharidia, Tarun Kumar Tripathy, J. Sukarno Mertoguno
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Patent number: 7246218Abstract: A system for executing instructions is presented. In some embodiments, among others, the system comprises functional units, local multiplexers, local register files, and a global register file, which are communicatively coupled to each other and arranged to accommodate shortened instruction words in multiple-issue processors. These components are arranged to permit greater access to registers by instructions, thereby permitting reduction of the word length, as compared to conventional very long instruction word (VLIW) processors.Type: GrantFiled: November 1, 2004Date of Patent: July 17, 2007Assignee: VIA Technologies, Inc.Inventors: Boris Prokopenko, Timour Paltashev, Derek Edward Davout Gladding
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Patent number: 7228403Abstract: A method for operating a processor having an architecture of a larger bitlength with a program comprising instructions compiled to produce instruction results of at least one smaller bitlength having the steps of detecting when in program order a first smaller bitlength instruction is to be dispatched which does not have a target register address as one of its sources, and adding a so_extract_instruction into an instruction stream before the smaller bitlength instruction.Type: GrantFiled: December 18, 2001Date of Patent: June 5, 2007Assignee: International Business Machines CorporationInventors: Petra Leber, Jens Leenstra, Wolfram Sauer, Dieter Wendel
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Patent number: 7216218Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.Type: GrantFiled: June 2, 2004Date of Patent: May 8, 2007Assignee: Broadcom CorporationInventor: Sophie Wilson
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Patent number: 7216138Abstract: A method and apparatus are described for converting a number from a floating point format to an integer format or from an integer format to a floating point format responsive to a control signal of a control signal format. Numbers are stored in the floating point format in a register of a first set of architectural registers in a packed format. One or more numbers in the floating point format are converted to the integer format and placed in a register of a second set of architectural registers in a packed format. Conversion from integer format to floating point format is performed in a similar manner. A floating point arithmetic apparatus is described that provides for converting a plurality of numbers between integer formats and a floating point formats, further providing for conversion operations that require a greater data path width than floating-point arithmetic operations.Type: GrantFiled: February 14, 2001Date of Patent: May 8, 2007Assignee: Intel CorporationInventors: Mohammad Abdallah, Prasad Modali, Chien-Yu Huang, legal representative, Thomas R. Huff, Vladimir Pentkovski, Patrice Roussel, Shreekant S. Thakkar, Hsien-Cheng E. Hsieh, deceased
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Patent number: 7213129Abstract: A system and method for aligning an instruction stream is described. The system comprises a rotator logic unit for rotating data bytes of the instruction stream. A shifter logic unit is used for shifting the data bytes to the start of a instruction based upon a length of an immediately prior instruction.Type: GrantFiled: August 30, 1999Date of Patent: May 1, 2007Assignee: Intel CorporationInventors: Fred Gruner, Mike Morrison, Kushagra Vaid
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Patent number: 7206921Abstract: A processor may include an instruction decoder to decode macroinstructions into micro-operations. In some embodiments, the instruction decoder may include a first decoder and a second decoder. The first decoder may decode a macroinstruction having SSE data type operands into a laminated micro-operation, and may generate unlamination information for the laminated micro-operation. The second decoder may generate from the laminated micro-operation and the unlamination information two or more micro-operations, where operands of the two or more micro-operations each correspond to a half of one of the SSE operands of the macroinstruction.Type: GrantFiled: April 7, 2003Date of Patent: April 17, 2007Assignee: Intel CorporationInventors: Zeev Sperber, Robert Valentine, Simcha Gochman
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Patent number: 7194602Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.Type: GrantFiled: March 12, 2003Date of Patent: March 20, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Kishida, Masaitsu Nakajima
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Patent number: 7149879Abstract: A processor and method of automatic instruction mode switching between N-bit and 2N-bit instructions by using parity bit check. The processor and method includes an instruction input device having a memory for storing a plurality of 2N-bit words, an instruction fetch device fetching a 2N-bit word from the memory, and a mode switch logic determining whether the 2N-bit word fetched by the instruction fetch device is two (N-P)-bit instructions or one 2(N-P)-bit instruction to accordingly switch the processor to corresponding N-bit or 2N-bit mode, wherein when the 2N-bit word fetched is even parity, the 2N-bit word is determined as two (N-P)-bit instructions if two N-bit words included in the 2N-bit word are on the even parity state, or determined as a 2(N-P)-bit instruction if the two N-bit words are on the odd parity state.Type: GrantFiled: October 14, 2003Date of Patent: December 12, 2006Assignee: Sunplus Technology Co., Ltd.Inventor: Bor-Sung Liang
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Patent number: 7133040Abstract: An apparatus and method for performing an insert-extract operation on packed data using computer-implemented steps is described. In one embodiment, a first data operand having a data element is accessed. A second packed data operand having at least two data elements is then accessed. The data element in the first data operand is inserted into any destination field of a destination register, or alternatively, a data element is extracted from any field of the source register.Type: GrantFiled: March 31, 1998Date of Patent: November 7, 2006Assignee: Intel CorporationInventors: Mohammad Abdallah, Srinivas Chennupaty, Robert S. Dreyer, Michael A. Julier, Katherine Kong, Larry Mennemeier, Ticky S. Thakkar
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Patent number: 7120779Abstract: A data processing system 2 is provided supporting address offset generating instructions which encode bits of an address offset value using previously redundant bits in a legacy instruction encoding whilst maintaining backwards compatibility with that legacy encoding.Type: GrantFiled: January 28, 2004Date of Patent: October 10, 2006Assignee: ARM LimitedInventor: David James Seal
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Patent number: 7103754Abstract: A computer architecture that provides the definition of a 20 bit signed displacement value used to form the operand storage address.Type: GrantFiled: March 28, 2003Date of Patent: September 5, 2006Assignee: International Business Machines CorporationInventors: Mark A. Check, Brian B. Moore, Timothy J. Slegel
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Patent number: 7089393Abstract: A data processing system using a main processor 8 and a coprocessor 10 provides coprocessor load instructions (USALD) for loading a variable number of data values dependent upon alignment into the coprocessor 10 and also specifying data processing operations to be performed upon operands within those loaded data words to generate result data words. The specified coprocessor processing operations may be a sum of absolute differences calculation for a row of pixel byte values. The result of this may be accumulated within an accumulate register 22. A coprocessor memory 18 is provided within the coprocessor 10 to provide local storage of frequently used operand values for the coprocessor 10.Type: GrantFiled: January 11, 2002Date of Patent: August 8, 2006Assignee: ARM LimitedInventors: Paul Matthew Carpenter, Peter James Aldworth
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Patent number: 7080235Abstract: A method for controlling functional units in a processor, according to which in a configuration a sequence of primary instruction words which consists of several instruction word parts and originates from a translation of a program code is compressed and stored as a sequence of associated program words. The invention also relates to a processor system for carrying out this method. The aim of the invention is to increase operating speed in an application-specific manner while retaining a low program word width. To this end, as regards the method, a program word contains a first characteristic of a primary instruction word and instruction word parts which differentiate the primary instruction word belonging to the program word from the primary instruction word belonging to the characteristic.Type: GrantFiled: December 21, 1999Date of Patent: July 18, 2006Assignee: Systemonic AGInventor: Matthias Weiss
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Patent number: 7069422Abstract: A shift left with carry instruction minimizes the number of instructions required for implementing a binary search. A multi-thread packet processor transfers a data packet from a flexible data input buffer to a packet task manager, dispatches the data packet from the packet task manager to a multi-threaded pipelined analysis machine, classifies the data packet in the analysis machine, modifies and forwards the data packet in a packet manipulator, wherein the analysis machine implements a binary search by executing a shift left with carry instruction to minimize the number of instructions required for the binary search. The multi-thread packet processor includes an analysis machine having multiple pipelines, wherein one pipeline is dedicated to directly manipulating individual data bits of a bit field, a packet task manager, a packet manipulator, a global access bus including a master request bus and a slave request bus separated from each other and pipelined, an external memory engine, and a hash engine.Type: GrantFiled: December 22, 2000Date of Patent: June 27, 2006Inventors: Richard P. Modelski, Michael J. Craren
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Patent number: 7069423Abstract: A built-in memory is divided into the following two types: first memories 5 and 7 and second memories 4 and 6, and made accessible in parallel by third buses XAB and XDB and second buses YAB and YDB respectively. Thereby, a CPU core 2 can simultaneously transfer two data values from the built-in memory to a DSP engine 3. Moreover, the third buses XAB and XDB and the second buses YAB and YDB are also separate from first buses IAB and IDB to be externally interfaced and the CPU core 2 can access an external memory in parallel with the access to the second memories 4 and 6 and the first memories 5 and 7.Type: GrantFiled: July 22, 2002Date of Patent: June 27, 2006Assignee: Hitachi, Ltd.Inventors: Hiroshi Ohsuga, Atsushi Kiuchi, Hironobu Hasegawa, Toru Baji, Koki Noguchi, Yasushi Akao, Shiro Baba
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Patent number: 7069420Abstract: In one particular embodiment, a processor receives and processes a plurality of instruction from a single instruction register. The processor loads the plurality of instructions into a single register and determines the number and size of instructions while the instructions are in the register. Each of the plurality of instructions is then simultaneously presented to the decoder. The decoder then decodes a first of the plurality of instructions and determines whether any additional instructions are present.Type: GrantFiled: September 28, 2000Date of Patent: June 27, 2006Assignees: Intel Corporation, Analog Devices, Inc.Inventors: Gregory A. Overkamp, Charles P. Roth, Ravi P. Singh
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Patent number: 7062634Abstract: A processor is described in which the need to encode no-operation instructions (nops) in the program is minimised by providing a device for generating nops in response to information encoded in operative instructions.Type: GrantFiled: January 29, 2002Date of Patent: June 13, 2006Assignee: STMicroelectronics LimitedInventors: Trefor Southwell, Peter Hedinger
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Patent number: 7051189Abstract: An improved method of optimizing the instruction set of a digital processor using code compression. In one embodiment, the method comprises obtaining an assembly language program to be used for the optimization process; calculating the static frequency of each instruction type from the base instruction set; sorting the instruction types by frequency; determining the number and type of instructions necessary for correct program execution; creating a compressed instruction set encoding; re-evaluating the compressed instruction according to the foregoing steps; and generating an instruction set encoding for the compressed instruction set. Improved compressed instruction formats and register structures useful in a processor are also disclosed. A computer program and apparatus for synthesizing logic implementing the aforementioned data cache architecture and pipeline performance enhancements are further disclosed.Type: GrantFiled: March 14, 2001Date of Patent: May 23, 2006Assignee: ARC InternationalInventor: Peter Warnes
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Patent number: 7051190Abstract: Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.Type: GrantFiled: June 25, 2002Date of Patent: May 23, 2006Assignee: Intel CorporationInventors: Nicholas G. Samra, Stephen J. Jourdan
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Patent number: 7047396Abstract: A method and system for fixed-length memory-to-memory processing of fixed-length instructions. Further, the present invention is a method and system for implementing a memory operand width independent of the ALU width. The arithmetic and register data are 32 bits, but the memory operand is variable in size. The size of the memory operand is specified by the instruction. Instructions in accordance with the present invention allow for multiple memory operands in a single fixed-length instruction. The instruction set is small and simple, so the implementation is lower cost than traditional processors. More addressing modes are provided for, thus creating a more efficient code. Semaphores are implemented using a single bit. Shift-and-merge instructions are used to access data across word boundaries.Type: GrantFiled: June 22, 2001Date of Patent: May 16, 2006Assignee: Ubicom, Inc.Inventors: David A. Fotland, Roger D. Arnold, Tibet Mimaroglu
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Patent number: 7043627Abstract: In view of a necessity of alleviating factors obstructing an effect of SIMD operation such as in-register data alignment in high speed formation of an SIMD processor, numerous data can be supplied to a data alignment operation pipe 211 by dividing a register file into four banks and enabling to designate a plurality of registers by a single piece of operand to thereby enable to make access to four registers simultaneously and data alignment operation can be carried out at high speed. Further, by defining new data pack instruction, data unpack instruction and data permutation instruction, data supplied in a large number can be aligned efficiently. Further, by the above-described characteristic, definition of multiply accumulate operation instruction maximizing parallelism of SIMD can be carried out.Type: GrantFiled: September 4, 2001Date of Patent: May 9, 2006Assignee: Hitachi, Ltd.Inventors: Takehiro Shimizu, Fumio Arakawa
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Patent number: 6996700Abstract: Herein disclosed is a microcomputer MCU adopting the general purpose register method. The microcomputer is enabled to have a small program capacity or a high program memory using efficiency and a low system cost, while enjoying the advantage of simplification of the instruction decoding as in the RISC machine having a fixed length instruction format of the prior art, by adopting a fixed length instruction format having a power of 2 but a smaller bit number than that of the maximum data word length fed to instruction execution means. And, the control of the coded division is executed by noting the code bits.Type: GrantFiled: December 11, 2001Date of Patent: February 7, 2006Assignee: Renesas Technology Corp.Inventors: Shumpei Kawasaki, Eiji Sakakibara, Kaoru Fukada, Takanaga Yamazaki, Yasushi Akao, Shiro Baba, Toshimasa Kihara, Keiichi Kurakazu, Takashi Tsukamoto, Shigeki Masumura, Yasuhiro Tawara, Yugo Kashiwagi, Shuya Fujita, Katsuhiko Ishida, Noriko Sawa, Yoichi Asano, Hideaki Chaki, Tadahiko Sugawara, Masahiro Kainaga, Kouki Noguchi, Mitsuru Watabe
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Patent number: 6970993Abstract: The present invention provides a memory architecture allowing for instructions of variable length to be stored without wasted memory spaces. Instructions of one, two, and three bytes can all be retrieved in a single fetch. The exemplary embodiment divides the memory block into two ×16 memories having some special addressing circuitry. This structure logically arranges the memory into a number of rows, each of four byte-wide columns. To the first of these ×16 memories, the full address is provided. If the address is within the two columns of the second ×16 memory, the full address is also provided to the second ×16 memory. If the address is to the first of the ×16 memories, the second ×16 memory instead receives the portion of the address specifying the row with one added to it. This results in a dual row access with the last one or two bytes of 3-byte instruction being supplied by the row above the first byte.Type: GrantFiled: September 8, 2003Date of Patent: November 29, 2005Assignee: ZiLOG, Inc.Inventors: Bruce L. Troutman, Russell B. Lloyd, Randal Q. Thornley
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Patent number: 6968430Abstract: A circuit and method are contemplated herein for improving instruction fetch time by determining mapping information prior to storage of the mapping information in a lower-level memory device. In one embodiment, the circuit and method are adapted to format and align the prefetched instructions into predecoded instructions, and determine mapping information relating the prefetched instructions to the predecoded instructions. In addition, the circuit and method may be adapted to store the mapping information along with corresponding predecoded instructions. By determining the mapping information prior to storage of the mapping information within the lower-level memory device, the circuit and method advantageously increases the rate at which the predecoded instructions may be fetched from the lower-level memory device.Type: GrantFiled: October 22, 2002Date of Patent: November 22, 2005Assignee: LSI Logic CorporationInventor: Asheesh Kashyap
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Patent number: 6968402Abstract: Techniques to buffer and present chunks are disclosed. In some embodiments, a first interface may receive chunks of a first cache line, and a second interface may receive chunks of a second cache line. A buffer may store chunks of the first cache line in a first chunk order and may store chunks of the second cache line in a second chunk order. A control unit may present a requester via the second interface with one or more chunks of the first cache line from the buffer.Type: GrantFiled: May 22, 2003Date of Patent: November 22, 2005Assignee: Intel CorporationInventors: David R. Jackson, Stephen W. Kiss, Miles F. Schwartz
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Patent number: 6961844Abstract: A system and method are presented for pre-decoding (i.e., determining the address boundaries of) variable-length instructions within an instruction block fetched from memory. The instruction block represents the contents of consecutive addresses in memory, and is fetched in response to a microprocessor request for a specific instruction within the block. After pre-decoding, the instructions present in the block are placed into a cache for execution by the microprocessor. Conventional instruction pre-decoding methods apply only to instructions fetched from addresses at or beyond the address of the requested instruction. The remaining instructions in the block are therefore not utilized. The system and method disclosed herein permit backward pre-decoding of the instruction block, in which the address boundaries of instructions fetched from addresses prior to that of the requested instruction may also be determined. This capability results in more efficient use of the cache.Type: GrantFiled: October 5, 2001Date of Patent: November 1, 2005Assignee: LSI Logic CorporationInventors: Charles H. Stewart, Asheesh Kashyap
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Patent number: 6957320Abstract: The present invention provides a system and method for managing load and store operations necessary for reading from and writing to memory or I/O in a superscalar RISC architecture environment. To perform this task, a load store unit is provided whose main purpose is to make load requests out of order whenever possible to get the load data back for use by an instruction execution unit as quickly as possible. A load operation can only be performed out of order if there are no address collisions and no write pendings. An address collision occurs when a read is requested at a memory location where an older instruction will be writing. Write pending refers to the case where an older instruction requests a store operation, but the store address has not yet been calculated. The data cache unit returns 8 bytes of unaligned data. The load/store unit aligns this data properly before it is returned to the instruction execution unit.Type: GrantFiled: July 9, 2002Date of Patent: October 18, 2005Assignee: Seiko Epson CorporationInventors: Cheryl D. Senter, Johannes Wang
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Patent number: 6952745Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.Type: GrantFiled: June 25, 2004Date of Patent: October 4, 2005Assignee: Intel CorporationInventors: James M. Dodd, Brian P. Johnson, Jay C. Wells, John B. Halbert
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Patent number: 6944749Abstract: A method for decoding instructions in an execution package with a processor includes using an assembler to assemble instructions into different execution packages. Each instruction has an identification segment and an instruction segment. The method also includes using the assembler to reorder the instructions by separating identification segments from instruction segments, grouping all identification segments of the execution package together, and grouping all instruction segments of the execution package together. The method uses the processor to decode identification segments of the instructions at the same time, and adds a length of each identification segment together to calculate a total length of the execution package.Type: GrantFiled: July 29, 2002Date of Patent: September 13, 2005Assignee: Faraday Technology Corp.Inventor: Shan-Chyun Ku
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Patent number: 6922737Abstract: A storage control device, connected to a host processing device through a full-duplex channel and for storing data received through the channel in a data storage means, comprises a plurality of channel processors for conducting a data-input-and-output process to the data storage means in correspondence with a command contained in data (a frame) sent from the host processing device through the channel, and a channel processor, among the plurality of channel processors, is assigned for executing the data-input-and-output process for the data (frame) according to a type of command contained in the data (frame). Thus, the storage control device of the present invention can use the full-duplex channel efficiently.Type: GrantFiled: September 10, 2002Date of Patent: July 26, 2005Assignee: Hitachi, Ltd.Inventors: Masami Maeda, Yoshihiro Asaka, Hidetoshi Sakaki, Masaru Tsukada
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Patent number: 6907516Abstract: Compressing program binaries with reduced compression ratios. One or several pre-processing acts are performed before performing compression using a local sequential correlation oriented compression technology such as PPM, or one of its variants or improvements. One pre-processing act splits the binaries into several substreams that have high local sequential correlation. Such splitting takes into consideration the correlation between common fields in different instructions as well as the correlation between different fields in the same instruction. Another pre-processing reschedules binary instructions to improve the degree of local sequential correlation without affecting dependencies between instructions. Yet another pre-processing act replaces common operation codes in the instruction with a symbols from a second alphabet, thereby distinguishing between operation codes that have a particular value, and other portions of the instruction that just happen to have the same value.Type: GrantFiled: May 30, 2002Date of Patent: June 14, 2005Assignee: Microsoft CorporationInventors: Darko Kirovski, Milenko Drinic, Hoi Huu Vo
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Patent number: 6901503Abstract: An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. external pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test dat or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SERCLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control.Type: GrantFiled: October 29, 2001Date of Patent: May 31, 2005Assignee: Cambridge Consultants Ltd.Inventors: Stephen John Barlow, Alistair Guy Morfey, James Digby Collier
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Patent number: 6889312Abstract: A processor supports multiple operand sizes (e.g. 8, 16, 32, and 64 bit operand sizes, in one embodiment). Additionally, the processor determines how to update a destination register when an operand size less than the largest operand size is used. In one embodiment, the processor determines whether or not to zero extend the result responsive to the operand size used. In one particular embodiment, the processor zero extends 32 bit operands and does not zero extend 8 or 16 bit operands. Furthermore, the processor may preserve the value in at least part of the remaining portion of the register when 8 or 16 bit operand sizes are used.Type: GrantFiled: April 2, 2001Date of Patent: May 3, 2005Assignee: Advanced Micro Devices, Inc.Inventors: Kevin J. McGrath, Ramsey W. Haddad, Bruce R. Holloway, I-Cheng K. Chen
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Patent number: 6889313Abstract: A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.Type: GrantFiled: May 2, 2000Date of Patent: May 3, 2005Assignee: STMicroelectronics S.A.Inventors: Andrew Cofler, Stéphane Bouvier, Laurent Wojcieszak
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Patent number: 6877084Abstract: A central processing unit (CPU) is described including a register file and an execution core coupled to the register file. The register file includes a standard register set and an extended register set. The standard register set includes multiple standard registers, and the extended register set include multiple extended registers. The execution core fetches and executes instructions, and receives a signal indicating an operating mode of the CPU. The execution core responds to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register. The standard registers may be general purpose registers of a CPU architecture associated with the instruction. The number of extended registers may be greater than the number of general purpose registers defined by the CPU architecture.Type: GrantFiled: April 2, 2001Date of Patent: April 5, 2005Assignee: Advanced Micro Devices, Inc.Inventor: David S. Christie
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Patent number: 6871274Abstract: A processor includes a conversion table storage unit storing therein a table used to convert to a non-compressed instruction code from an index included in a compressed instruction code, and a conversion unit receiving a compressed instruction code to extract an index and a parameter therefrom to convert the extracted index to a non-compressed instruction code to incorporate the parameter into the obtained non-compressed instruction code to recover an instruction code for transmission to an instruction decode unit.Type: GrantFiled: June 7, 2002Date of Patent: March 22, 2005Assignee: Renesas Technology Corp.Inventor: Yasuhiro Nunomura
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Patent number: 6865664Abstract: Embodiments of systems, methods, and computer program products are provided for compressing a computer program based on a compression criterion and executing the compressed program. For example, a computer program may be compressed by scanning an initial computer program to identify one or more uncompressed instructions that have a high frequency of use. A storage mechanism, such as a data structure, may then be populated with the identified uncompressed instructions. A compressed computer program may be generated by respectively replacing one or more of the identified uncompressed instructions with a compressed instruction that identifies a location of the corresponding uncompressed instruction in the storage mechanism. Additional compression of the computer program may be achieved by scanning the compressed computer program to identify one or more uncompressed instructions that have a high frequency of use when at least a portion of their instruction operand is ignored.Type: GrantFiled: December 13, 2000Date of Patent: March 8, 2005Assignee: Conexant Systems, Inc.Inventors: Martin T. Budrovic, David J. Kolson
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Patent number: 6865666Abstract: A data processing device having a PC controlling part for executing an operation of branch which has a first register for holding a result of decoding in an instruction decode unit, a register for holding a description indicating an execution condition of the operation (a value of field for designating condition), and a register for holding the description indicating a time for executing the operation (an address value of PC), wherein the execution condition is started when a value held in the register is in agreement with a PC value in accordance with the description of the register; and if the condition is satisfied, the PC controlling part executes the operation based on a content held in the register, whereby it is possible to delay the time for judging the execution condition during this delay, to thereby increase a degree of freedom in scheduling instructions such that the branch instruction is positioned prior to the operation instruction for determining the execution condition in the program.Type: GrantFiled: September 3, 1998Date of Patent: March 8, 2005Assignee: Renesas Technology Corp.Inventors: Toyohiko Yoshida, Hideyuki Fujii
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Patent number: 6859873Abstract: A variable length instruction pipeline includes optional expansion stages that can be included in the variable length instruction pipeline to avoid pipeline stalls. The expansion stages are removed from the variable length instruction pipeline when not needed to reduce the length of the pipeline, which reduces latency and other problems associated with long pipelines. For example, in one embodiment of the present invention, a variable length instruction pipeline includes a first pipeline stage, a first expansion stage, and a second pipeline stage. The second pipeline stage is configured to selectively receive instructions from the first pipeline stage or the first expansion stage if the first expansion stage holds an instruction.Type: GrantFiled: June 8, 2001Date of Patent: February 22, 2005Assignee: Infineon Technologies AGInventors: Erik K. Norden, Roger D. Arnold, Robert E. Ober, Neil S. Hastie
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Patent number: 6850999Abstract: A coherency resolution technique enables efficient resolution of data coherency for packet data associated with a service queue of an intermediate network node. The packet data is enqueued on a write buffer prior to being stored on an external packet memory of a packet memory system. The packet data may be interspersed among other packets of data from different service queues, wherein the packets are of differing sizes. In response to a read request for the packet data, a coherency operation is performed by coherency resolution logic on the data in the write buffer to determine if any of its enqueued data can be used to service the request.Type: GrantFiled: November 27, 2002Date of Patent: February 1, 2005Assignee: Cisco Technology, Inc.Inventors: Kwok Ken Mak, Xiaoming Sun
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Patent number: 6834336Abstract: A 32-bit instruction 50 is composed of a 4-bit format field 51, a 4-bit operation field 52, and two 12-bit operation fields 59 and 60. The 4-bit operation field 52 can only include (1) an operation code “cc” that indicates a branch operation which uses a stored value of the implicitly indicated constant register 36 as the branch address, or (2) a constant “const”. The content of the 4-bit operation field 52 is specified by a format code provided in the format field 51.Type: GrantFiled: May 24, 2002Date of Patent: December 21, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Shuichi Takayama, Nobuo Higaki
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Patent number: 6832307Abstract: A plurality of fold decoders are each coupled to a different set of successive entries within an instruction fetch buffer stack and check the contents of the successive entries for a variable number of variable-length instructions which may be folded. Folding information for each of the respective set of entries, identifying a number of instructions therein which may be folded (if any) and a size of each instruction which may be folded, is produced by the fold decoders and stored in the first entry of the set, then transmitted to the main decoder for use in folding instructions during decoding.Type: GrantFiled: July 19, 2001Date of Patent: December 14, 2004Assignee: STMicroelectronics, Inc.Inventor: Nicholas J. Richardson
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Patent number: 6826676Abstract: A programmable processing system includes a first processor for executing a first portion of an instruction, a second processor for executing a second portion of the instruction, where the second portion of the instruction is interpreted by the first processor as an extension to an immediate operand field included in the first portion of the instruction.Type: GrantFiled: November 19, 2001Date of Patent: November 30, 2004Assignee: Intel CorporationInventor: John A. Wishneusky
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Patent number: 6820189Abstract: A computation core for executing programmed instructions includes an execution block for performing digital signal processor operations in response to digital signal processor instructions and for performing microcontroller operations in response to microcontroller instructions, a register file for storing operands for and results of the digital signal processor operations and the microcontroller operations, and control logic for providing control signals to the execution block and the register file in response to the instructions. The digital signal processor instructions each have a first length and the microcontroller instructions each have a second length that is less than the first length.Type: GrantFiled: May 12, 2000Date of Patent: November 16, 2004Assignee: Analog Devices, Inc.Inventors: Marc Hoffman, John Edmondson, Jose Fridman