Decoding Instruction To Accommodate Variable Length Instruction Or Operand Patents (Class 712/210)
  • Patent number: 7793079
    Abstract: A method of expanding a conditional instruction having a plurality of operands within a pipeline processor is disclosed. The method identifies the conditional instruction prior to an issue stage and determines if the plurality of operands exceeds a predetermined threshold. The method expands the conditional instruction into a non-conditional instruction and a select instruction. The method further executes the non-conditional instruction and the select instruction in separate pipelines.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: September 7, 2010
    Assignee: QUALCOMM Incorporated
    Inventors: Serena Badran-Louca, Rodney Wayne Smith, Michael Scott McIlvaine
  • Patent number: 7793081
    Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: September 7, 2010
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Robert Kevin Montoye, Brett Olsson, John-David Wellman
  • Publication number: 20100199073
    Abstract: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.
    Type: Application
    Filed: October 15, 2009
    Publication date: August 5, 2010
    Inventors: Erdem Hokenek, Mayan Moudgill, Michael J. Schulte, C. John Glossner
  • Publication number: 20100146244
    Abstract: A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.
    Type: Application
    Filed: December 7, 2009
    Publication date: June 10, 2010
    Applicant: Panasonic Corporation
    Inventors: Takeshi Kishida, Masaitsu Nakajima
  • Patent number: 7734898
    Abstract: A data processing system uses a data processor instruction that forms an immediate value. The data processing instruction uses a first field as a portion of the immediate value. A second field of the data processing instruction determines a positional location of the portion of the immediate value within the immediate value. A bit value in a third field of the data processing instruction is used to determine a remainder of the immediate value.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: June 8, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventor: William C. Moyer
  • Publication number: 20100115240
    Abstract: In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.
    Type: Application
    Filed: November 5, 2008
    Publication date: May 6, 2010
    Inventors: Ohad Falik, Lihu Rappoport, Ron Gabor, Yulia Kurolap, Michael Mishaeli
  • Patent number: 7711926
    Abstract: A method, cache controller, and computer processor provide a parallel mapping system whereby a plurality of mappers processes several inputs simultaneously. The plurality of mappers are disposed in a pipelined processor upstream from a multiplexor. Mapping, tag comparison, and selection by the multiplexor all occur in a single pipeline stage. Data does not wait idly to be selected by the multiplexor. Instead, each instruction of a first instruction set is read in parallel into a corresponding one of the plurality of mappers. This parallel mapping system implementation reduces processor cycle time and results in improved processor efficiency.
    Type: Grant
    Filed: April 18, 2001
    Date of Patent: May 4, 2010
    Assignee: MIPS Technologies, Inc.
    Inventors: Ryan C. Kinter, David A. Courtright
  • Patent number: 7707393
    Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.
    Type: Grant
    Filed: May 7, 2007
    Date of Patent: April 27, 2010
    Assignee: Broadcom Corporation
    Inventor: Sophie Wilson
  • Patent number: 7689811
    Abstract: A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor (18) operable to perform data processing operations within parallel processing lanes on at least one source operand in response to a data processing instruction decoded by said instruction decoder (16); and said data processor being operable in response to said decoded instruction with generated constant and associated data value to expand at least a data portion (1210) of said associated data value, said expansion being performed in response to said instruction with generated constant and depending on a selected function, to generate a constant (1240), said generated constant (1240) forming one of said at least one source operands.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: March 30, 2010
    Assignee: ARM Limited
    Inventors: Wilco Dijkstra, Simon Andrew Ford, David James Seal
  • Patent number: 7676654
    Abstract: Methods and apparatus for accessing an extended register space associated with a processor are disclosed. In an example method, an instruction indicating a tag value is received. It is then determined whether information is stored in a first group of registers or a second group of registers based on a comparison of the tag value and an identifier value indicative of the second group of registers. The information is then accessed in the second group of registers in response to the tag value matching the identifier value.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: March 9, 2010
    Assignee: Intel Corporation
    Inventor: Ralph M Kling
  • Patent number: 7676651
    Abstract: The invention provides a code compression technology that is favorable for a micro controller or other embedded system, and for compressed codes, resulting from conversion of program codes into variable length codes, and grouped program codes, address conversion information for specifying the start address of each group and compressed code type information for specifying the code length of each compressed code contained in a group are stored in a memory, and by enabling a corresponding compressed code address to be calculated from a code address output by a CPU, code compression that is favorable for a micro controller or other embedded system is realized.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 9, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Hiromichi Yamada, Yuichi Abe, Yasuhiro Nakatsuka, Takanaga Yamazaki
  • Patent number: 7676652
    Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.
    Type: Grant
    Filed: August 27, 2003
    Date of Patent: March 9, 2010
    Assignee: ARM Limited
    Inventors: Hedley James Francis, Frederic Claude Marie Piry, Pierre Michel Broyer
  • Patent number: 7676653
    Abstract: The invention provides a decode unit for decoding instructions in a processor. The decode unit comprises opcode decoding logic, operand decoding logic, and a sixteen-bit input. The opcode decoding logic is operable to determine an opcode using five bits of the input and the operand decoding logic is operable to determine three four-bit operand elements from the remaining eleven bits of the input, the three operand elements each having one of twelve possible binary values. The operand decoding logic is operable to decode an encoded group of the eleven bits to determine a first part of each of the three operand elements, and to read verbatim a verbatim group of the eleven bits to determine a second part of each of the three operand elements.
    Type: Grant
    Filed: May 9, 2007
    Date of Patent: March 9, 2010
    Assignee: XMOS Limited
    Inventor: Michael David May
  • Patent number: 7668381
    Abstract: The decoding apparatus in the present invention includes a memory operable to hold encoded data representing one of a compressed sound and a compressed image, a memory read-out unit operable to sequentially read out the encoded data from said memory, a match determining circuit operable to determine whether or not data matching a specific bit sequence exists in the encoded data read out by said memory read-out unit, a deleting circuit operable to delete a part of the specific bit sequence from the encoded data read out from said memory, when said match determining circuit determines that the specific bit sequence exists, and a decoding circuit operable to decode the post-deletion encoded data.
    Type: Grant
    Filed: October 20, 2005
    Date of Patent: February 23, 2010
    Assignee: Panasonic Corporation
    Inventors: Masayuki Masumoto, Kazushi Kurata, Hideyo Tsuruta
  • Patent number: 7664934
    Abstract: A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.
    Type: Grant
    Filed: February 15, 2007
    Date of Patent: February 16, 2010
    Assignee: Panasonic Corporation
    Inventors: Takeshi Kishida, Masaitsu Nakajima
  • Patent number: 7664765
    Abstract: A new technique for accelerating the computational speed of a computer algorithm is provided. The inventive technique can be applied to an encryption algorithm, such as an RSA algorithm, for example. A method and system for effecting secure information communications utilizing an accelerated information encryption algorithm is also contemplated.
    Type: Grant
    Filed: July 12, 2006
    Date of Patent: February 16, 2010
    Assignee: Cipherflux, LLC
    Inventors: Jerzy Henryk Urbanik, Krzysztof Ryszard Kalita, Przemyslaw Bartlomiej Bezeg
  • Patent number: 7664935
    Abstract: A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: February 16, 2010
    Inventors: Brett Coon, Yoshiyuki Miyayama, Le Trong Nguyen, Johannes Wang
  • Patent number: 7647478
    Abstract: An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of store checking at the instruction level. The apparatus includes fetch logic, and translation logic. The fetch logic receives an extended instruction. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies that store checking be suppressed for the extended instruction. The extended prefix tag is an otherwise architectural opcode within an existing instruction set. The fetch logic precludes store checking for pending store events associated with the extended instruction. The translation logic is coupled to the fetch logic. The translation logic translates the extended instruction into a micro instruction sequence that sequence directs the microprocessor to exclude store checking during execution of a prescribed operation.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: January 12, 2010
    Assignee: IP First, LLC
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks
  • Patent number: 7647479
    Abstract: An apparatus and method are provided for extending a microprocessor instruction set to specify non-temporal memory references at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into a micro instruction sequence. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies a non-temporal access for a memory reference prescribed by the extended instruction, where the non-temporal access cannot be specified by an existing instruction from an existing instruction set. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within the existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the micro instruction sequence, and executes the non-temporal access to perform the memory reference.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: January 12, 2010
    Assignee: IP First, LLC
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks
  • Patent number: 7640417
    Abstract: Methods and apparatus relating to speculatively decoding instruction lengths in order to increase instruction throughput are described. In an embodiment, instructions are speculatively decoded within a pipelined microprocessor architecture such that up to four instruction lengths may be decoded within a maximum of two processor clock cycles. Other embodiments are also disclosed.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: December 29, 2009
    Assignee: Intel Corporation
    Inventor: Venkateswara Rao Madduri
  • Patent number: 7594098
    Abstract: An embodiment of the invention relates to a process for compression of executable code by a microprocessor, comprising decomposing the executable code into words; dividing the executable code into instruction lines; compressing each word of each line in the form of a compressed word of variable length, the compressed words of a line being combined into a line of compressed words; and constituting an addressing table localizing each of the lines of compressed words in a block of lines compressed words and comprising one input per group of lines of compressed words, each input (j) specifying the position of a first line of compressed words in the block, and the respective lengths of the lines of compressed words of group, except for a last line of compressed words of the group, whereof the length is determined by means of the position of a first line of compressed words of a following group.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: September 22, 2009
    Assignee: STMicroelectronics, SA
    Inventor: Didier Fuin
  • Patent number: 7587535
    Abstract: When data is transferred to an access destination in a different endian format, a transfer start address is aligned based on a transfer bus width, and a transfer size is adjusted according to the transfer bus width and a transfer address. Thus, it becomes possible to perform burst transfer in the access destination. Accordingly, in the case where burst transfer to an access destination in a different endian format is performed with a smaller data width than a transfer bus width, an inconvenience where burst transfer can not be performed because an address is converted and data access is no longer an ascending order access can be prevented.
    Type: Grant
    Filed: April 20, 2007
    Date of Patent: September 8, 2009
    Assignee: Panasonic Corporation
    Inventor: Takatsugu Sawai
  • Patent number: 7581084
    Abstract: A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.
    Type: Grant
    Filed: May 21, 2004
    Date of Patent: August 25, 2009
    Assignee: Nintendo Co., Ltd.
    Inventors: Yu-Chung C. Liao, Peter A. Sandon, Howard Cheng
  • Patent number: 7581083
    Abstract: As shown in FIG. 1, an operation-processing device of the present invention comprises a register array (11) having plural registers for holding an arbitrary value based on a write address Aw and a write control signal Sw and outputting this value based on a read address Ar, an ALU (12) for performing operations on this value, a decoder (13) for decoding an operation instruction from an operation program AP for operating this ALU (12), and an instruction-execution-controlling portion (50) for controlling the register array (11) and the ALU (12) in order to execute this operation instruction, wherein this instruction-execution-controlling portion (50) selects one of the registers based on the operation instruction and performs register-to-register addressing processing that, based on a value held by this selected register, selects another register.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: August 25, 2009
    Assignee: Sony Corporation
    Inventor: Tomohisa Shiga
  • Patent number: 7565510
    Abstract: A load/store unit includes a Top register for storing a value retained before loading to a load destination register and a saved register capable of storing data retained to the Top register. When an unaligned instruction evaluation unit determines that a load instruction issued from a instruction decode unit is an unaligned instruction, data stored to the Top register are stored to the saved register in order to make the Top register available to subsequent load instructions issued from the instruction decode unit.
    Type: Grant
    Filed: April 25, 2006
    Date of Patent: July 21, 2009
    Assignee: NEC Electronics Corporation
    Inventor: Shuichi Kunie
  • Patent number: 7543134
    Abstract: An apparatus and method for extending a microprocessor instruction set is provided. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended instruction tag. The extended prefix directs that an architectural extension be employed in the execution of an operation prescribed by the extended instruction. The extended instruction tag indicates the extended instruction prefix, where the extended instruction tag is an otherwise architecturally specified opcode within the microprocessor instruction set. The extended execution logic is coupled to the translation logic, and receives the corresponding micro instructions, and employs the architectural extension in the execution of the operation.
    Type: Grant
    Filed: December 1, 2004
    Date of Patent: June 2, 2009
    Assignee: IP-First, LLC
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks
  • Patent number: 7529912
    Abstract: Apparatus and method are provided for extending a microprocessor instruction set to allow for instruction-level specification of floating point format to be employed during execution of an associated floating point operation. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix specifies the floating point format. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and executes the associated floating point operation according to the floating point format specified by the extended prefix.
    Type: Grant
    Filed: March 18, 2005
    Date of Patent: May 5, 2009
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks
  • Patent number: 7526633
    Abstract: Techniques for processing transmissions in a communications (e.g., CDMA) system. The method and system encode and process instructions of mixed lengths (e.g., 16 bits and 32 bits) and instruction packets including instructions of mixed lengths. This includes encoding a plurality of instructions of a first length and a plurality of instructions of a second length. The method and system encode a header having at least one instruction length bit. The instruction bit distinguishes between instructions of the first length and instructions of the second length for an associated DSP to process in a mixed stream. The method and system distinguish between the instructions of the first length and the instructions of the second length according to the contents of the instruction length bits. The header further includes bits for distinguishing between instructions of varying lengths in an instruction packet.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: April 28, 2009
    Assignee: QUALCOMM Incorporated
    Inventors: Lucian Codrescu, Erich Plondke, Muhammad Ahmed, William C. Anderson
  • Patent number: 7523230
    Abstract: The present invention includes a method and device for controlling the data length of read and write operations performed on a memory device. The method includes determining a first number of channels available to a memory controller operatively coupled to the memory device; determining a second number representative of the number of populated channels; calculating a burst length based on the first and second numbers; and programming the memory controller to use the burst length as the data length of read and write operations performed on the memory device.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: April 21, 2009
    Inventors: James M. Dodd, Brian P. Johnson, Jay C. Wells, John B. Halbert
  • Patent number: 7523294
    Abstract: The present invention discloses a method for compressing instruction codes. This method comprises: compressing an instruction block including a plurality of instructions according to Huffman-Encoding technique; determining whether it's necessary to insert no-operation (nop) instructions among the plurality of compressed instructions according to a compression ratio, so as to generate a plurality of new instruction blocks complying with the compression ratio; if it's necessary to insert nop instructions, inserting nop instructions among the plurality of compressed instructions to form the plurality of new instruction blocks; and repeating the above-mentioned steps until no nop instructions have to be inserted.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: April 21, 2009
    Assignee: Realtek Semiconductor Corp.
    Inventor: Yen-Ju Lu
  • Patent number: 7502911
    Abstract: A digital signal processor uses a variable length instruction set. The variable length instructions may be stored in adjacent locations within memory space. The beginning and ending of instructions may, but are not required to, occur across memory word boundaries. Preferably, the variable length instructions contain variable numbers of instruction fragments. Each instruction fragment causes a particular operation (or operations) to be performed, thereby allowing multiple operations to be performed during each clock cycle. This reduces the total number of clock cycles necessary to perform a task.
    Type: Grant
    Filed: September 25, 2006
    Date of Patent: March 10, 2009
    Assignee: QUALCOMM Incorporated
    Inventors: Gilbert C. Sih, Qiuzhen Zou, Jian Lin
  • Publication number: 20090055629
    Abstract: An instruction length determination device includes an instruction input unit having a memory space to store a plurality of N-bit data; an instruction fetch unit which fetches the plurality of N-bit data from the instruction input unit; an instruction length determination logic which compares concatenate bits of a first N-bit data with a predetermined value for determination of an instruction length; and an instruction concatenate unit which selectively concatenates a number of successive N-bit data based on the determination. The instruction length determination logic determines that the first N-bit data is a complete instruction when the concatenate bit of the first N-bit data is not equal to the predetermined value. Otherwise, the instruction length determination logic determines that a complete instruction is formed of last N-bit data finally fetched and all N-bit previously reserved.
    Type: Application
    Filed: August 19, 2008
    Publication date: February 26, 2009
    Applicant: Sunplus Technology Co., Ltd.
    Inventor: Lian Sung
  • Patent number: 7493470
    Abstract: Apparatus and methods for real-time control using a data processor. In one aspect, the invention comprises an improved processor having one or more extension instructions (and associated supporting pipeline hardware) which are specially adapted for use in a real-time control algorithm running on the processor. In one exemplary embodiment, the processor is a 32-bit pipelined RISC device having custom multiply (CMUL) and multiply-accumulate (CMAC) instructions added to the extension instruction set to optimize algorithm performance in real-time linear time-invariant (LTI) applications. Specialized extension hardware, and methods for generating a processor design adapted for real-time control applications are also disclosed.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: February 17, 2009
    Assignee: ARC International, PLC
    Inventors: Rene Cumplido, Roger Goodall, Simon Jones
  • Publication number: 20090043989
    Abstract: A processor 2 is provided with the ability to execute program instructions in the form of Java bytecodes including a dedicated null checking instruction. The null checking instruction reads the top of stack value, compares this with a null value and jumps to an exception handling routine if the top of stack value equals the null value, otherwise the next program instruction is executed.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 12, 2009
    Applicant: ARM LIMITED
    Inventor: Rodolph Gerard Jacques Ascanio Jean-Denis Perfetta
  • Publication number: 20090043990
    Abstract: A digital processor and method of operation utilize an alias address space to implement variable length instruction encoding on a legacy processor. The method includes storing instructions of a code sequence in memory; generating instruction addresses of the code sequence; automatically switching between a first operating mode and a second operating mode in response to a transition in instruction addresses between a first address space and a second address space, wherein addresses in the first and second address spaces access a common memory space; in the first operating mode, accessing instructions in the first address space; in the second operating mode, accessing instructions in the second address space; and executing the accessed instructions of the code sequence. Instructions of different instruction lengths may be utilized in the first and second operating modes.
    Type: Application
    Filed: August 8, 2007
    Publication date: February 12, 2009
    Applicant: Analog Devices, Inc.
    Inventors: Abhijit Giri, Rajiv Nadig
  • Patent number: 7490118
    Abstract: Expanding the capacity of a fixed digital field using a unique number calculated from the digital field, such as an error code. Expansion is possible by calculating a new error code using a different algorithm. A recipient, upon not detecting the error code from the original algorithm, checks for the new error code before indicating an error. The presence of the new error code acts like an extra bit to give an entirely new set of numbers for the digital field, thus doubling the command set. In another aspect of the invention, fill bits between transmission packets are used to indicate further data, and are included in calculating the new error code.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: February 10, 2009
    Assignee: Liontech Trains LLC
    Inventors: Louis G. Kovach, II, Neil Percibal Young
  • Publication number: 20090019263
    Abstract: A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be associated with a plurality of variable length instructions, which are to be executed by the processing unit. The length decode unit may perform a length decode operation for each of the plurality of instruction bytes. For each instruction byte, the length decode unit may estimate the instruction length of a current variable length instruction associated with a current instruction byte. Furthermore, during the length decode operation, for each instruction byte, the length decode unit may estimate the start of a next variable length instruction based on the estimated instruction length of the current variable length instruction, and store a first pointer to the estimated start of the next variable length instruction.
    Type: Application
    Filed: July 10, 2007
    Publication date: January 15, 2009
    Inventors: Gene W. Shen, Sean Lie
  • Publication number: 20080307204
    Abstract: In one embodiment, a rotator, a mask generator, and circuitry configured to mask the rotated operand output by the rotator with the output mask generated by the mask generator perform a shift operation. Coupled to receive the input operand and the shift count, the rotator is configured to rotate the input operand by the shift count. Coupled to receive the shift count and the shift direction, the mask generator is configured to generate an output mask by decoding a most significant bit (MSB) field of the shift count to generate a first mask, decoding a least significant bit (LSB) field of the shift count to generate a second mask, logically ANDing the bits of the second mask with the corresponding bit of the first mask and logically ORing the result with an adjacent bit of the first mask that is selected responsive to the shift direction.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Inventor: Honkai Tam
  • Publication number: 20080307203
    Abstract: A method, system, and computer program product are provided for identifying instructions to obtain representative traces. A phase instruction budget is calculated for each phase in a set of phases. The phase instruction budget is based on a weight associated with each phase and a global instruction budget. A starting index and an ending index are identified for instructions within a set of intervals in each phase in order to meet the phase instruction budget for that phase, thereby forming a set of interval indices. A determination is made as to whether the instructions within the set of interval indices meet the global instruction budget. Responsive to the global instruction budget being met, the set of interval indices are output as collection points for the representative traces.
    Type: Application
    Filed: June 5, 2007
    Publication date: December 11, 2008
    Inventors: Robert H. Bell, JR., Wen-Tzer T. Chen, Richard J. Eickemeyer, Venkat R. Indukuru, Pattabi M. Seshadri, Madhavi G. Valluri
  • Patent number: 7454594
    Abstract: A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and permit software pipelining between arithmetic operations performed in parallel by a SIMD arithmetic unit. A selector for adding an operation for interchanging multiple outputs of a SIMD arithmetic unit is added to a data path. A register file is divided in accordance with the output bit fields of the SIMD arithmetic unit. A means of specifying multiple registers as a SIMD instruction's output operand is added. Therefore, part of the output results of arithmetic operations performed in parallel by the SIMD arithmetic unit can be stored in a register providing the input for another arithmetic operation. Software pipelining is rendered achievable in this manner.
    Type: Grant
    Filed: December 17, 2002
    Date of Patent: November 18, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Yuki Kondoh
  • Patent number: 7447871
    Abstract: A data processing apparatus 2 is provided which is responsive to data access instructions to perform data access operations. These data access instructions have a first form utilizing a 12-bit offset field but with a fixed addressing mode and a second form utilizing a shorter 8-bit offset field but with an addressing mode specified within a manipulation mode control field of the data access instruction.
    Type: Grant
    Filed: February 7, 2007
    Date of Patent: November 4, 2008
    Assignee: ARM Limited
    Inventors: David James Seal, Vladimir Vasekin
  • Publication number: 20080250229
    Abstract: In a processor executing instructions from a variable-length instruction set, a preload instruction is operative to retrieve from memory a data block corresponding to an instruction cache line, pre-decode instructions from a variable-length instruction set in the data block, and load the instructions and pre-decode information into the instruction cache. An instruction execution unit indicates to a pre-decoder the position within the data block of a first valid instruction. The pre-decoder successively determines the length of each instruction and hence the instruction boundaries. An instruction cache line offset indicator that identifies the position of the first valid instruction may be generated and provided to the pre-decoder in a variety of ways.
    Type: Application
    Filed: April 4, 2007
    Publication date: October 9, 2008
    Applicant: QUALCOMM INCORPORATED
    Inventors: Brian Michael Stempel, Thomas Andrew Sartorius, Rodney Wayne Smith
  • Publication number: 20080229075
    Abstract: A set of low-cost microcontroller extensions facilitates Digital Signal Processing (DSP) applications by incorporating a Multiply-Accumulate (MAC) unit in a Central Processing Unit (CPU) of the microcontroller which is responsive to the extensions.
    Type: Application
    Filed: March 16, 2007
    Publication date: September 18, 2008
    Inventors: Benjamin Francis Froemming, Emil Lambrache
  • Patent number: 7424597
    Abstract: Parallel table lookups are implemented using variable Mux instructions to reorder data. Table data can be represented in a “table” register, while the desired ordering can be represented in an “Index” register. A direct variable Mux instruction can specify the table register and the index register as arguments, along with a result register. The instruction writes at least some of the data from the table register into the result register as specified in the index register. If the entire table cannot fit within a single register, entries can be divided between two or more table registers. An indirect variable Mux instruction can specify both a table-register-select register and a subword-location-select register. Both the direct and indirect Mux instructions can be used with entry data that is divided in accordance with significance between registers. In that case, plural Mux instructions are used with UnPack instructions that concatenate portions of the table entries.
    Type: Grant
    Filed: March 31, 2003
    Date of Patent: September 9, 2008
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Ruby B. Lee, Dale Morris
  • Patent number: 7421566
    Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.
    Type: Grant
    Filed: June 2, 2006
    Date of Patent: September 2, 2008
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Robert Kevin Montoye, Brett Olsson, John-David Wellman
  • Publication number: 20080162882
    Abstract: Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on multiple data elements stored registers in a register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results, wherein the execution unit is capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions.
    Type: Application
    Filed: July 27, 2007
    Publication date: July 3, 2008
    Applicant: MICROUNITY SYSTEMS
    Inventors: Craig Hansen, John Moussouris, Alexia Massalin
  • Patent number: 7380103
    Abstract: A microprocessor apparatus and method are provided, for selectively controlling write back of a result. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has an extended prefix and an extended prefix tag. The extended prefix precludes write back of the result, where the result is that which is produced by executing an operation prescribed by said extended instruction, and wherein the result would otherwise be written back into a destination register. The extended prefix tag indicates the extended prefix, where the extended prefix tag is an otherwise architecturally specified opcode within an instruction set for a microprocessor. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and executes the operation to generate the result, and precludes write back of the result.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: May 27, 2008
    Assignee: iP-First, LLC
    Inventors: G. Glenn Henry, Rodney E. Hooker, Terry Parks
  • Patent number: 7376814
    Abstract: Variable length instructions are formed for execution in a processing system. Each instruction includes a parameter portion having one or more of predetermined types of parameters and an opcode portion. The opcode portion specifies an operation to be performed, the number of parameters in the instruction, and definitive characteristics of the parameters. The parameters may represent data which is compressible, thereby enabling the size of parameters in an instruction to be reduced.
    Type: Grant
    Filed: September 7, 1999
    Date of Patent: May 20, 2008
    Assignee: NXP B.V.
    Inventors: Winthrop L. Saville, Kevin Ross
  • Patent number: RE40498
    Abstract: The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: September 9, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masato Suzuki, Hiroshi Kamiyama, Shinya Miyaji
  • Patent number: RE40883
    Abstract: A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: August 25, 2009
    Assignee: Altera Corporation
    Inventors: Gerald George Pechanek, Edwin Franklin Barry