Decoding Instruction To Accommodate Variable Length Instruction Or Operand Patents (Class 712/210)
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Patent number: 8195432Abstract: A media capture system, method, and computer program product are provided for assessing processing capabilities utilizing cascaded memories. In use, media data is captured from a system in accordance with predetermined criteria. Additionally, the media data is stored in a plurality of cascaded memories separate from the system. Further, the media data is used for assessing media processing capabilities of the system, based on the predetermined criteria.Type: GrantFiled: November 19, 2008Date of Patent: June 5, 2012Assignee: NVIDIA CorporationInventors: William S. Herz, Jihua Yu, Hao Tang
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Patent number: 8185725Abstract: In a processor executing instructions in at least a first instruction set execution mode having a first minimum instruction length and a second instruction set execution mode having a smaller, second minimum instruction length, line and counter index addresses are formed that access every counter in a branch history table (BHT), and reduce the number of index address bits that are multiplexed based on the current instruction set execution mode. In one embodiment, counters within a BHT line are arranged and indexed in such a manner that half of the BHT can be powered down for each access in one instruction set execution mode.Type: GrantFiled: November 5, 2009Date of Patent: May 22, 2012Assignee: QUALCOMM IncorporatedInventors: Brian Michael Stempel, Rodney Wayne Smith
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Patent number: 8179540Abstract: An image forming apparatus is provided that holds counter information obtained by integrating a consumption of a consumable that depends on usage of service provided by the image forming apparatus. A log corresponding to the usage of the service is set in job log information with a synchronization flag set off. The log in the job log information, for which the synchronization flag is set off, is set on. The counter information and the job log information are output after the synchronization flag for the log having the synchronization flag set off has been set on.Type: GrantFiled: October 29, 2008Date of Patent: May 15, 2012Assignee: Canon Kabushiki KaishaInventors: Junichi Hiruma, Nobuyuki Tonegawa
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Publication number: 20120110307Abstract: A compressed instruction processing device has: a compressed instruction expanding circuit which expands a compressed instruction code that include a difference code between an instruction code being a compression object and a reference instruction code and which outputs an expanded instruction code; an instruction buffer storing the instruction code expanded by the compressed instruction expanding circuit; and an execution section executing the instruction code expanded by the compressed instruction expanding circuit, wherein the compressed instruction expanding circuit outputs the expanded instruction code by inputting the instruction code in the instruction buffer as the reference instruction code and adding the reference instruction code and the difference code in the compressed instruction code.Type: ApplicationFiled: August 15, 2011Publication date: May 3, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Masayuki TSUJI
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Patent number: 8161269Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.Type: GrantFiled: March 24, 2011Date of Patent: April 17, 2012Assignee: Intel CorporationInventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
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Publication number: 20120079247Abstract: A processor includes a first and second execution unit each of which is arranged to execute multiply instructions of a first type upon fixed point operands and to execute multiply instructions of a second type upon floating point operands. A register file of the processor stores operands in registers that are each addressable by instructions for performing the first and second types of operations. An instruction decode unit is responsive to the at least one multiply instruction of the first type and the at least one multiply instruction of the second type to at the same time enable a first data path between the first set of registers and the first execution unit and to enable a second data path between a second set of registers and the second execution unit.Type: ApplicationFiled: September 15, 2011Publication date: March 29, 2012Inventors: Timothy D. Anderson, Duc Quang Bui, Eric Biscondi, Shriram D. Moharil, Mujibur Rahman, Soujanya Narnur, Peter Richard Dent, Ashish Rai Shrivastava
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Patent number: 8131978Abstract: An original first instruction word (I1) to an original third instruction word (I3) include a bit field (L11) and a bit field (L12) to a bit field (L31) and a bit field (L32). An information word (IW) includes a set of some of bit fields belonging to a plurality of instruction words executed in the same cycle, which are the bit field (L12) of the original first instruction word (I1) to the bit field (L32) of the original third instruction word (I3). An instruction decoder (103) of a processor (100) decomposes the information word (IW) and restores the arrangements of the original first instruction word (I1) to the original third instruction word (I3) by combining the bit field (L11) to the bit field (L31) to the bit field (L12) to the bit field (L32). This can reduce the amount of memory consumption without degrading the instruction execution performance.Type: GrantFiled: June 15, 2007Date of Patent: March 6, 2012Assignee: NEC CorporationInventor: Shorin Kyo
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Patent number: 8127117Abstract: A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined disparate source register units from a register file structure is received within a processing unit. The instruction is then executed to combine corresponding half word units from the source register units and to input the half word units into respective portions of a resulting destination register unit. During the execution of the instruction, the predetermined source register units are identified and corresponding most significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective most significant portion of a resulting destination register unit.Type: GrantFiled: May 10, 2006Date of Patent: February 28, 2012Assignee: QUALCOMM IncorporatedInventors: Mao Zeng, Lucian Codrescu
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Patent number: 8028153Abstract: A circuit arrangement and method support data dependent instruction decoding, whereby instructions are decoded, in part, using decode data that is stored in operand registers identified by such instructions. An instruction may include an opcode and at least one operand that identifies a register. During execution of the instruction, the instruction is first decoded using the opcode, and then decode data stored in the operand register is retrieved and used to further decode the instruction, e.g., to select from among a plurality of operations or instruction types associated with the same opcode.Type: GrantFiled: August 14, 2008Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: Mark J Hickey, Adam J Muff, Matthew R Tubbs, Charles D Wait
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Publication number: 20110219214Abstract: A processor. The processor includes a first register for storing a first packed data, a decoder, and a functional unit. The decoder has a control signal input. The control signal input is for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation. The second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder and the register. The functional unit is for performing the pack operation and the unpack operation using the first packed data. The processor also supports a move operation.Type: ApplicationFiled: May 16, 2011Publication date: September 8, 2011Inventors: Alexander Peleg, Yaakov Yaari, Millind Mittal, Larry M. Mennemeier, Benny Eitan
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Patent number: 8006071Abstract: Methods and apparatus are provided for optimizing a processor core. Common processor subcircuitry is used to perform calculations for various types of instructions, including branch and non-branch instructions. Increasing the commonality of calculations across different instruction types allows branch instructions to jump to byte aligned memory address even if supported instructions are multi-byte or word aligned.Type: GrantFiled: March 31, 2004Date of Patent: August 23, 2011Assignee: Altera CorporationInventor: James Loran Ball
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Publication number: 20110173418Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.Type: ApplicationFiled: March 24, 2011Publication date: July 14, 2011Inventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
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Patent number: 7979676Abstract: A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.Type: GrantFiled: December 7, 2009Date of Patent: July 12, 2011Assignee: Panasonic CorporationInventors: Takeshi Kishida, Masaitsu Nakajima
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Patent number: 7966476Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.Type: GrantFiled: February 28, 2008Date of Patent: June 21, 2011Assignee: Intel CorporationInventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
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Patent number: 7962725Abstract: A pre-decoder in a variable instruction length processor indicates properties of instructions in pre-decode bits stored in an instruction cache with the instructions. When all the encodings of pre-decode bits associate with one length instruction are defined, a property of an instruction of that length may be indicated by altering the instruction to emulate an instruction of a different length, and encoding the property in the pre-decode bits associated with instructions of the different length. One example of a property that may be so indicated is an undefined instruction.Type: GrantFiled: May 4, 2006Date of Patent: June 14, 2011Assignee: QUALCOMM IncorporatedInventors: Rodney Wayne Smith, Brian Michael Stempel
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Patent number: 7953955Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.Type: GrantFiled: December 14, 2010Date of Patent: May 31, 2011Assignee: Altera Corporation.Inventors: Sergei Yurievich Larin, Gerald George Pechanek, Thomas M. Conte
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Patent number: 7945605Abstract: A new technique for accelerating the computational speed of a computer algorithm is provided. The inventive technique can be applied to video compression/decompression algorithms, optical character recognition algorithms, and digital camera zooming applications.Type: GrantFiled: December 28, 2009Date of Patent: May 17, 2011Assignee: Cipherflux, LLCInventors: Jerzy Henryk Urbanik, Krzysztof Ryszard Kalita, Przemyslaw Bartlomiej Bezeg
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Publication number: 20110083001Abstract: A systematic approach to architecture and design of the instruction fetch mechanisms and instruction set architectures in embedded processors is described. This systematic approach allows a relaxing of certain restrictions normally imposed by a fixed-size instruction set architecture (ISA) on design and development of an embedded system. The approach also guarantees highly efficient usage of the available instruction storage which is only bounded by the actual information contents of an application or its entropy. The result of this efficiency increase is a general reduction of the storage requirements, or a compression, of the instruction segment of the original application. An additional feature of this system is the full decoupling of the ISA from the core architecture. This decoupling allows usage of a variable length encoding for any size of the ISA without impacting the physical instruction memory organization or layout and branching mechanism as well as tuning of the execution core to the application.Type: ApplicationFiled: December 14, 2010Publication date: April 7, 2011Applicant: Altera CorporationInventors: Sergei Yurievich Larin, Gerald George Pechanek, Thomas M. Conte
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Patent number: 7917734Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.Type: GrantFiled: June 30, 2003Date of Patent: March 29, 2011Assignee: Intel CorporationInventors: James S. Coke, Peter J. Ruscito, Masood Tahir, David B. Jackson, Ves A. Naydenov, Scott D. Rodgers, Bret L. Toll, Frank Binns
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Patent number: 7908463Abstract: An extraction and decode mechanism for acquiring and processing instructions and the corresponding constant(s) embedded within the instructions. The extraction and decode mechanism may be included within a processing unit, and may comprise an instruction decode unit and at least one constant steer network. During operation, the instruction decode unit may obtain and decode instructions which are to be executed by the processing unit. For each instruction, the instruction decode unit may also determine the location of one or more constants embedded within the instruction. The constant steer network may receive the location information from the instruction decode unit. While the instruction decode unit decodes the instruction, the constant steer network may obtain the constant(s) embedded within the instruction based on the location information and store the constant(s). The constant(s) embedded within the instruction may be immediate or displacement (imm/disp) constant(s).Type: GrantFiled: June 26, 2007Date of Patent: March 15, 2011Assignee: GLOBALFOUNDRIES Inc.Inventor: Sean Lie
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Patent number: 7895418Abstract: There is disclosed an operand queue for use in a floating point unit. The floating point unit comprises floating point processing units for executing floating point instructions that write operands to an external memory and for executing floating point instructions that read operands from the external memory. The floating point also comprises an operand queue for storing a plurality of operands associated with one or more operations being processed in the floating point unit. The operand queue stores a first operand being written to an external memory by a floating point write instruction executed by a first one of the plurality of floating point processing units and supplies the first operand to a floating point read instruction executed by a second one of the plurality of floating point processing units subsequent to the execution of the floating point write instruction.Type: GrantFiled: November 28, 2005Date of Patent: February 22, 2011Assignee: National Semiconductor CorporationInventor: Daniel W. Green
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Patent number: 7895414Abstract: An instruction length determination device includes an instruction input unit having a memory space to store a plurality of N-bit data; an instruction fetch unit which fetches the plurality of N-bit data from the instruction input unit; an instruction length determination logic which compares concatenate bits of a first N-bit data with a predetermined value for determination of an instruction length; and an instruction concatenate unit which selectively concatenates a number of successive N-bit data based on the determination. The instruction length determination logic determines that the first N-bit data is a complete instruction when the concatenate bit of the first N-bit data is not equal to the predetermined value. Otherwise, the instruction length determination logic determines that a complete instruction is formed of last N-bit data finally fetched and all N-bit previously reserved.Type: GrantFiled: August 19, 2008Date of Patent: February 22, 2011Assignee: Sunplus Technology Co., Ltd.Inventor: Lian Sung
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Patent number: 7882325Abstract: A single micro-instruction to perform either an N-bit or a 2N-bit load is provided. A microprocessor having an N-bit load port performs either an N-bit load or a 2N-bit load in a single cycle with the same micro-instruction being used for both the N-bit and the 2N-bit load.Type: GrantFiled: December 21, 2007Date of Patent: February 1, 2011Assignee: Intel CorporationInventors: Zeev Sperber, Robert Valentine, Ehud Cohen, Doron Orenstien, Benny Eitan
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Patent number: 7865699Abstract: This invention pertains to apparatus, method and a computer program stored on a computer readable medium. The computer program includes instructions for use with an instruction unit having a code page, and has computer program code for partitioning the code page into at least two sections for storing in a first section thereof a plurality of instruction words and, in association with at least one instruction word, for storing in a second section thereof an extension to each instruction word in the first section. The computer program further includes computer program code for setting a state of at least one page table entry bit for indicating, on a code page by code page basis, whether the code page is partitioned into the first and second sections for storing instruction words and their extensions, or whether the code page is comprised instead of a single section storing only instruction words.Type: GrantFiled: October 31, 2007Date of Patent: January 4, 2011Assignee: International Business Machines CorporationInventors: Erik R Altman, Michael Gschwind, David A. Luick, Daniel A. Prener, Jude A. Rivers, Sumedh W. Sathaye, John-David Wellman
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Patent number: 7844800Abstract: A processor 2 utilising register renaming executes program instructions requiring a large number of architectural register specifiers to be renamed by dividing the renaming tasks into an initial set and a remaining set. The initial set are performed first and the results passed via a main channel 32 for further processing. The remaining set are performed in sequence with the results being passed via a background channel 34 for further processing. This technique is particularly useful for performing renaming operations for load/store multiple LDM instructions.Type: GrantFiled: August 21, 2007Date of Patent: November 30, 2010Assignee: ARM LimitedInventors: Melanie Emanuelle Lucie Vincent, Florent Begon, Cedric Denis Robert Airaud, Norbert Bernard Eugene Lataille
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Patent number: 7844654Abstract: An arithmetic unit of arbitrary-precision, including: a main processing unit, which splits up the first and the second arbitrary-precision values into N-bit (where N is a natural number) operands respectively in the-least-significant-bit-first order for computing with the arbitrary-precision data and consecutively outputting a series of pairs of the first and second N-bit operands; and an N-bit arithmetic unit, which performs computing with the N-bit operands, while requesting the main processing unit to feed the next N-bit operands each time the computation completes. The carry bit generated by the operation is fed to the next N-bit operation.Type: GrantFiled: August 30, 2005Date of Patent: November 30, 2010Assignee: Seiko Epson CorporationInventor: Nobuo Karaki
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Publication number: 20100299503Abstract: An apparatus in a microprocessor that has an instruction set architecture in which instructions may include a length-modifying prefix used to select an address/operand size other than a default address/operand size, wherein the apparatus marks the start byte and the end byte of each instruction in a stream of instruction bytes. Decode logic decodes each instruction byte of a predetermined number of instruction bytes to determine whether the instruction byte specifies a length-modifying prefix and generates a start mark and an end mark for each of the instruction bytes based on an address/operand size. Operand/address size logic provides the default operand/address size to the decode logic to use to generate the start and end marks during a first clock cycle during which the decode logic decodes the predetermined number of instruction bytes.Type: ApplicationFiled: October 1, 2009Publication date: November 25, 2010Applicant: VIA Technologies, Inc.Inventors: Thomas C. McDonald, John L. Duncan
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Patent number: 7836278Abstract: A method and apparatus are contemplated for increasing the number of available instructions in an instruction set architecture. The new instructions extend the number of general-purpose registers and include three or more operands. A combination of an escape code field, an opcode field, an operation configuration field and an operation size field determines a unique new instruction operation. A source operand extension field includes bits to be combined with other fields in order to extend the number of source operand values for general-purpose registers.Type: GrantFiled: December 12, 2007Date of Patent: November 16, 2010Assignee: Advanced Micro Devices, Inc.Inventors: Ranganathan Sudhakar, Michael Frank, Debjit Dassarma
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Publication number: 20100287359Abstract: A method and apparatus provide means for compressing instruction code size. An Instruction Set Architecture (ISA) encodes instructions compact, usual or extended bit lengths. Commonly used instructions are encoded having both compact and usual bit lengths, with compact or usual bit length instructions chosen based on power, performance or code size requirements. Instructions of the ISA can be used in both privileged and non-privileged operating modes of a microprocessor. The instruction encodings can be used interchangeably in software applications. Instructions from the ISA may be executed on any programmable device enabled for the ISA, including a single instruction set architecture processor or a multi-instruction set architecture processor.Type: ApplicationFiled: May 11, 2009Publication date: November 11, 2010Applicant: MIPS Technologies, Inc.Inventor: Erik K. Norden
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Publication number: 20100268919Abstract: A register file, in a processor, includes a first plurality of registers of a first size, n-bits. A decoder uses a mapping that divides the register file into a second plurality M of registers having a second size. Each of the registers having the second size is assigned a different name in a continuous name space. Each register of the second size includes a plurality N of registers of the first size, n-bits. Each register in the plurality N of registers is assigned the same name as the register of the second size that includes that plurality. State information is maintained in the register file for each n-bit register. The dependence of an instruction on other instructions is detected through the continuous name space. The state information allows the processor to determine when the information in any portion, or all, of a register is valid.Type: ApplicationFiled: April 20, 2009Publication date: October 21, 2010Inventors: Shailender Chaudhry, Marc Tremblay
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Patent number: 7818542Abstract: A mechanism for superscalar decode of variable length instructions. The decode mechanism may be included within a processing unit, and may comprise a length decode unit. The length decode unit may obtain a plurality of instruction bytes. The instruction bytes may be associated with a plurality of variable length instructions, which are to be executed by the processing unit. The length decode unit may perform a length decode operation for each of the plurality of instruction bytes. For each instruction byte, the length decode unit may estimate the instruction length of a current variable length instruction associated with a current instruction byte. Furthermore, during the length decode operation, for each instruction byte, the length decode unit may estimate the start of a next variable length instruction based on the estimated instruction length of the current variable length instruction, and store a first pointer to the estimated start of the next variable length instruction.Type: GrantFiled: July 10, 2007Date of Patent: October 19, 2010Assignee: GLOBALFOUNDRIES Inc.Inventors: Gene W. Shen, Sean Lie
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Patent number: 7818543Abstract: A mechanism for superscalar decode of variable length instructions. A length decode unit may obtain a plurality of instruction bytes based on a scan window of a predetermined size. The instruction bytes may be associated with a plurality of variable length instructions, which are scheduled to be executed by a processing unit. The length decode unit may, for each instruction byte, estimate the start of a next variable length instruction following a current variable length instruction, and store a first pointer. A pre-pick unit may, for each instruction byte, use the first pointer to estimate the start of a subsequent variable length instruction following the next variable length instruction within the scan window, and store a second pointer. A pick unit may use a start pointer and related first and second pointers to determine the actual start of the variable length instructions within the scan window, and generate instruction pointers.Type: GrantFiled: July 10, 2007Date of Patent: October 19, 2010Assignee: GlobalFoundries Inc.Inventors: Gene W. Shen, Sean Lie
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Patent number: 7814299Abstract: A circuit arrangement and method support instruction target history based register address indexing, whereby register addresses to be used by an instruction are decoded using a target history table of previous target register addresses, and an index into the target history table supplied by an index value in the instruction. An instruction may include at least one index value that identifies a previously used register address. During execution of the instruction, the index is retrieved from the instruction, and then a register address is retrieved from the target history table using the index.Type: GrantFiled: November 20, 2008Date of Patent: October 12, 2010Assignee: International Business Machines CorporationInventors: Mark Joseph Hickey, Adam James Muff, Matthew Ray Tubbs, Charles David Wait
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Patent number: 7797516Abstract: A set of low-cost microcontroller extensions facilitates Digital Signal Processing (DSP) applications by incorporating a Multiply-Accumulate (MAC) unit in a Central Processing Unit (CPU) of the microcontroller which is responsive to the extensions.Type: GrantFiled: March 16, 2007Date of Patent: September 14, 2010Assignee: ATMEL CorporationInventors: Benjamin Francis Froemming, Emil Lambrache
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Patent number: 7793079Abstract: A method of expanding a conditional instruction having a plurality of operands within a pipeline processor is disclosed. The method identifies the conditional instruction prior to an issue stage and determines if the plurality of operands exceeds a predetermined threshold. The method expands the conditional instruction into a non-conditional instruction and a select instruction. The method further executes the non-conditional instruction and the select instruction in separate pipelines.Type: GrantFiled: June 27, 2007Date of Patent: September 7, 2010Assignee: QUALCOMM IncorporatedInventors: Serena Badran-Louca, Rodney Wayne Smith, Michael Scott McIlvaine
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Patent number: 7793081Abstract: There are provided methods and computer program products for implementing instruction set architectures with non-contiguous register file specifiers. A method for processing instruction code includes processing a fixed-width instruction of a fixed-width instruction set using a non-contiguous register specifier of a non-contiguous register specification. The fixed-width instruction includes the non-contiguous register specifier.Type: GrantFiled: April 3, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Michael Karl Gschwind, Robert Kevin Montoye, Brett Olsson, John-David Wellman
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Publication number: 20100199073Abstract: A multithreaded processor comprises a plurality of hardware thread units, an instruction decoder coupled to the thread units for decoding instructions received therefrom, and a plurality of execution units for executing the decoded instructions. The multithreaded processor is configured for controlling an instruction issuance sequence for threads associated with respective ones of the hardware thread units. On a given processor clock cycle, only a designated one of the threads is permitted to issue one or more instructions, but the designated thread that is permitted to issue instructions varies over a plurality of clock cycles in accordance with the instruction issuance sequence. The instructions are pipelined in a manner which permits at least a given one of the threads to support multiple concurrent instruction pipelines.Type: ApplicationFiled: October 15, 2009Publication date: August 5, 2010Inventors: Erdem Hokenek, Mayan Moudgill, Michael J. Schulte, C. John Glossner
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Publication number: 20100146244Abstract: A data processor which executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file.Type: ApplicationFiled: December 7, 2009Publication date: June 10, 2010Applicant: Panasonic CorporationInventors: Takeshi Kishida, Masaitsu Nakajima
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Patent number: 7734898Abstract: A data processing system uses a data processor instruction that forms an immediate value. The data processing instruction uses a first field as a portion of the immediate value. A second field of the data processing instruction determines a positional location of the portion of the immediate value within the immediate value. A bit value in a third field of the data processing instruction is used to determine a remainder of the immediate value.Type: GrantFiled: September 17, 2004Date of Patent: June 8, 2010Assignee: Freescale Semiconductor, Inc.Inventor: William C. Moyer
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Publication number: 20100115240Abstract: In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.Type: ApplicationFiled: November 5, 2008Publication date: May 6, 2010Inventors: Ohad Falik, Lihu Rappoport, Ron Gabor, Yulia Kurolap, Michael Mishaeli
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Patent number: 7711926Abstract: A method, cache controller, and computer processor provide a parallel mapping system whereby a plurality of mappers processes several inputs simultaneously. The plurality of mappers are disposed in a pipelined processor upstream from a multiplexor. Mapping, tag comparison, and selection by the multiplexor all occur in a single pipeline stage. Data does not wait idly to be selected by the multiplexor. Instead, each instruction of a first instruction set is read in parallel into a corresponding one of the plurality of mappers. This parallel mapping system implementation reduces processor cycle time and results in improved processor efficiency.Type: GrantFiled: April 18, 2001Date of Patent: May 4, 2010Assignee: MIPS Technologies, Inc.Inventors: Ryan C. Kinter, David A. Courtright
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Patent number: 7707393Abstract: The present invention relates to the field of (micro)computer design and architecture, and in particular to microarchitecture associated with moving data values between a (micro)processor and memory components. Particularly, the present invention relates to a computer system with an processor architecture in which register addresses are generated with more than one execution channel controlled by one central processing unit with at least one load/store unit for loading and storing data objects, and at least one cache memory associated to the processor holding data objects accessed by the processor, wherein said processor's load/store unit contains a high speed memory directly interfacing said load/store unit to the cache and directly accessible by the cache memory for implementing scatter and gather operations. The present invention improves the performance of architectures with dual ported microprocessor implementations comprising two execution pipelines capable of two load/store data transactions per cycle.Type: GrantFiled: May 7, 2007Date of Patent: April 27, 2010Assignee: Broadcom CorporationInventor: Sophie Wilson
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Patent number: 7689811Abstract: A data processing apparatus (2) comprising: a register data store operable to store data elements; an instruction decoder (14, 16) operable to decode an instruction with generated constant, said instruction having a data value associated therewith; a data processor (18) operable to perform data processing operations within parallel processing lanes on at least one source operand in response to a data processing instruction decoded by said instruction decoder (16); and said data processor being operable in response to said decoded instruction with generated constant and associated data value to expand at least a data portion (1210) of said associated data value, said expansion being performed in response to said instruction with generated constant and depending on a selected function, to generate a constant (1240), said generated constant (1240) forming one of said at least one source operands.Type: GrantFiled: July 13, 2004Date of Patent: March 30, 2010Assignee: ARM LimitedInventors: Wilco Dijkstra, Simon Andrew Ford, David James Seal
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Patent number: 7676654Abstract: Methods and apparatus for accessing an extended register space associated with a processor are disclosed. In an example method, an instruction indicating a tag value is received. It is then determined whether information is stored in a first group of registers or a second group of registers based on a comparison of the tag value and an identifier value indicative of the second group of registers. The information is then accessed in the second group of registers in response to the tag value matching the identifier value.Type: GrantFiled: July 30, 2007Date of Patent: March 9, 2010Assignee: Intel CorporationInventor: Ralph M Kling
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Patent number: 7676652Abstract: Within a system supporting execution of variable length instructions a program is stored within discrete memory regions with a variable length instruction spanning a gap between two such discrete memory regions. When execution is attempted of such a variable length instruction spanning a gap, an abort handler is initiated which serves to copy the end portion of one of the memory regions together with the start portion of the other memory region into a separate fix-up memory region where these may be concatenated such that the whole of the variable length instruction will appear in one place. Execution of that variable length instruction from out of the fix-up memory region can then be triggered.Type: GrantFiled: August 27, 2003Date of Patent: March 9, 2010Assignee: ARM LimitedInventors: Hedley James Francis, Frederic Claude Marie Piry, Pierre Michel Broyer
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Patent number: 7676651Abstract: The invention provides a code compression technology that is favorable for a micro controller or other embedded system, and for compressed codes, resulting from conversion of program codes into variable length codes, and grouped program codes, address conversion information for specifying the start address of each group and compressed code type information for specifying the code length of each compressed code contained in a group are stored in a memory, and by enabling a corresponding compressed code address to be calculated from a code address output by a CPU, code compression that is favorable for a micro controller or other embedded system is realized.Type: GrantFiled: June 30, 2003Date of Patent: March 9, 2010Assignee: Hitachi, Ltd.Inventors: Hiromichi Yamada, Yuichi Abe, Yasuhiro Nakatsuka, Takanaga Yamazaki
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Patent number: 7676653Abstract: The invention provides a decode unit for decoding instructions in a processor. The decode unit comprises opcode decoding logic, operand decoding logic, and a sixteen-bit input. The opcode decoding logic is operable to determine an opcode using five bits of the input and the operand decoding logic is operable to determine three four-bit operand elements from the remaining eleven bits of the input, the three operand elements each having one of twelve possible binary values. The operand decoding logic is operable to decode an encoded group of the eleven bits to determine a first part of each of the three operand elements, and to read verbatim a verbatim group of the eleven bits to determine a second part of each of the three operand elements.Type: GrantFiled: May 9, 2007Date of Patent: March 9, 2010Assignee: XMOS LimitedInventor: Michael David May
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Patent number: RE41751Abstract: A processor can decode short instructions with a word length equal to one unit field and long instructions with a word length equal to two unit fields. An opcode of each kind of instruction is arranged into the first unit field assigned to the instruction. The number of instructions to be executed by the processor in parallel is s. When the ratio of short to long instructions is s-1:1, the s-1 short instructions are assigned to the first unit field to the s-1tA unit field in the parallel execution code, and the long instruction is assigned to the sth unit field to the (s+k?1)th unit field in the same parallel execution code.Type: GrantFiled: November 24, 2003Date of Patent: September 21, 2010Assignee: Panasonic CorporationInventors: Taketo Heishi, Tetsuya Tanaka, Nobuo Higaki, Shuichi Takayama, Kensuke Odani
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Patent number: RE41959Abstract: The present invention discloses a program converting unit for generating a machine language instruction from a source program for a processor that manages an N-bit address while processing M-bit data, N being greater than M, and such a processor that runs the converted program. The program converting unit comprising: a parameter holding unit for holding a data width and a pointer width designated by a user; the data width representing the number of bits of data used in the source program while the pointer width representing the number of bits of an address; and a generating unit for generating an instruction to manage the data width when a variable operated by the instruction represents the data, and for generating an instruction to manage the pointer width when a variable operated by the instruction represents the address.Type: GrantFiled: September 14, 2000Date of Patent: November 23, 2010Assignee: Panasonic CorporationInventors: Masato Suzuki, Hiroshi Kamiyama, Shinya Miyaji
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Patent number: RE43248Abstract: Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register for indicating the address of a next program instruction word in the data memory; means for modifying the contents of the program counter register in response to a current program instruction word; and control means, responsive to one or more predetermined indicator bits of the program counter register, for controlling the processor core to execute program instruction words of a current instruction set selected from the predetermined plurality of instruction sets and specified by the state of the one or more indicator bits of the program counter register.Type: GrantFiled: February 1, 2002Date of Patent: March 13, 2012Assignee: ARM LimitedInventor: Edward Colles Nevill