Masking Patents (Class 712/224)
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Patent number: 8332620Abstract: A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement.Type: GrantFiled: July 25, 2008Date of Patent: December 11, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Uri Dayan, Aviram Amir, Itzhaki Barak, Shahar Nahum, Idan Rozenberg, Ron Shaposhnikov, Erez Steinberg
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Patent number: 8250576Abstract: The present invention extends to methods, systems, and computer program products for a structured task hierarchy for a parallel runtime. The parallel execution runtime environment permits flexible spawning and attachment of tasks to one another to form a task hierarchy. Parent tasks can be prevented from completing until any attached child sub-tasks complete. Exceptions can be aggregated in an exception array such that any aggregated exceptions for a task are available when the task completes. A shield mode is provided to prevent tasks from attaching to another task as child tasks.Type: GrantFiled: September 30, 2009Date of Patent: August 21, 2012Assignee: Microsoft CorporationInventors: Huseyin S. Yildiz, Stephen H. Toub, John J. Duffy
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Patent number: 8245195Abstract: A method for debugging a computer program is provided. The method pushes a plurality of registers into a stack, and calculates a jump-from address and a jump-to address for each jump according to values of the registers. The jump-from address and the jump-to address are then stored into a storage system. The method may monitor the execution of the computer program in system management mode (SMM).Type: GrantFiled: December 7, 2008Date of Patent: August 14, 2012Assignee: Hon Hai Precision Industry Co., Ltd.Inventor: Ching-Yu Lai
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Patent number: 8225075Abstract: Method, apparatus, and program means for shuffling data. The method of one embodiment comprises receiving a first operand having a set of L data elements and a second operand having a set of L control elements. For each control element, data from a first operand data element designated by the individual control element is shuffled to an associated resultant data element position if its flush to zero field is not set and a zero is placed into the associated resultant data element position if its flush to zero field is not set.Type: GrantFiled: October 8, 2010Date of Patent: July 17, 2012Assignee: Intel CorporationInventors: William W. Macy, Jr., Eric L. Debes, Patrice L. Roussel, Huy V. Nguyen
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Patent number: 8209522Abstract: Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field from a second general register designated as a second source register. The second instruction inserts any extracted field parts in a result register.Type: GrantFiled: January 6, 2011Date of Patent: June 26, 2012Assignee: MIPS Technologies, Inc.Inventors: Sol Katzman, Robert Gelinas, W. Patrick Hays
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Publication number: 20120151185Abstract: A processor and a method for privilege escalation in a processor are provided. The method may comprise fetching an instruction from a fetch address, where the instruction requires the processor to be in supervisor mode for execution, and determining whether the fetch address is within a predetermined address range. The instruction is filtered through an instruction mask and then it is determined whether the instruction, after being filtered through the mask, equals the value in an instruction value compare register. The processor privilege is raised to supervisor mode for execution of the instruction in response to the fetch address being within the predetermined address range and the filtered instruction equaling the value in the instruction value compare register, wherein the processor privilege is raised to supervisor mode without use of an interrupt. The processor privilege returns to its previous level after execution of the instruction.Type: ApplicationFiled: December 14, 2010Publication date: June 14, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Anthony J. Bybell, Anup Wadia
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Patent number: 8201170Abstract: A method of enabling multiple different operating systems to run concurrently on the same computer, comprising selecting a first operating system to have a relatively high priority (the realtime operating system. such as C5); selecting at least one secondary operating system to have a relatively lower priority (the general purpose operating system, such as Linux); providing a common program (a hardware resource dispatcher similar to a nanokernel) arranged to switch between said operating systems under predetermined conditions; and providing modifications to said first and second operating systems to allow them to be controlled by said common program.Type: GrantFiled: April 7, 2004Date of Patent: June 12, 2012Assignee: Jaluna SAInventors: Eric Lescouet, Vladimir Grouzdev
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Patent number: 8191085Abstract: A method for operating a data processing system includes providing an application binary interface (ABI) which determines a set of non-contiguous volatile registers and a set of non-volatile registers. The set of non-contiguous volatile registers includes a plurality of general purpose registers (GPRs) and a plurality of special purpose registers (SPRs). The method includes providing less than three instructions which collectively load or store all of the set of non-contiguous volatile registers determined by the ABI. A system includes a set of volatile registers including a plurality of volatile GPRs, a plurality of volatile supervisor SPRs, and a plurality of volatile user SPRs, and execution circuitry for executing a first instruction that loads or stores the plurality of volatile supervisor SPRs, for executing a second instruction that loads or stores the plurality of volatile GPRs, and for executing a third instruction that loads or stores the plurality of volatile user SPRs.Type: GrantFiled: August 29, 2006Date of Patent: May 29, 2012Assignee: Freescale Semiconductor, Inc.Inventor: William C. Moyer
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Patent number: 8161270Abstract: A programmable processor configured to perform one or more packet modifications through execution of one or more commands. A pipelined processor core comprises a first stage configured to selectively shift and mask data in each of a plurality of categories in response to one or more decoded commands, and combine the selectively shifted and masked data in each of the categories. The pipelined processor core further comprises a second stage configured to selectively perform one or more operations on the combined data from the first stage and other data responsive to the one or more decoded commands. In one implementation, the processor is implemented as an application specific integrated circuit (ASIC).Type: GrantFiled: March 30, 2004Date of Patent: April 17, 2012Assignee: Extreme Networks, Inc.Inventors: David K. Parker, Erik R. Swenson, Christopher J. Young
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Publication number: 20120079244Abstract: An apparatus and method are described for performing arbitrary logical operations specified by a table. For example, one embodiment of a method for performing a logical operation on a computer processor comprises: reading data from each of two or more source operands; combining the data read from the source operands to generate an index value, the index value identifying a subset of bits within an immediate value transmitted with an instruction; reading the bits from the immediate value; and storing the bits read from the immediate value within a destination register to generate a result of the instruction.Type: ApplicationFiled: September 24, 2010Publication date: March 29, 2012Inventor: Andrew T. Forsyth
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Patent number: 8145885Abstract: A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.Type: GrantFiled: April 30, 2008Date of Patent: March 27, 2012Assignee: International Business Machines CorporationInventors: Ronald Nick Kalla, Minh Michelle Quy Pham, Balaram Sinharoy, John Wesley Ward, III
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Patent number: 8127117Abstract: A method and system to combine corresponding half word units from multiple register units within a microprocessor, such as, for example, a digital signal processor, during execution of a single instruction are described. An instruction to combine predetermined disparate source register units from a register file structure is received within a processing unit. The instruction is then executed to combine corresponding half word units from the source register units and to input the half word units into respective portions of a resulting destination register unit. During the execution of the instruction, the predetermined source register units are identified and corresponding most significant half word units and associated data are retrieved from the identified register units. The retrieved half word units are further combined and input into a respective most significant portion of a resulting destination register unit.Type: GrantFiled: May 10, 2006Date of Patent: February 28, 2012Assignee: QUALCOMM IncorporatedInventors: Mao Zeng, Lucian Codrescu
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Patent number: 8086830Abstract: An arithmetic processing apparatus capable of performing an arithmetic operation for generating a condition flag commonly referred to by using a condition flag generated on an arithmetic operation unit basis in as few steps as possible is provided. The arithmetic processing apparatus, which processes multiple data in parallel based on single instruction, includes: processing elements capable of performing a common arithmetic operation based on the evaluation result of the instruction stored in the instruction register; and a condition flag arithmetic operation unit capable of performing one of the logical operation and the comparison operation on the condition flag retained in each processing element, transferring the operation result to each processing element, and updating the condition flag based on the operation result.Type: GrantFiled: August 24, 2005Date of Patent: December 27, 2011Assignee: Panasonic CorporationInventors: Takeshi Furuta, Hideshi Nishida, Takeshi Tanaka
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Patent number: 7949697Abstract: A bit field operation circuit has a first shift unit, a mask shift amount control circuit, a second shift unit, a logic operation unit, and a selection unit. The first shift unit outputs a first intermediate data based on a first control signal. The mask shift amount control circuit outputs a mask shift control signal in accordance with a mask shift amount. The second shift unit outputs a second intermediate data based on a mask shift control signal. The third shift unit outputs a third intermediate data based on the first control signal. The logic operation unit performs logical operation of the second intermediate data and the third intermediate data, and outputs a mask selection data. The selection unit selects either one of the first intermediate data or the second input data based on the mask selection data to output as output data.Type: GrantFiled: August 1, 2007Date of Patent: May 24, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Kenichi Handa
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Patent number: 7913255Abstract: Techniques for the design and use of a digital signal processor, including processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system provide background thread processing in a multithread digital signal processor for backgrounding and other background operations. The method and system form a background thread interrupt as one of a plurality of interrupt types, the background thread interrupt initiates a low-priority background process using one of a plurality of processing threads of a multithread digital signal processor. The process includes storing the background thread interrupt in an interrupt register and a background processing mask for associating with a processing thread of the multithread digital signal processor, which associates with at least a subset of said plurality of processing threads.Type: GrantFiled: October 20, 2005Date of Patent: March 22, 2011Assignee: QUALCOMM IncorporatedInventor: Lucian Codrescu
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Patent number: 7895419Abstract: A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.Type: GrantFiled: January 11, 2008Date of Patent: February 22, 2011Assignee: International Business Machines CorporationInventors: Dan F. Greiner, Timothy J. Slegel, Joachim von Buttlar
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Patent number: 7895423Abstract: Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field from a second general register designated as a second source register. The second instruction inserts any extracted field parts in a result register.Type: GrantFiled: August 19, 2009Date of Patent: February 22, 2011Assignee: MIPS Technologies, Inc.Inventors: Sol Katzman, Robert Gelinas, W. Patrick Hays
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Method and structure for low latency load-tagged pointer instruction for computer microarchitechture
Patent number: 7849293Abstract: A methodology and implementation of a load-tagged pointer instruction for RISC based microarchitecture is presented. A first lower latency, speculative implementation reduces overall throughput latency for a microprocessor system by estimating the results of a particular instruction and confirming the integrity of the estimate a little slower than the normal instruction execution latency. A second higher latency, non-speculative implementation that always produces correct results is invoked by the first when the first guesses incorrectly. The methodologies and structures disclosed herein are intended to be combined with predictive techniques for instruction processing to ultimately improve processing throughput.Type: GrantFiled: January 31, 2008Date of Patent: December 7, 2010Assignee: International Business Machines CorporationInventors: Bartholomew Blaner, Michael K. Gschwind -
Patent number: 7849466Abstract: A multithreaded processor device is disclosed and includes a processor that is configured to execute a plurality of executable program threads and a mode control register. The mode control register includes a first data field to control a first execution mode of a first of the plurality of executable program threads and a second data field to control a second execution mode of a second of the plurality of executable program threads. In a particular embodiment, the first execution mode is a run mode and the second execution mode is a low power mode.Type: GrantFiled: July 12, 2005Date of Patent: December 7, 2010Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Donald Robert Padgett, Erich Plondke, Taylor Simpson, Muhammad Ahmed, William C. Anderson, Sujat Jamil
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Publication number: 20100306505Abstract: A processor 2 includes an execution cluster 10 having multiple execution units 14, 16, 18, 20. The execution units 14, 16, 18, 20 share result buses 22, 24. Issue circuitry 12 within the execution cluster 10 determines future availability of a result bus 22, 24 for an instruction to be issued (or recently issued) using a known cycle count for that instruction. The availability is tracked for each result bus using a mask register 32 storing a mask value within which each bit position indicates the availability or non-availability of that result bus at a particular processing cycle in the future. The mask value is left shifted each processing cycle.Type: ApplicationFiled: June 1, 2009Publication date: December 2, 2010Inventors: David James Williamson, Conrado Blasco Allue
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Patent number: 7818549Abstract: The present invention relates to an event driven digital signal processor 1 comprising: a central arithmetical unit 5, a register 4, a controller 3, an instruction memory 2, and input/output devices. The instruction memory 2 is arranged to include time performance constraints and events. An event control unit 6 is arranged to recognize an event and to control processing to be carried out as a consequence of the event while fulfilling the time performance constraints. The controller 3 is arranged to suspend processing of the time performance constraints after initiating operations in the event control unit 6. The controller 3 resumes processing when advised by the event control unit 6.Type: GrantFiled: September 22, 2003Date of Patent: October 19, 2010Assignee: SAAB ABInventors: Ingemar Söderquist, Rolf Loh
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Publication number: 20100169619Abstract: In one embodiment, an apparatus comprises a queue comprising a plurality of entries and a control unit coupled to the queue. The control unit is configured to allocate a first queue entry to a store memory operation, and is configured to write a first even offset, a first even mask, a first odd offset, and a first odd mask corresponding to the store memory operation to the first entry. A group of contiguous memory locations are logically divided into alternately-addressed even and odd byte ranges. A given store memory operation writes at most one even byte range and one adjacent odd byte range. The first even offset identifies a first even byte range that is potentially written by the store memory operation, and the first odd offset identifies a first odd byte range that is potentially written by the store memory operation.Type: ApplicationFiled: March 10, 2010Publication date: July 1, 2010Inventors: Tse-yu Yeh, Daniel C. Murray, Po Yung Chang, Anup S. Mehta
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Patent number: 7685408Abstract: Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.Type: GrantFiled: September 29, 2008Date of Patent: March 23, 2010Assignee: Altera CorporationInventors: Edward A. Wolff, Peter R. Molnar, Ayman Elezabi, Gerald George Pechanek
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Publication number: 20100023734Abstract: A method for executing an instruction, the method includes: executing a compare and configure mask instruction, wherein the executing comprises: performing a comparison to provide a comparison result; and configuring, in response to the comparison result, a multiple bit mask that is stored in a multiple-purpose register; wherein all bits of the multiple bit mask are configured to have the same value; and applying an algorithmic operation on the multiple bit mask to provide an algorithmic operation result; wherein the algorithmic operation result represents an outcome of a high level programming language conditional statement.Type: ApplicationFiled: July 25, 2008Publication date: January 28, 2010Inventors: Uri Dayan, Aviram Amir, Itzhaki Barak, Shahar Nahum, Idan Rozenberg, Ron Shaposhnikov, Erez Steinberg
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Patent number: 7634638Abstract: An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register.Type: GrantFiled: October 22, 2002Date of Patent: December 15, 2009Assignee: MIPS Technologies, Inc.Inventor: Michael Gottlieb Jensen
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Patent number: 7600100Abstract: An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates the instructions are to be executed in privileged (kernel) state only, and are to communicate with privileged control registers. The instructions designate which of a plurality of privileged architecture registers is to be modified, which bit fields within the designated privileged architecture register is to be modified, and whether the designated bit fields are to be set or cleared. An instruction atomically sets or clears bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.Type: GrantFiled: December 6, 2006Date of Patent: October 6, 2009Assignee: MIPS Technologies, Inc.Inventor: Michael Gottlieb Jensen
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Patent number: 7581091Abstract: Systems and methods that allow for extracting a field from data stored in a pair of registers using two instructions. A first instruction extracts any part of the field from a first register designated as a first source register, and executes a second instruction extracting any part of the field from a second general register designated as a second source register. The second instruction inserts any extracted field parts in a result register.Type: GrantFiled: April 10, 2006Date of Patent: August 25, 2009Assignee: MIPS Technologies, Inc.Inventors: Robert Gelinas, Patrick W Hays, Sol Katzman
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Patent number: 7565515Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.Type: GrantFiled: January 16, 2004Date of Patent: July 21, 2009Assignee: Microunity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Patent number: 7558948Abstract: A method for reducing overhead on a loop of a plurality of instructions is disclosed. The method includes providing a carry mask, the carry mask having a first value for the loop being performed at least the particular number of times minus one and a second value for at least a last instruction of the loop being performed a last time, providing addition logic, wherein the carry mask and a current instruction address of the plurality of instructions correspond to inputs of the addition logic and determining which of the plurality of instructions is to be executed using the carry mask to provide a resultant of the addition logic based on the carry mask and the current instruction address of the plurality of instructions.Type: GrantFiled: September 20, 2004Date of Patent: July 7, 2009Assignee: International Business Machines CorporationInventors: Anthony J. Bybell, Richard W. Doing, David D. Dukro
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Patent number: 7555636Abstract: A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-bit hardware execution environment, a load and reserve instruction sets a reservation for a memory location. The original 64-bit data object is decomposed into two 32-bit halves. A Shift Right Double Word Immediate (SRDI) instruction captures the high-order bits of the 64-bit register. If the store conditional instruction determines that the reservation is not lost, the store conditional instruction stores the result. If the store conditional instruction fails, the process returns to the reserve instruction until the store conditional operation returns a success.Type: GrantFiled: August 29, 2007Date of Patent: June 30, 2009Assignee: International Business Machines CorporationInventor: Larry Bert Brenner
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Publication number: 20090150655Abstract: A register updating method includes generating third information including first information and second information, wherein the first information indicates whether updating of regions of a register block is allowed and the second information includes information that is to be updated in the register block, transmitting the third information to an address of the register block that is to be updated, and selecting a part of the second information in a unit of the regions and writing the selected second information to the register block, based on the first information included in the received third information.Type: ApplicationFiled: December 3, 2008Publication date: June 11, 2009Inventor: Moon-Gyung KIM
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Patent number: 7543287Abstract: In one embodiment, a standard block device command is received at a device controller. The standard block device command is addressed to a virtual block device associated with the device controller. The standard block device command is to invoke functionality from the device controller unrelated to the standard block device command. The functionality invoked by the standard block device command is performed by the device controller.Type: GrantFiled: June 30, 2005Date of Patent: June 2, 2009Assignee: Intel CorporationInventors: Vincent J. Zimmer, Michael A. Rothman
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Patent number: 7529907Abstract: Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.Type: GrantFiled: October 22, 2007Date of Patent: May 5, 2009Assignee: MIPS Technologies, Inc.Inventors: Mario D. Nemirovsky, Stephen Melvin, Enrique Musoll, Narendra Sankar
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Patent number: 7526635Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.Type: GrantFiled: January 15, 2004Date of Patent: April 28, 2009Assignee: Micounity Systems Engineering, Inc.Inventors: Craig Hansen, John Moussouris
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Publication number: 20090089557Abstract: Embodiments of an apparatus that uses unused masked data bits during an access to a memory are described. This apparatus includes a selection circuit, which selects data bits to be driven on data lines during the access to the memory. This selection circuit includes a control input that receives a data mask signal, which indicates whether a set of data bits is to be masked during the access to the memory. During the access to the memory, the selection circuit selects either the set of data bits to be driven when the data mask signal is not asserted, or an alternative set of values to be driven when the data mask signal is asserted.Type: ApplicationFiled: September 12, 2008Publication date: April 2, 2009Applicant: RAMBUS INC.Inventors: Lei Luo, Frederick A. Ware, John Wilson, Jade M. Kizer
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Publication number: 20090077354Abstract: A technique for handling predicated code in an out-of-order processor includes detecting a predicate defining instruction associated with a predicated code region. Renaming of predicated instructions, within the predicated code region, is then stalled until a predicate of the predicate defining instruction is resolved.Type: ApplicationFiled: September 17, 2007Publication date: March 19, 2009Inventors: Ram Rangan, William E. Speight, Mark W. Stephenson, Lixin Zhang
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Publication number: 20090049283Abstract: An information processing device including registers (105) for holding data and an operation device (102) for executing arithmetic and logic operations on input/output data held in the register. The information processing device can issue an inter-register copy instruction for instructing data held in one register to be copied to another register. The information processing device further includes a copy information holding device (113) for reserving for execution of a data copy operation by the inter-register copy instruction from a control unit (108) so as to execute the actual copy operation simultaneously with the succeeding instruction to hide the execution time of the copy operation. Thus, in the inter-register copy instruction execution phase, a reservation for a data copy operation is stored in the copy information holding device so that the execution phase is completed without performing the actual data copy operation.Type: ApplicationFiled: May 18, 2006Publication date: February 19, 2009Inventor: Noritaka Hoshi
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Patent number: 7493481Abstract: In some embodiments, the execution of load and store instructions for internal fields of data structures is accelerated by using on-chip template registers and appropriate machine code instructions. A load/store machine code instruction comprises an identifier of a memory address offset of an internal field word relative to a base address of the data structure, an identifier of an intra-word start bit of the internal field, and an identifier of an intra-word length of the internal field. The three identifiers may coincide, for example if the three identifiers are represented by an identity of a template register storing a template entry including the memory address offset, the start position, and the field length. The three identifiers may also be provided as part of a machine code instruction itself. Further provided are compilers, compiler methods, and hardware systems for implementing accelerated internal-field load and store operations.Type: GrantFiled: May 17, 2004Date of Patent: February 17, 2009Assignee: NetXen, Inc.Inventors: Govind Kizhepat, Kenneth Y Choy, Suresh Kadiyala
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Patent number: 7480787Abstract: A mask is first generated in a general-purpose integer register. The mask is generated by executing a single instruction multiple data (SIMD) instruction on a plurality of operands stored in a plurality of registers and by writing the result to the general-purpose integer register. Next, a conditional-move mask is generated in a register using the mask, and then the conditional-move mask is used in selecting operands from the plurality of operands to generate a result in another register.Type: GrantFiled: January 27, 2006Date of Patent: January 20, 2009Assignee: Sun Microsystems, Inc.Inventors: Paul Caprioli, Lawrence A. Spracklen, Sherman H. Yip
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Patent number: 7437541Abstract: A method, system, and computer instructions for atomically updating 64-bit fields in the 32-bit AIX kernel, wherein the underlying hardware's 64-bit capable instructions are used to construct an atomic primitive. If a data request applies to the 32-bit kernel on 64-bit hardware execution environment, a load and reserve instruction sets a reservation for a memory location. The original 64-bit data object is decomposed into two 32-bit halves. A Shift Right Double Word Immediate (SRDI) instruction captures the high-order bits of the 64-bit register. If the store conditional instruction determines that the reservation is not lost, the store conditional instruction stores the result. If the store conditional instruction fails, the process returns to the reserve instruction until the store conditional operation returns a success.Type: GrantFiled: July 8, 2004Date of Patent: October 14, 2008Assignee: International Business Machiens CorporationInventor: Larry Bert Brenner
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Patent number: 7404068Abstract: Mechanisms for performing per-bit operations in system memory in a single operation thereby obviating the need for semaphore mechanisms when performing per-bit operations. A processor accesses an instruction that identifies the specific bit of system memory that is to be operated upon, as well as an operation to be performed on the bit. The operation may be, for example, a bit set, clear, or toggle. The processor then instructs system memory to perform the operation. Since the operation is performed in a single operation, other processes do not need to wait before continuing operation on the memory address of the specific bit. In addition, semaphores restricting access to the memory address need not be used while still retaining adequate assurance that the memory address will remain consistent.Type: GrantFiled: November 7, 2003Date of Patent: July 22, 2008Assignee: Finisar CorporationInventors: Gerald L. Dybsetter, Jayne C. Hahin
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Patent number: 7401204Abstract: A parallel processor performs efficient parallel processing of one or more basic instructions contained in each of a plurality of instruction words delimited by instruction delimiting information. The processor includes: a plurality of instruction execution units performing processes in accordance with corresponding, supplied basic instructions in parallel; an instruction fetch unit fetching the instruction words one by one in accordance with the instruction delimiting information; and an instruction issue unit recognizing and, in accordance therewith, selecting each of the basic instructions contained in each of the instruction words fetched by the instruction fetch unit to a corresponding instruction execution unit to execute the basic instruction.Type: GrantFiled: September 1, 2000Date of Patent: July 15, 2008Assignee: Fujitsu LimitedInventors: Hideo Miyake, Atsuhiro Suga, Yasuki Nakamura, Yoshimasa Takebe
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Patent number: 7401208Abstract: A processor interleaves instructions according to a priority rule which determines the frequency with which instructions from each respective thread are selected and added to an interleaved stream of instructions to be processed in the data processor. The frequency with which each thread is selected according to the rule may be based on the priorities assigned to the instruction threads. A randomization is inserted into the interleaving process so that the selection of an instruction thread during any particular clock cycle is not based solely by the priority rule, but is also based in part on a random or pseudo random element. This randomization is inserted into the instruction thread selection process so as to vary the order in which instructions are selected from the various instruction threads while preserving the overall frequency of thread selection (i.e. how often threads are selected) set by the priority rule.Type: GrantFiled: April 25, 2003Date of Patent: July 15, 2008Assignee: International Business Machines CorporationInventors: Ronald Nick Kalla, Minh Michelle Quy Pham, Balaram Sinharoy, John Wesley Ward, III
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Patent number: 7373463Abstract: An integrated circuit and an antifraud method implementing at least one operation involving at least one secret quantity, and functionally including upstream and downstream of the operator at least one source register and at least one destination register, respectively, and including means for loading a random number at least in the destination register.Type: GrantFiled: February 11, 2004Date of Patent: May 13, 2008Assignee: STMicroelectronics S.A.Inventors: Yannick Teglia, Pierre-Yvan Liardet
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Patent number: 7370184Abstract: An apparatus for shifting data is disclosed. The apparatus includes a shifter, a register, and a shift post processor. The shifter shifts an operand according to an offset parameter, thereby generating a shifted operand. The register is coupled to the shift post processor to transfer a shift carry operand stored in the register to the shift post processor, and coupled to the shifter to store the shifted operand after any transfer of the shift carry operand. The shift post processor is coupled to the shifter and the register to process the shifted operand to generate an output based on at least a control signal and a mask field. The shift post processor comprises a decoder to decode the offset parameter into the mask field, the mask field having a plurality of mask bits, each of the mask bits corresponding to a bit position of the shifted operand.Type: GrantFiled: August 20, 2001Date of Patent: May 6, 2008Assignee: The United States of America as represented by the Secretary of the NavyInventor: Sam B. Sandbote
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Patent number: 7353501Abstract: A method instruments a function in an executable file so that the instrumented function calls a generic preprocessor prior to execution of the body of the function. After the preprocessor modifies the original function's incoming parameters, the body of the function itself is executed. Finally, execution is directed to a generic postprocessor prior to returning from the function. The postprocessor modifies the outgoing parameters and return value. In one implementation, the parameters of an instrumented function are described and packaged into a descriptor data structure. The descriptor data structure is passed to the generic preprocessor and postprocessor. A generic processor uses the descriptor to select changed behaviors based on the calling context.Type: GrantFiled: November 18, 2002Date of Patent: April 1, 2008Assignee: Microsoft CorporationInventors: Qinlin Tang, Gurbakshish S. Rana, Richard Shupak
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Patent number: 7350058Abstract: A data processing system 2 is provided which supports shift-and-insert instructions SLI, SRI which serve to shift a source data value by a specified shift amount and then insert bits from that shifted value other than the shifted-in bits into a destination value with the remaining bits within that destination value being unaltered.Type: GrantFiled: August 30, 2004Date of Patent: March 25, 2008Assignee: ARM LimitedInventors: Paul Matthew Carpenter, Simon Andrew Ford
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Publication number: 20080065863Abstract: One embodiment of the present method and apparatus for data stream alignment support includes retrieving a first input from a first register file, retrieving a second input from a second register file, the second register file being dedicated to a stream shift unit and performing the stream shift instruction in accordance with the first input, the second input and a third input.Type: ApplicationFiled: September 11, 2006Publication date: March 13, 2008Inventors: Alexandre E. Eichenberger, Michael Karl Gschwind, John-David Wellman, Peng Wu
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Publication number: 20080046698Abstract: A computer implemented method of video date encoding generates a mask having one bit corresponding each spatial frequency coefficient of a block during quantization. The bit state of the mask depends upon whether the corresponding quantized spatial frequency coefficient is zero or non-zero. The runs of zero quantized spatial frequency coefficients determined by a left most bit detect instruction are determined from the mask and run length encoded. The mask is generated using a look up table to map the scan order of quantization to the zig-zag order of run length encoding. Variable length coding and inverse quantization optionally take place within the run length encoding loop.Type: ApplicationFiled: August 21, 2007Publication date: February 21, 2008Inventors: Kapil Ahuja, Pavan V. Shastry, Ratna M.V. Reddy
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Patent number: 7330937Abstract: A method is disclosed that comprises determining whether a data subsystem is to operate as cache memory or as scratchpad memory in which line fetches from external memory are suppressed and programming a control bit to cause the data subsystem to be operated as either a cache or scratchpad memory depending on the determination. Other embodiments are disclosed herein as well.Type: GrantFiled: April 5, 2004Date of Patent: February 12, 2008Assignee: Texas Instruments IncorporatedInventors: Gerard Chauvel, Serge Lasserre, Dominique D'Inverno, Maija Kuusela, Gilbert Cabillic, Jean-Philippe Lesot, Michel Banâtre, Jean-Paul Routeau, Salam Majoul, Frédéric Parain