Masking Patents (Class 712/224)
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Patent number: 7318014Abstract: A complete hardware design environment is available through a system level simulator. This hardware design environment provides a bit accurate simulator for carrying out hardware simulations in the system level simulator. These simulations take advantage of the computational capabilities of the simulation processor. To take advantage of the simulation processor's resources (e.g., certain FPU components), the signals used in the simulation are made to conform to the native word type of the simulation processor. The hardware blocks deployed in a design frequently use non-native (from the simulation processor's perspective) word types. The bit accurate simulator casts words (signals) defined in the hardware design from a non-native format to a multi-bit native format suitable for use by the simulation processor. At various stages in the simulation, the simulator checks the “value” of the signal to determine whether that value is allowed by a word format specified by the hardware design.Type: GrantFiled: May 31, 2002Date of Patent: January 8, 2008Assignee: Altera CorporationInventors: Philippe Molson, Tony San
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Patent number: 7302511Abstract: In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.Type: GrantFiled: October 13, 2005Date of Patent: November 27, 2007Assignee: Intel CorporationInventors: Stalinselvaraj Jeyasingh, Andrew V. Anderson, Steven M. Bennett, Erik Cota-Robles, Alain Kagi, Gilbert Neiger, Richard Uhlig
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Patent number: 7290122Abstract: A method and apparatus for power reduction in a processor controlled by multiple-instruction control words. A multiple-instruction control word comprises a number of ordered fields, with each ordered field containing an instruction for an element of the processor. The sequence of instructions for a loop is compressed by identifying a set of aligned fields that contain NOP instructions in all of the control words of the sequence. The sequence of control words is then modified by removing the fields of the identified aligned set containing NOP instructions and adding an identifier that identifies the set of fields removed. The sequence of control words is processed by fetching the identifier at the start the loop, then, for each control word in the sequence, fetching a control word and reconstructing the corresponding uncompressed control word by inserting NOP instructions into the compressed control word as indicated by the identifier.Type: GrantFiled: August 29, 2003Date of Patent: October 30, 2007Assignee: Motorola, Inc.Inventors: Philip E. May, Brian G. Lucas, Kent D. Moat
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Patent number: 7290289Abstract: A processor comprises a first calculating unit, a second calculating unit and a control means for controlling the two calculating units, such that they selectively operate in a high security mode of operation processing complementary data or in a parallel mode of operation processing independent data, or in a security mode of operation processing the same data, or that they are in a power-saving mode of operation, wherein one of the calculating units is switched off.Type: GrantFiled: January 23, 2004Date of Patent: October 30, 2007Assignee: Infineon Technologies AGInventors: Marcus Janke, Peter Laackmann
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Patent number: 7278011Abstract: A method, completion table and processor for tracking a larger number of outstanding instructions. The completion table may include a plurality of entries where each entry tracks a consecutive number of outstanding instructions. Each entry may be configured to store an instruction address and an identification of a first of the consecutive number of outstanding instructions. By being able to track a consecutive number of outstanding instructions, such as the length of a cache line, in each entry in the completion table by only storing the instruction address and identification of the first of the consecutive number of outstanding instruction in that entry, the completion table may be able to track a larger number of outstanding instruction without increasing its size.Type: GrantFiled: April 8, 2004Date of Patent: October 2, 2007Assignee: International Business Machines CorporationInventors: Susan E. Eisen, Hung Q. Le, David A. Luick, Dung Q. Nguyen
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Patent number: 7275147Abstract: Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a shift value, preferably as parameters of the instruction. A first and a second subset of data of less than n bits are selected, by logical shifting, from the two registers, respectively, based solely upon the shift value. Then, the subsets are concatenated, preferably by a logical OR, to obtain an output of n bits. The output may be aligned data or packed data, particularly useful for performing a single operation on multiple sets of the data through parallel processing with a SIMD processor.Type: GrantFiled: March 31, 2003Date of Patent: September 25, 2007Assignee: Hitachi, Ltd.Inventor: Clifford Tavares
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Patent number: 7269720Abstract: Techniques are described for dynamically controlling the execution of operations within a multi-operation instruction, such as a very long instruction word (VLIW). A programmable processor fetches and executes a first instruction having an operation mask. Based on the operation mask, the processor selectively executes one or more operations within a second instruction. Individual operations within a multi-operation instruction can be selectively enabled and disabled, which is advantageous in many situations, including event handling and code debugging.Type: GrantFiled: April 4, 2005Date of Patent: September 11, 2007Assignee: NXP B.V.Inventors: Marcel J. A. Tromp, Frans W Sijstermans, Sunny C Huang, Rudolf H. J. Bloks
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Patent number: 7219213Abstract: According to some embodiments, a evaluation unit may be provided for Single Instruction, Multiple Data (SIMD) execution engine flag registers. For example, a horizontal evaluation unit might perform evaluation operations across multiple vectors being processed by the SIMD execution engine. According to some embodiments, a vertical evaluation unit might perform evaluation operations across multiple flag registers.Type: GrantFiled: December 17, 2004Date of Patent: May 15, 2007Assignee: Intel CorporationInventors: Michael K. Dwyer, Hong Jiang
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Patent number: 7191317Abstract: A method and system for conditionally carrying out an operation defined in a computer instruction wherein a computer instruction is implemented on so-called packed operands; that is, operands containing a plurality of packed objects in respective lanes. An operation defined in the computer instruction is conditionally carried out in dependence on stored condition values which determine for each lane whether or not the operation is to be executed on objects in that lane.Type: GrantFiled: September 13, 1999Date of Patent: March 13, 2007Assignee: Broadcom CorporationInventor: Sophie Wilson
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Patent number: 7185183Abstract: A group of bit set and bit clear instructions are provided for a microprocessor to allow atomic modification of privileged architecture control registers. The bit set and bit clear instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers. Two operands are provided for the instructions, the first designating which of the privileged control registers is to be modified, the second designating a general purpose register that contains a bit mask. The bit set instructions set bits in the designated control register according to bits set in the bit mask. The bit clear instructions clear bits in the designated control register according to bits set in the bit mask. By atomically modifying privileged control registers, a requirement for strict nesting of interrupt routines is eliminated.Type: GrantFiled: August 2, 2001Date of Patent: February 27, 2007Assignee: MIPS Technologies, Inc.Inventor: G. Michael Uhler
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Patent number: 7177967Abstract: In one embodiment, an apparatus includes a set of multiplex blocks coupled with an interrupt controller and multiple interrupt request lines, and a virtual machine monitor block (VMM) coupled to the set of multiplex blocks. Each multiplex block corresponds to a distinct interrupt request line. Each multiplex block is to route the interrupt request signal received via the corresponding interrupt request line either to the interrupt controller or the VMM block depending on a current configuration value of this multiplex block.Type: GrantFiled: September 30, 2003Date of Patent: February 13, 2007Assignee: Intel CorporationInventors: Stalinselvaraj Jeyasingh, Andrew V. Anderson, Steven M. Bennett, Erik Cota-Robles, Alain Kagi, Gilbert Neiger, Richard Uhlig
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Patent number: 7143265Abstract: A memory access system is described which generates two memory addresses from a single memory access instruction which identifies a register holding at least two packed objects. In the preferred embodiment, the contents of a base register is combined respectively with each of two or more packed objects in an offset register.Type: GrantFiled: September 29, 2004Date of Patent: November 28, 2006Assignee: Broadcom CorporationInventor: Sophie Wilson
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Patent number: 7139904Abstract: A data byte insertion circuit includes circuitry to generate derivative intermediate data words from input data words of a current and a preceding cycle, repositioning data bytes of the input data words before and after data byte insertion points of the current and preceding cycles, and circuitry to generate re-aligned variants of insertion data bytes of the current cycle. The data byte insertion circuit further includes circuitry to generate a number of multi-bit data bit selection masks, and circuitry to generate an output data word by conditionally using selected parts of the derivate intermediate data words and the re-aligned variants of the insertion data bytes, in accordance with the multi-bit data bit selection masks.Type: GrantFiled: March 1, 2002Date of Patent: November 21, 2006Inventors: J. Zachary Gorman, Richard S. Willardson
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Patent number: 7114055Abstract: A reduced instruction set computer architecture implemented on a field programmable gate array includes a parallel bit shifter capable of reversible shifts and bit reversals, a Reed-Muller Boolean unit coupled to the parallel bit shifter and an immediate instruction function using a half-word literal field in an instruction word that impacts a whole word logically through a combination of modes that variously manipulates the distribution of a set of literal bits of the half-word literal field across the instruction word.Type: GrantFiled: September 29, 2003Date of Patent: September 26, 2006Assignee: Xilinx, Inc.Inventor: Michael A. Baxter
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Patent number: 7028171Abstract: The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an instruction as an N-way select instruction. The method also includes selecting at least one pair of source operands from a plurality of instruction operands using information from a plurality of parallel control registers. The method, further includes selecting a final source operand from each of the selected at least one pair of source operands, and outputting each of the selected final source operands. In general, any N-way select instruction will have M=log2N stages of operation.Type: GrantFiled: March 28, 2002Date of Patent: April 11, 2006Assignee: Intel CorporationInventor: Gad Sheaffer
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Patent number: 7003653Abstract: A method for rapidly mapping a bitmask returned by a Single Instruction Multiple Data (SIMD) computer compare instruction is provided. A user supplied partitioned mapping variable includes multiple mapping elements. Each of the multiple mapping elements is applied to the inputs of a different one of multiple digital multiplexers. The bitmask returned by the SIMD compare instruction is applied to the selects or all of the multiple digital multiplexers. Each multiplexer outputs one bit, as selected by the bitmask, from the respective mapping element applied to each multiplexer. The one bit outputs are accumulated in a mapped output variable as a mapped bitmask.Type: GrantFiled: October 21, 2002Date of Patent: February 21, 2006Assignee: Sun Microsystems, Inc.Inventor: Lawrence Spracklen
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Patent number: 6968446Abstract: A processor is configured to support a programmable flags masking during processing of a system call instruction such as Syscall. The processor includes a register storing a mask, where an indication within the mask corresponds to each of a plurality of flags used by the processor. Based on the state of the indication, the processor may clear a corresponding flag or may retain the value of the corresponding flag. By programming the register appropriately, the desired clearing and retaining of the plurality of flags may be performed as part of the system call instruction. Flexibility may be provided for different operating systems having different sets of flags to be preserved or cleared.Type: GrantFiled: August 9, 2001Date of Patent: November 22, 2005Assignee: Advanced Micro Devices, Inc.Inventor: Kevin J. McGrath
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Patent number: 6944753Abstract: A method for allowing a partial instruction to be executed in a fixed point unit pipeline during the instruction dispatch cycle creates a mask used to select which bits of the operands participate in a future logical operation of the fixed point unit back a cycle to the instruction dispatch stage of the fixed point unit. As an S/390 System improvement applicable to other computers, the mask is determined and created two cycles ahead of execution, or two cycles before the mask is actually used. Also, in the method used for moving the mask generation back by one cycle, mask generation overlaps the dispatch stage in the I-unit, and this provides a handshake between the I-unit and E-unit of the fixed point unit of the central processor unit of the computer system. The control setting selection process occurs in a predetermination cycle stage or e-1 (em1) stage for the mask generation and the register file read address.Type: GrantFiled: April 11, 2001Date of Patent: September 13, 2005Assignee: International Business Machines CorporationInventors: Fadi Y. Busaba, Christopher A. Krygowski, Wen H. Li
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Patent number: 6934828Abstract: A technique is described to reduce the complexity of floating point linear address (FLA) maintenance in a superscalar processor by coupling FLA updates when floating point data is stored instead of when floating point addresses are stored.Type: GrantFiled: September 17, 2002Date of Patent: August 23, 2005Assignee: Intel CorporationInventors: Rajesh S. Parthasarathy, Aravindh Bakthavathsalu
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Patent number: 6883087Abstract: Binary data is processed and organized by determining patterns specific for the binary data in a software package. Code sections may be split from an instruction according to the code section type or behavior. Certain of these code sections may be organized into specialized ordered lists. Furthermore, some code sections may be abbreviated and sections deleted. Dictionaries are used to store references for or values of the code sections. The processed data may be useful in subsequent compression techniques. In addition, other aspects of the present invention relating to the reducing the size and/or ordering the form of the binary data are described.Type: GrantFiled: December 15, 2000Date of Patent: April 19, 2005Assignee: Palm, Inc.Inventors: Pierre Raynaud-Richard, Cyril Meucillon, Jean-Baptiste Quéru
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Patent number: 6865644Abstract: A system and method for industrial control I/O forcing is provided. The invention includes a processor, shared memory and an I/O processor with cache memory. The invention provides for the cache memory to be loaded with I/O force data from the shared memory. The I/O processor performs I/O forcing utilizing the I/O force data stored in the cache memory. The invention further provides for the processor to notify the I/O processor in the event that I/O force data is altered during control program execution. The invention further provides for the I/O processor to refresh the cache memory (e.g., via a blocked write) after receipt of alteration of the I/O force data from the processor.Type: GrantFiled: July 25, 2001Date of Patent: March 8, 2005Assignee: Rockwell Automation Technologies, Inc.Inventors: Raymond R. Husted, Ronald E. Schultz, Dennis J. Dombrosky, David A. Karpuszka
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Patent number: 6834337Abstract: A system and method for data processing includes packing multiple signed data elements per register into a processor's registers using the rules set forth herein, and simultaneously operating on the elements in a register in a single cycle using the same operand. The elements can be independent of each other, and the sizes of the elements in a register can differ from each other. Moreover, a relatively large element can be split across multiple registers. In an exemplary application, a data stream representing two images can be simultaneously processed using the same number of registers as have been required to process a single image. Or, a single image can be processed approaching N-times faster, where N is the number of elements per register. In any case, the present invention results in a significant increase in processing efficiency.Type: GrantFiled: September 29, 2000Date of Patent: December 21, 2004Assignee: International Business Machines CorporationInventors: Joan Laverne Mitchell, Michael Thomas Brady, Jennifer Q. Trelewicz
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Publication number: 20040255100Abstract: Within a processor 2 providing single instruction multiple data (SIMD) type operation, single data processing instructions can serve to control processing logic 4, 6, 8, 10 to perform SIMD-type processing operations upon multiple independent input values to generate multiple independent result values having a greater data width than the corresponding input values. A repartitioner (FIG. 5) in the form of appropriately controlled multiplexers serves to partition these result data values into high order bit portions and low order bit portions that are stored into separate registers 38, 40. The required SIMD width preserved result values can be read from the desired high order 38 result register or low order result register 40 without further processing being required. Furthermore, the preservation of the full result facilitates improvements in accuracy, such as over extended accumulate operations and the like.Type: ApplicationFiled: June 16, 2003Publication date: December 16, 2004Applicant: ARM LIMITEDInventor: Daniel Kershaw
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Publication number: 20040243789Abstract: A system and method for processing multiple arbitrary sized data elements in a register. A method of the invention comprises the steps of: creating a mask register that defines a set of arbitrary sized segments for a register; storing a plurality of arbitrary sized data elements in a segmented data register arranged in accordance with the mask register, wherein the arbitrary sized data elements are sign extended; simultaneously operating on each of the of the data elements in the segmented data register to generate a set of resulting data elements in response to a machine instruction, wherein the resulting data elements depend on each other; and unpacking the resulting data elements to provide a plurality of arbitrary sized results that are independent of each other.Type: ApplicationFiled: May 27, 2003Publication date: December 2, 2004Applicant: International Business Machines CorporationInventors: Michael T. Brady, Jennifer Q. Trelewicz, Joan L. Mitchell
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Publication number: 20040210746Abstract: A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.Type: ApplicationFiled: January 15, 2004Publication date: October 21, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040205325Abstract: A system and software for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying both a mask and a register containing data, the mask comprising fields that each correspond to a field of the data contained in the register, the execution unit is operable to detect some of the fields of the mask as having a predetermined value and identifying corresponding fields of the data contained in the register as write-enabled data fields; and cause the write-enabled data fields to be written to a specified memory location.Type: ApplicationFiled: January 16, 2004Publication date: October 14, 2004Applicant: MICROUNITY SYSTEMS ENGINEERING, INC.Inventors: Craig Hansen, John Moussouris
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Publication number: 20040193848Abstract: Execution of a single stand-alone instruction manipulates two n bit strings of data to pack data or align the data. Decoding of the single instruction identifies two registers of n bits each and a shift value, preferably as parameters of the instruction. A first and a second subset of data of less than n bits are selected, by logical shifting, from the two registers, respectively, based solely upon the shift value. Then, the subsets are concatenated, preferably by a logical OR, to obtain an output of n bits. The output may be aligned data or packed data, particularly useful for performing a single operation on multiple sets of the data through parallel processing with a SIMD processor.Type: ApplicationFiled: March 31, 2003Publication date: September 30, 2004Applicant: Hitachi, Ltd.Inventor: Clifford Tavares
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Patent number: 6757820Abstract: A method and apparatus for performing single-instruction bit field extraction and for counting a number of leading zeros in a sequence of bits on a general purpose processor are provided. The fast bit extraction operations are accomplished by executing a first instruction for extracting an arbitrary number of bits of a sequence of bits stored in two or more source registers of the processor starting at an arbitrary offset and the storing the extracted bits in a destination register. Both the source and the destination registers are specified by the instruction. In addition, a second instruction is provided for counting the number of leading zeros in a sequence of bits stored in two or more source registers of the processor and then storing a binary value representing the number of leading zeros in a destination register. Again the source and the destination registers are specified by the second instruction.Type: GrantFiled: January 31, 2003Date of Patent: June 29, 2004Assignee: Sun Microsystems, Inc.Inventors: Subramania Sudharsanan, Jeffrey Meng Wah Chan, Marc Tremblay
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Patent number: 6757789Abstract: The present invention provides various techniques for optimized transfer of information in electronic systems involving memory devices to improve data bandwidth. The invention offers solutions to the problem of packing all of the required information including data, control and address information over a limited number of interconnect lines in an optimized fashion. In one embodiment, the present invention combines different control information, such as row address and bank address information into a unified address field wherein one or more bits can be shared. By sharing bits across various address fields, the present invention conserves bandwidth that is required by the control signals. In another embodiment, the present invention provides various schemes for defining and constructing packets of information that maximize the amount of information carried by a given packet across a limited number of interconnect lines.Type: GrantFiled: January 30, 2002Date of Patent: June 29, 2004Assignee: Rambus, Inc.Inventors: Abhijit M. Abhyankar, Frederick A. Ware, Donald C. Stark, Craig E. Hampel, Paul G. Davis
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Publication number: 20040123079Abstract: An electronic system (2001) for manipulating an input data argument (D[31:0]) comprising an integer number of bits. The system comprises an input (R) for receiving a right direction argument and an input (L) for receiving a left direction argument. The system also comprises circuitry (200) for producing a first data output having the integer number of bits by rotating the input data argument in response to the first direction argument and the second direction argument. The system also comprises circuitry for providing a modified data output (502). The circuitry for providing comprises circuitry for selecting a first set of bits from the first data output as a first portion of the modified data output and circuitry for providing a second set of bits from a source other than the first data output as a second portion of the modified data output.Type: ApplicationFiled: December 20, 2002Publication date: June 24, 2004Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: Patrick W. Bosshart
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Patent number: 6748521Abstract: A data processing system is provided with a digital signal processor which has an instruction for saturating multiple fields of a selected set of source operands and storing the separate saturated results in a selected destination register. A first 32-bit operand (600) and a second 32-bit operand (602) are treated as four 16-bit fields and the sixteen bits in each field are saturated separately. Multi-field saturation circuitry is operable to treat a source operand as a number of fields, such that a multi-field saturated (610) result is produced that includes a number of saturated results each corresponding to each field. One instruction is provided which treats an operand pair as having two packed fields, and another instruction is provided that treats the operand pair has having four packed fields. Saturation circuitry is operable to selectively treat a field as either a signed value or an unsigned value.Type: GrantFiled: October 31, 2000Date of Patent: June 8, 2004Assignee: Texas Instruments IncorporatedInventor: David Hoyle
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Patent number: 6745319Abstract: A data processing system is provided with a digital signal processor (DSP) which has a shuffle instruction for shuffling a source operand (600) and storing the shuffled result in a selected destination register (610). A shuffled result is formed by interleaving bits from a first source operand portion with bits from a second operand portion. A de-interleave and pack (DEAL) instruction is provided for de-interleaving a source operand. The shuffle instruction and the DEAL instruction have an exactly inverse effect. The DSP includes swizzle circuitry that performs interleaving or de-interleaving in a single execution phase.Type: GrantFiled: October 31, 2000Date of Patent: June 1, 2004Assignee: Texas Instruments IncorporatedInventors: Keith Balmer, David Hoyle, Lewis Nardini
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Patent number: 6738792Abstract: A mask generator circuit includes at least first and second mask generator circuits coupled to receive most significant and least significant sections of the pointer and to generate masks therefrom, and a plurality of circuits each configured to generate a region of the output mask from the mask generator circuit. The mask generated from the most significant bits section of the pointer (the most significant bits (MSB) mask) includes bits corresponding to various regions of the output mask. The plurality of circuits receive the MSB mask and the least significant bits (LSB) mask generated from the least significant bits section of the pointer and generate the output mask therefrom.Type: GrantFiled: March 9, 2001Date of Patent: May 18, 2004Assignee: Advanced Micro Devices, Inc.Inventor: Karthikeyan Muthusamy
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Patent number: 6718456Abstract: Disclosed herein is a apparatus and method for packing a 16-bit number into an 8-bit result byte. The method and apparatus utilize a parallel processing right shift circuit and a filter to obtain desired results. The parallel processes are comprised of a plurality of multiplexers capable of discretely analyzing smaller groups of bits. In this manner, higher throughput may be obtained than previously known.Type: GrantFiled: June 2, 2000Date of Patent: April 6, 2004Assignee: Sun Microsystems, Inc.Inventor: Michael Ott
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Patent number: 6715066Abstract: A system is described for rearranging data units of a data word in accordance with a mask word, the mask word having a plurality of mask bits each associated with a data unit, each mask bit having one of a set condition or a clear condition. The system includes a control module and a shifter module. The control module is configured to generate, for each mask bit, values identifying the number of mask bits to the left of the respective mask bit which have one of the set condition or the clear condition and the number of mask bits to the right of the respective mask bit which have the other of the set condition or the clear condition. The shifter module is configured to shift data units of the data word in accordance with the values generated by the control module.Type: GrantFiled: April 7, 2000Date of Patent: March 30, 2004Assignee: Sun Microsystems, Inc.Inventor: Guy L. Steele, Jr.
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Patent number: 6691240Abstract: A method for implementing a variable length delay instruction includes the steps of designating a source register for holding information and designating a destination register for retrieving the information. A first number of cycles before retrieval of the information to the destination register then is determined, and the information is transferred from the source register to delaying device, such as queuing device, for the first number of cycles. Finally, the information is written from the delaying device to the destination register. An apparatus for implementing variable length delay instructions includes an input line for reading information from a source register; delaying device for receiving said information read from the source register; a multiplexer; and a select line. A trigger signal is transmitted to the multiplexer, thereby instructing the multiplexer to write the information to a destination register.Type: GrantFiled: October 31, 2000Date of Patent: February 10, 2004Assignee: Texas Instruments IncorporatedInventors: Eric J. Stotzer, David Hoyle, Joseph Zbiciak
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Patent number: 6691222Abstract: A system and method of executing instructions within a counterflow pipeline processor. The counterflow pipeline processor includes an instruction pipeline, a data pipeline, a reorder buffer and a plurality of execution units. An instruction and one or more operands issue into the instruction pipeline and a determination is made at one of the execution units whether the instruction is ready for execution. If so, the operands are loaded into the execution unit and the instruction executes. The execution unit is monitored for a result and, when the result arrives, it is stored into the result pipeline. If the instruction reaches the end of the pipeline without executing it wraps around and is sent down the instruction pipeline again.Type: GrantFiled: March 18, 2003Date of Patent: February 10, 2004Assignee: Intel CorporationInventors: Kenneth J. Janik, Shih-Lien L. Lu, Michael F. Miller
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Patent number: 6691308Abstract: A Central Processing Unit (CPU) hotpatch circuit compares the run-time instruction stream against an internal cache. The internal cache stores embedded memory addresses with associated control flags, executable instruction codes, and tag information. In the event that a comparison against the current program counter succeeds, then execution is altered as required per the control flags. If no comparison match is made, then execution of the instruction that was accessed by the program counter is executed.Type: GrantFiled: December 30, 1999Date of Patent: February 10, 2004Assignee: STMicroelectronics, Inc.Inventor: Christian D. Kasper
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Patent number: 6671797Abstract: A data processing system is provided with a digital signal processor which has an instruction for expanding one bit to form a mask field. In one form of the instruction, a first bit from a two-bit mask in a source operand is replicated and placed in an least significant half word of a destination operand while a second bit from the two-bit mask in the source operand is replicated and placed in a most significant half word of the destination operand. In another form of the instruction, a first bit from a four bit mask in a source operand is replicated and placed in a least significant byte of a destination operand, a second bit from the four-bit mask in the source operand is replicated and placed in a second least significant byte of the destination operand, a third bit from the four-bit mask is replicated and placed in a second most significant byte of the destination operand and a fourth bit form the four-bit mask is replicated and placed in a most significant byte of the destination operand.Type: GrantFiled: October 31, 2000Date of Patent: December 30, 2003Assignee: Texas Instruments IncorporatedInventor: Jeremiah E. Golston
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Patent number: 6658448Abstract: A method in a multi-processor computing system is disclosed. The method is an object-oriented method that allows a user to make associations between processes to be executed and available CPUs of the system. In particular, the method includes the displaying of the associations for a user to manipulate. Responses are accepted by the method from a user for creating logical groupings of the CPUs, hereinafter referred to as affinity groups. Next, an affinity mask is accepted from the user for each of the affinity groups, which affinity mask assigns available ones of the CPUs. After this a determination is made as to whether or not there are more CPUs to be assigned to the affinity groups, and if not; specific rules that make associations between the processes and the affinity groups are then accepted by the method from the user.Type: GrantFiled: October 21, 1999Date of Patent: December 2, 2003Assignee: Unisys CorporationInventors: Joseph Peter Stefaniak, Philip Douglas Wilson
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Publication number: 20030217250Abstract: In one embodiment, a command pertaining to one or more portions of a register is received from guest software. Further, a determination is made as to whether the guest software has access to all of the requested portions of the register based on indicators within a mask field that correspond to the requested portions of the register. If the guest software has access to all of the requested portions of the register, the command received from the guest software is executed on the requested portions of the register.Type: ApplicationFiled: April 16, 2002Publication date: November 20, 2003Inventors: Steve Bennett, Andrew V. Anderson, Erik Cota-Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Gilbert Neiger, Richard Uhlig, Michael A. Kozuch
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Patent number: 6629239Abstract: A system is described for rearranging an input data word in relation to a mask word, the data word comprising a plurality of input data units in a series of input data unit positions, each associated with a respective one of a plurality of bits of the mask word in a series of mask bit positions, each mask bit having one of a plurality of conditions, to provide an output data word comprising a plurality of output data units in a series of output data unit positions. The system comprises a control module and a shift module. The control module is configured to identify, for each output data unit position, the number of bits in bit positions in the mask word to one end of that bit position which have one of the conditions, and the number of bits in bit positions to another end of the mask word have another of the conditions.Type: GrantFiled: April 7, 2000Date of Patent: September 30, 2003Assignee: Sun Microsystems, Inc.Inventor: Guy L. Steele, Jr.
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Publication number: 20030172254Abstract: A method of operating a processor core provides of instructions for copying data from one general purpose register to another general purpose register. A conditional move instruction provides for conditional copying of bits from a source register into a destination based on corresponding bits in a control register. A permute instruction provides for arbitrary permutations based on a control register.Type: ApplicationFiled: February 4, 2003Publication date: September 11, 2003Applicant: Hitachi, Ltd.Inventors: Srinivas Mandavilli, Arindam Saha
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Patent number: 6618804Abstract: A system is disclosed for rearranging data units of a data word in accordance with a mask word, the mask word having a plurality of mask bits each associated with a data unit, each mask bit having one of a set condition and a clear condition. The system includes an array of interconnected swap modules organized in a series of swap stages, each swap module having two inputs and two outputs. Each swap module is configured to receive at each input a data unit and associated mask bits and couple the data units to the respective outputs in relation to the associated mask bit's condition.Type: GrantFiled: April 7, 2000Date of Patent: September 9, 2003Assignee: Sun Microsystems, Inc.Inventors: Guy L. Steele, Jr., Peter Lawrence
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Patent number: 6591357Abstract: A method and an apparatus for configuring arbitrary sized data paths comprising multiple context processing elements (MCPEs) are provided. Multiple MCPEs may be chained to form wider-word data paths of arbitrary widths, wherein a first ALU serves as the most significant byte (MSB) of the data path while a second ALU serves as the least significant byte (LSB) of the data path. The ALUs of the data path are coupled using a left-going, or forward, carry chain for transmitting at least one carry bit from the LSB ALU to the MSB ALU. The MSB ALU comprises configurable logic for generating at least one signal in response to a carry bit received over the left-going carry chain, the at least one signal comprising a saturation signal and a saturation value. The MCPEs of the data path use configurable logic to manipulate a resident bit sequence in response to the saturation signal transmitted thereby reconfiguring, or changing the operation of, the data path in response to he saturation signal.Type: GrantFiled: February 26, 2001Date of Patent: July 8, 2003Assignee: Broadcom CorporationInventor: Ethan A. Mirsky
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Patent number: 6587939Abstract: An information processing apparatus is provided with a executable instruction extracting unit which is reconfigured by means of a executable instruction extracting unit reconfiguration unit with reference to a compressed/executable instruction correspondence table optimized for the respective executable program, which has been made up with an compressed instruction. The compressed instruction is extended into the corresponding executable instructions by means of the executable instruction extracting unit as reconfigured.Type: GrantFiled: January 13, 2000Date of Patent: July 1, 2003Assignee: Kabushiki Kaisha ToshibaInventor: Hiroyuki Takano
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Publication number: 20030105945Abstract: Techniques for performing a bit rake instruction in a programmable processor. The bit rake instruction extracts an arbitrary pattern of bits from a source register, based on a mask provided in another register, and packs and right justifies the bits into a target register. The bit rake instruction allows any set of bits from the source register to be packed together.Type: ApplicationFiled: October 29, 2002Publication date: June 5, 2003Applicant: BOPS, Inc.Inventors: Edward A. Wolff, Peter R. Molnar, Ayman Elezabi, Gerald George Pechanek
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Patent number: 6574702Abstract: A method and apparatus for determining an exact match in a ternary CAM device. Each ternary CAM cell includes CAM cells for storing CAM data, local mask cells for storing prefix mask data for the corresponding CAM cells, and a mask override circuit. Each local mask cell includes a masking circuit that masks the prefix mask data or CAM data provided to the comparison circuit, or masks the comparison result from the match line of a CAM cell. The mask override circuit effectively overrides the prefix mask data stored in the local mask cell. The mask override circuit performs the override function by negating the operation of the mask circuit such that no masking operation occurs when an exact match compare or invalidate function is performed by the ternary CAM device. For example, during an exact match operation, the CAM cells compare comparand data with unmasked CAM data and provide the compare results to CAM match lines.Type: GrantFiled: May 9, 2002Date of Patent: June 3, 2003Assignee: NetLogic Microsystems, Inc.Inventors: Sandeep Khanna, Bindiganavale S. Nataraj, Varadarajan Srinivasan
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Patent number: 6560698Abstract: A microcontroller provides a register change summary resource for summarizing register changes. Selected system registers within each resource are coupled to bits in resource change registers of the register change summary resource using logic that tracks accesses to the system registers. Each resource change register is coupled to a bit in a summary register. For systems with numerous system registers, each summary register may be coupled to a bit in a higher-level summary register. The register change summary resource further provides a software-controlled bit mask register. A change in a summary or resource change register may trigger a processor interrupt. Each register in the register change summary resource can be reset, also under software control. The registers within the register change summary resource are accessible through a dedicated software development port.Type: GrantFiled: May 7, 1999Date of Patent: May 6, 2003Assignee: Advanced Micro Devices, Inc.Inventor: Daniel P. Mann
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Publication number: 20030041229Abstract: The present invention is a technique to perform field operations. A shifter to shifts an operand. A register stores the shifted operand. A shift post processor processes the shifted operand based on at least a control signal and an offset parameter.Type: ApplicationFiled: August 20, 2001Publication date: February 27, 2003Inventor: Sam B Sandbote