Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.

Abstract: An apparatus and method are provided for making predictions for instruction flow changing instructions. The apparatus has a fetch queue that identifies a sequence of instructions to be fetched for execution by execution circuitry, and prediction circuitry for making predictions in respect of instruction flow changing instructions, and for controlling which instructions are identified in the fetch queue in dependence on the predictions. The prediction circuitry has a target prediction storage used to identify target addresses for instruction flow changing instructions that are predicted as taken.

Abstract: In one embodiment, a branch processing method, comprising: assigning plural branch instructions for a given clock cycle to primary branch information and secondary branch information; routing the primary branch information along a first path having adder logic and the secondary branch information along a second path having no adder logic; and writing the primary branch information including a displacement branch target address to a branch order table (BOT) and the secondary branch information without a target address to the BOT.

Abstract: Disclosed herein are vector index registers for storing or loading indexes of true and/or false results of conditional operations using multiple lane processing in vector processors. Each of the vector index registers store multiple addresses for accessing multiple positions in operand vectors in various types of operations that can leverage multi-lane processing.

Abstract: In filtering requests to be forwarded to a runtime environment, a filtering apparatus intercepts a new runtime request for the runtime environment and determines execution paths that may be traversed by the runtime request when executed in the runtime environment. The filtering apparatus assigns a probability of traversal by the runtime request to each of the execution paths and identifies at least one given execution path that reference a stressed resource of the runtime environment. Based on the probabilities assigned to the at least one given execution path, the filtering apparatus determines whether or not to block the runtime request from being sent to the runtime environment. If the probability assigned to the at least one given execution path exceeds a configured threshold, the runtime request is blocked from being sent to the runtime environment. Otherwise, the runtime request is sent to the runtime environment.

Abstract: Systems and methods are provided for receiving a request for documentation related to functionality of an application, accessing a test automate generated from a recording of actions using the functionality of the application, and parsing the test automate to determine one or more steps in a process and, for each step in the process, a list of the actions for the step and corresponding data. The system and methods further provide for generating a file comprising the one or more steps and the list of actions and corresponding data for each step, determining a selected template for generating documentation for the functionality of the application and generating a populated template by populating one or more steps and corresponding list of actions in the selected template using the file comprising the one or more steps and the list of actions and corresponding data for each step.

Abstract: The present disclosure meets demand to realize control computations according to programs having different execution formats by a single control device. The control device includes a storage unit storing a first program to be scanned as a whole for each execution and a second program that is sequentially executed, an execution processing unit computing a first command value by executing the first program at every predetermined control cycle, an interpreter interpreting at least a part of the second program and generating an intermediate code, a command value computation unit computing a second command value at every control cycle according to the intermediate code generated in advance by the interpreter, and an output unit outputting the first command value computed by the execution processing unit and the second command value computed by the command value computation unit at every control cycle.

Abstract: Embodiments relate to branch prediction using a pattern history table (PHT) that is indexed using a global path vector (GPV). An aspect includes receiving a search address by a branch prediction logic that is in communication with the PHT and the GPV. Another aspect includes starting with the search address, simultaneously determining a plurality of branch predictions by the branch prediction logic based on the PHT, wherein the plurality of branch predictions comprises one of: (i) at least one not taken prediction and a single taken prediction, and (ii) a plurality of not taken predictions. Another aspect includes updating the GPV by shifting an instruction identifier of a branch instruction associated with a taken prediction into the GPV, wherein the GPV is not updated based on any not taken prediction.

Abstract: Reconfiguring execution pipelines of out-of-order (OOO) computer processors based on phase training and prediction is disclosed. In one aspect, a pipeline reconfiguration circuit is communicatively coupled to an execution pipeline providing multiple selectable pipeline configurations. The pipeline reconfiguration circuit generates a phase identifier (ID) for a phase based on a preceding phase. The phase ID is used as an index into an entry of a pipeline configuration prediction (PCP) table to determine whether training for the phase is ongoing. If so, the pipeline reconfiguration circuit performs multiple training cycles, each employing a pipeline configuration from the selectable pipeline configurations for the execution pipeline, to determine a preferred pipeline configuration for the phase. If training for the phase is complete, the pipeline reconfiguration circuit reconfigures the execution pipeline into the preferred pipeline configuration indicated by the entry before the phase is executed.

Abstract: An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. For example, one embodiment of a processor comprises: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB.

Abstract: Embodiments relate to branch prediction using a pattern history table (PHT) that is indexed using a global path vector (GPV). An aspect includes receiving a search address by a branch prediction logic that is in communication with the PHT and the GPV. Another aspect includes starting with the search address, simultaneously determining a plurality of branch predictions by the branch prediction logic based on the PHT, wherein the plurality of branch predictions comprises one of: (i) at least one not taken prediction and a single taken prediction, and (ii) a plurality of not taken predictions. Another aspect includes updating the GPV by shifting an instruction identifier of a branch instruction associated with a taken prediction into the GPV, wherein the GPV is not updated based on any not taken prediction.

Abstract: A system, method, and computer program product are provided for defining and utilizing minimal testable values for software project development and operations. In operation, a system identifies a software development project. The system defines an initial list of minimal testable values (MTVs) as part of a backlog definition stage associated with a project backlog corresponding to the software development project. The system links the MTVs to the project backlog. The system confirms the MTVs as part of a backlog confirmation stage associated with the software development project. Further, the system maintains the MTVs during a backlog grooming stage associated with the software development project. Moreover, the system certifies the MTVs after each delivery of software associated with the software development project.

Abstract: A data processing system supporting execution of transactions comprising one or more program instructions that execute to generate speculative updates is provided. The speculative updates are committed in normal operation if the transaction completes without a conflict. Start of execution of a transaction may be detected and execution diverted to be performed by software emulation rather than direct execution by the processing hardware. The software emulation may store data representing one or more versions of the speculative updates generated during the emulation. The software emulation may also detect conflicts with the transaction being emulated. In order to facilitate modifying the behaviour of other parts of the system interacting with a transaction under investigation, a non-standard response signal may be returned in response to a detected memory access request to a transaction being emulated.

Abstract: An apparatus includes a processor and a loop cache coupled to the processor. The loop cache provides to the processor instructions corresponding to a loop in the instructions. The loop cache includes a persistence counter.

Abstract: Technologies for assembling an execution profile of an event are disclosed. The technologies may include monitoring the event for a branch instruction, generating a callback to a security module upon execution of the branch instruction, filtering the callback according to a plurality of event identifiers, and validating a code segment associated with the branch instruction, the code segment including code executed before the branch instruction and code executed after the branch instruction.

Abstract: Provided are a computer program product, system, and method for embedding and executing trace functions in code to gather trace data. A plurality of trace functions are embedded in the code. For each embedded trace function, a trace level is included indicating code to which the trace applies. The trace level comprises one of a plurality of levels. During the execution of the code, the embedded trace functions having one of the levels associated with a specified at least one level specified are executed. The embedded trace functions associated with at least one level not comprising one of the at least one specified level are not invoked.

Abstract: An apparatus and method are described for performing conflict detection operations. For example, one embodiment of a processor comprises: a first source vector register to store a first set of data elements; a second source vector register to store a second set of data elements; conflict detection logic to perform a specified comparison operation comparing each of the first set of data elements with specified data elements from the second set and generating a set of comparison results, the comparison operation to be selected from a group consisting of a greater than comparison, a less than comparison, a greater than or equal to comparison, a less than or equal to comparison, and a not equal to comparison.

Abstract: An apparatus and method for a dual return stack buffer (RSB) for use in binary translation systems. An embodiment of a processor includes: a dual return stack buffer (DRSB) comprising a native RSB and an extended RSB (XRSB), the dual RSB to be used within a binary translation execution environment in which guest call-return instruction sequences are translated to native call-return instruction sequences to be executed directly by the processor; the native RSB to store native return addresses associated with the native call-return instruction sequences; and the XRSB to store emulated return addresses associated with the guest call-return instruction sequences, wherein each native return address stored in the RSB is associated with an emulated return address stored in the XRSB.

Abstract: The data processor includes CPU operable to execute an instruction included in an instruction set. The instruction set includes a load instruction for reading data on a memory space. The data read according to the load instruction includes data of a format type having a data-read-branching-occurrence bit region. The CPU includes a data-read-branching control register; a data-read-branching address register; and a read-data-analyzing unit. On condition that a bit value showing the occurrence of data read branching has been set on the data-read-branching-occurrence bit region, and a value showing the data-read-branching-occurrence bit remaining valid has been set on the data-read-branching control register, the switching between processes is performed by branching to an address stored in the data-read-branching address register.

Abstract: Embodiments relate to fingerprint-based branch prediction. An aspect includes based on encountering a branch instruction during execution of software on a processor of a computer system, determining a fingerprint of the software, the fingerprint comprising a representation of a sequence of behavior that occurs in the processor while the software is executing. Another aspect includes based on determining that a match for the fingerprint and the branch instruction is located in an entry in the prediction table: predicting the branch instruction according to the associated prediction field. Another aspect includes based on determining that no match for the fingerprint and the branch instruction are located in an entry in the prediction table: creating a new entry in the prediction table for the fingerprint and the branch instruction.

Abstract: An image processing apparatus is provided. A splitting unit of the image processing apparatus may split a first space within an input three-dimensional (3D) model into a plurality of subspaces in order to generate an acceleration structure of the input 3D model. A decision unit of the image processing apparatus may set a subspace determined as having a relatively high probability of including a ray progress path among the plurality of subspaces, as a child node having a relatively high traversal priority in the acceleration structure among a plurality of child nodes.

Abstract: A processor includes a loop counter that is reset to 0 when a loop instruction for executing a process in a loop from a loop start address to a loop end address is issued, a data memory that receives data that is used for executing a process in the loop, in which the data is transferred from outside, a calculator that uses the data transferred to the data memory to execute the process in the loop, a data counter that increments the loop counter by 1 every time a certain amount of data that is used for executing a process in the loop is transferred from outside to a data memory, and a loop controller that decrements the loop counter by 1 and causes the calculator to execute the process in the loop when a loop count value of the loop counter is not 0.

Abstract: One embodiment is a computer-implemented method for safe conditional operation when storage access cannot be proven safe. The method includes receiving a portion of source code for a transaction by an enhanced compiler and. The portion of source code received is analyzed, by the enhanced compiler, to determine whether the portion of source code is a candidate for transformation. Responsive to a determination that the portion of source code analyzed by the enhanced compiler is a candidate for transformation, the portion of the source code analyzed is transformed, by a computer processor, to use a conditional operation in a first portion of the transformed code. The conditional operation uses hardware transaction memory to invoke retry operations within hardware. A branch is added, directed to an original code portion, in a second portion of transformed code, where the branch is a recovery portion containing the original code portion.

Abstract: Exemplary methods, apparatuses, and systems generate a plurality of possible branch traces for a computer program. Each possible branch trace represents different sequences of branch instructions that may be executed while the computer program is running. Each branch instruction has a corresponding identifier. A branch trace value is generated for at least one of the plurality of possible branch traces. Generating the branch trace value includes performing a mathematical or logical operation between a first identifier and each subsequent identifier of the possible branch trace to obtain the branch trace value. An output including a branch trace is generated based upon a match between a run-time branch trace value and the at least one generated branch trace value.

Abstract: A system comprises a plurality of computation units interconnected by an interconnection network.

Abstract: A method and apparatus for branch reduction in a multithreaded packet processor is presented. An instruction is executed which includes testing of a branch flag. The branch flag references a configuration bit vector wherein each bit in the configuration bit vector corresponds to a respective feature. When said branch flag returns a first result processing is continues at an instruction located at a first location relative to a Program Counter (PC) and when the branch flag returns a second result processing is continued at a second location relative to said PC.

Abstract: A method and system for automatically enforcing a hybrid branching strategy include receiving a changeset designated for a branch. In response to receiving the changeset, the system may automatically determine whether a merge conflict associated with the changeset exists between the branch and an associated protected branch, and the system may automatically determine whether the changeset is up to date. Upon determining that no merge conflict exists, the system automatically initiates execution of a continuous integration testing pipeline. The continuous integration testing pipeline includes a series of tests applied to the changeset. If the changeset passes the series of tests, the system automatically merges the changeset with the associated protected branch.

Abstract: A data processing apparatus is provided comprising prediction circuitry for predicting a response of the data processing circuitry at at least one given execution point to execution of a program instruction; tracing circuitry for tracing operation of the data processing apparatus for outputting a prediction indicator indicating whether or not the predicted response is correct; a data store configured to store information relating to the predicted response of said data processing circuitry at the given execution point for use by at least one of said prediction logic and said tracing circuitry a later execution point; and a history buffer configured to store historical information with regard to one or more entries of the data store at a corresponding execution point previous to the given execution point to enable restoration of said data store to a state corresponding to said previous execution point.

Abstract: One embodiment of the present invention sets forth a mechanism for managing thread divergence in a thread group executing a multithreaded processor. A unanimous branch instruction, when executed, causes all the active threads in the thread group to branch only when each thread in the thread group agrees to take the branch. In such a manner, thread divergence is eliminated. A branch-any instruction, when executed, causes all the active threads in the thread group to branch when at least one thread in the thread group agrees to take the branch.

Abstract: The invention provides an image processing device, an image processing method, and an image processing program which enable accurately observing a moving image of an object within a time interval within which the object is in a desired state. A control unit performs an analysis process after the elapse of every defined time period. As the analysis process, the control unit acquires evaluation values corresponding to image data of a plurality of frames stored within a latest defined time period and, based on the acquired evaluation values, selects a group of reproduction data formed from image data of a certain number of frames, out of the image data of the plurality of frames stored within the latest defined time period. After the completion of the analysis process, the control unit starts reproduction of a moving image based on the group of reproduction data selected through the analysis process.

Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.

Abstract: Methods and systems for performing control of flow in a graphics processor architecture are provided. For example, in at least one embodiment, a computing system includes a memory storing a plurality of instructions and a graphics processing unit. The graphics processing unit is configured to process the instructions according to a multi-stage scalar pipeline and store condition code values in the branch control stack. The graphics processing unit is further configured to process branch instructions using condition code values stored in the condition register at the top of the branch control stack.

Abstract: Processes requiring access to shared resources are adapted to issue a reservation request, such that a place in a resource access queue, such as one administered by means of a semaphore system, can be reserved for the process. The reservation is issued by a Reservation Management module at a time calculated to ensure that the reservation reaches the head of the queue as closely as possible to the moment at which the process actually needs access to the resource. The calculation may be made on the basis of priority information concerning the process itself, and statistical information gathered concerning historical performance of the queue.

Abstract: Processes requiring access to shared resources are adapted to issue a reservation request, such that a place in a resource access queue, such as one administered by means of a semaphore system, can be reserved for the process. The reservation is issued by a Reservation Management module at a time calculated to ensure that the reservation reaches the head of the queue as closely as possible to the moment at which the process actually needs access to the resource. The calculation may be made on the basis of priority information concerning the process itself, and statistical information gathered concerning historical performance of the queue.

Abstract: A test code generation technique that replaces instructions having a machine state dependent result with special redirection instructions provides generation of test code in which state dependent execution choices are made without a state model. Redirection instructions cause execution of a handler than examines the machine state and replaces the redirection instruction with a replacement instruction having a desired result resolved in accordance with the current machine state. The instructions that are replaced may be conditional branch instructions and the result a desired execution path. The examination of the machine state permits determination of a branch condition for the replacement instruction so that the next pass of the test code executes along the desired path. Alternatively, the handler can execute a jump to the branch instruction, causing immediate execution of the desired branch path.

Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

Abstract: A data processing apparatus is disclosed including trace logic for monitoring behavior of a portion of said data processing apparatus and prediction logic for providing at least one prediction as to at least one step of the behavior of the portion of the data processing apparatus. The trace logic monitors behavior of the portion of the data processing apparatus, determines from the monitored behavior whether the at least one prediction is correct, and outputs a prediction indicator indicating whether the at least one prediction is correct.

Abstract: The computer system of the present invention emulates target instructions. The computer system includes a processing unit for branching to collective emulation coding for emulating plural of target instructions created beforehand collectively, thereby processing those instructions collectively according to the coding when those target instructions are combined so as to be processed collectively and a memory for storing the collective emulation coding.

Abstract: A system and method for automatically optimizing parallel execution of multiple work units in a processor by reducing a number of branch instructions. A computing system includes a first processor core with a general-purpose micro-architecture and a second processor core with a same instruction multiple data (SIMD) micro-architecture. A compiler detects and evaluates branches within function calls with one or more records of data used to determine one or more outcomes. Multiple compute sub-kernels are generated, each comprising code from the function corresponding to a unique outcome of the branch. Multiple work units are produced by assigning one or more records of data corresponding to a given outcome of the branch to one of the multiple compute sub-kernels associated with the given outcome. The branch is removed. An operating system scheduler schedules each of the one or more compute sub-kernels to the first processor core or to the second processor core.

Abstract: Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.

Abstract: A method and apparatus for executing branch instructions is provided. In one embodiment, the method includes receiving a branch instruction, wherein a first path of the branch instruction branches to a target instruction, and wherein a second path of the branch instruction branches to one or more interceding instructions between the branch instruction and the target instruction. The method further includes issuing the one or more interceding instructions and the target instruction and determining if the branch instruction follows the first path or the second path. Upon determining that the branch instruction follows the first path, the one or more interceding instructions between the branch instruction and the target instruction are invalidated.

Abstract: General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program written in a high-level language are automatically translated into a distributed execution plan. Map and reduction computations are automatically added to the plan. Patterns in the sequential program can be automatically identified to trigger map and reduction processing. Direct invocation of map and reduction processing is also provided. One or more portions of the reduce computation are pushed to the map stage and dynamic aggregation is inserted when possible. The system automatically identifies opportunities for partial reductions and aggregation, but also provides a set of extensions in a high-level computing language for the generation and optimization of the distributed execution plan. The extensions include annotations to declare functions suitable for these optimizations.

Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.

Abstract: Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.

Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

Abstract: Methods and systems consistent with the present invention provide a programmable table which allows software to define a plurality of branching functions, each of which maps a vector of condition codes to a branch offset. This technique allows for a flexible multi-way branching functionality, using a conditional branch outcome table that can be specified by a programmer. Any instruction can specify the evaluation of arbitrary conditional expressions to compute the values for the condition codes, and can choose a particular branching function. When the processor executes the instruction, the processor's arithmetic/logical functional units evaluate the conditional expressions and then the processor performs the branch operation, according to the specified branching function.

Abstract: A microprocessor includes an architectural register and a non-architectural register, each having a plurality of condition code flags. A first instruction of the microarchitectural instruction set of the microprocessor instructs the microprocessor to update the plurality of condition code flags based on a result of the first instruction. The first instruction includes a field for indicating whether to update the plurality of condition code flags of the architectural or non-architectural register. A second instruction of the microarchitectural instruction set instructs the microprocessor to conditionally perform an operation based on one of the plurality of condition code flags. The second instruction includes a field for indicating whether to use the one of the plurality of condition code flags of the architectural or non-architectural register to determine whether to perform the operation.

Abstract: An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register has a guard input which allows the ALU to write a result to the register upon receipt of a selection signal at the guard input. A lookup table is dynamically programmed with logic to implement an upcoming branching portion of program code. Upon evaluation of the branch conditions of the branching portion of code, the lookup table outputs a selection signal for writing the correct results of the branching portion of code based on the evaluation of the branch condition statements and the truth table programmed into the lookup table to the result register.

Abstract: Described herein is technology for, among other things, enabling use of custom expressions in a rules engine. The rules engine may be used in conjunction with a workflow. The technology involves providing a custom expression with access to validation context and execution context of the workflow. The custom expression can then participate in rules engine validation and execution. Furthermore, the technology allows for variables of the custom expression to be analyzed so that the rules engine can discover the variable dependencies of the custom expression and any side effects that drive forward chaining.

Abstract: A processing apparatus is arranged to execute multiple-instruction words, a multiple-instruction word having a plurality of instructions. The processing apparatus comprises a plurality of issue slots (IS1, IS2) arranged for parallel execution of the plurality of instructions; a register file (RF1, RF2) accessible by the plurality of issue slots, and a communication network (CN) for coupling of the plurality of issue slots and the register file. The processing apparatus is further arranged to produce a first identifier (OV1) on the validity of first result data (RD1) produced by a first issue slot (IS1) and a second identifier (OV2) on the validity of second result data (RD2) produced by a second issue slot (IS2). The communication network comprises at least one selection circuit (SC1) arranged to dynamically control the transfer of either the first result data or the second result data to a register of the register file, in a single processor cycle, by using the first identifier and the second identifier.