Abstract: A microprocessor is provided with an instruction fetch mechanism that simultaneously predicts multiple control-flow instructions. The instruction fetch unit further is capable of handling multiple types of control-flow instructions. The instruction fetch unit uses predecode data and branch prediction data to select the next instruction fetch bundle address. If a branch misprediction is detected, a corrected branch target address is selected as the next fetch bundle address. If no branch misprediction occurs and the current fetch bundle includes a taken control-flow instruction, then the next fetch bundle address is selected based on the type of control-flow instruction detected. If the first taken control-flow instruction is a return instruction, a return address from the return address stack is selected as the next fetch bundle address.

Abstract: An information processing apparatus and method, such that when an interruption occurs in a microprocessor, an exception processing sequence control is started, a program condition of an interrupted program and an address of the interrupted program are saved in a RAM, a program address of a jump instruction is read out from an exception processing generating source and is set in a program counter, and the exception processing sequence control is stopped. Thereafter, a normal processing sequence control is started, the jump instruction is read out from a ROM, an address of an exception processing vector is calculated according to the jump instruction, the exception processing vector is read out from the ROM, a branch address of an exception processing routine indicated by the exception processing vector is set in the program counter, and an operation state of the microprocessor is branched to the exception processing routine.