Abstract: The electronic circuit contains a plurality of processing elements (10), which are supplied with instructions under control of a common program flow, typically for SIMD operation wherein the same instructions are applied to all processing elements and different operand data of the instructions to respective ones of the processing elements (10). Under control of the instructions each processing element (10) determines, whether an operand data dependent condition has occurred. The processing element outputs a condition signal dependent on said determination. The condition signals are summed to form a sum signal. Program flow is controlled by a conditional jump dependent on a value represented by the sum signal.

Abstract: A predication technique for out-of-order instruction processing provides efficient out-of-order execution with low hardware overhead. A special op-code demarks unified regions of program code that contain predicated instructions that depend on the resolution of a condition. Field(s) or operand(s) associated with the special op-code indicate the number of instructions that follow the op-code and also contain an indication of the association of each instruction with its corresponding conditional path. Each conditional register write in a region has a corresponding register write for each conditional path, with additional register writes inserted by the compiler if symmetry is not already present, forming a coupled set of register writes. Therefore, a unified instruction stream can be decoded and dispatched with the register writes all associated with the same re-name resource, and the conditional register write is resolved by executing the particular instruction specified by the resolved condition.

Abstract: A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

Abstract: A VLIW processor is provided with an architecture which includes fetching and executing circuitry which when combined with operation, compare, branch (OCB) instructions realizes no processing branch penalties. The OCB instructions are provided with two direct branch fields or with two indirect branch fields.

Abstract: There is disclosed a processing apparatus including, as an instruction set, a complex conditional branch instruction, and a condition setting instruction. The complex conditional branch instruction is an instruction for performing comparison operation for one or each of a plural number of conditions, and for performing branching to a branch target specified, based on comparison operation between the results of the comparison operations performed and the branching condition value specified. The condition setting instruction is an instruction for setting the condition.

Abstract: The present invention provides an efficient method to implement nested if-then-else conditional statements in a SIMD processor, which requires only one vector compare instruction for both if and else parts of the conditional construct. No stack and stack-handling instructions are needed for vector condition codes. Two condition code flag bits representing if and else parts of testing per element provide for nesting of multiple if-then-else. All SIMD instructions are conditional including the vector compare instruction, and this provides a method for aggregating multiple conditions in nested if-then-else statements. M full levels of if-then-else nesting requires (2M?1) nodes or vector test instructions and 2M+1 condition code flags per vector element. Also, capability to compare any element of first source vector register with any element of second source vector is provided.

Abstract: One embodiment of a computing system configured to manage divergent threads in a thread group includes a stack configured to store at least one token and a multithreaded processing unit. The multithreaded processing unit is configured to perform the steps of fetching a program instruction, determining that the program instruction is an indirect branch instruction, and processing the indirect branch instruction as a sequence of two-way branches to execute an indirect branch instruction with multiple branch addresses. Indirect branch instructions may be used to allow greater flexibility since the branch address or multiple branch addresses do not need to be determined at compile time.

Abstract: A microcomputer includes a CPU capable of performing a plurality of tasks in a parallel time-sharing operation. The tasks include at least one special task having a fixed loop program with a constant increase of an instruction address. When the CPU performs a conditional judgment instruction in the special task, the CPU prohibits reflecting an execution result of the conditional judgment instruction to both of the CPU and a periphery circuit in a case where it is no need to perform an instruction described in the special task after the conditional judgment instruction.

Abstract: An approach for improving efficiency of speculative execution of instructions is disclosed. In one embodiment, a branch predictor entry associated with a particular branch instruction is accessed when the particular branch instruction is to be speculatively executed. The branch predictor entry may take on different values indicating whether a first possible path or a second possible path should be executed. Based upon a current value of the branch predictor entry, a predicted path for the particular branch instruction may be determined. Instructions along the predicted path may be executed, before the particular branch instruction is resolved. Once the particular branch instruction is resolved, a cost associated with executing the one or more instructions may be determined. Accordingly, the branch predictor entry may be updated by an amount that is commensurate with the cost.

Abstract: The information processing device of the present invention stores the branch history information of a fetched instruction. When branch prediction fails, BHR information used for the branch prediction is restored using this stored branch history information. Thus, even when branch prediction fails, BHR information can be accurately restored. Accordingly, prediction accuracy can be improved.

Abstract: Architectural techniques and implementations that defer enforcement of certain delayed control transfer instruction (DCTI) sequencing constraints or conventions to later stages of an execution pipeline are described. In this way, complexity of a processor pipeline front-end (including fetch sequencing) can be simplified, at least in-part, by fetching instructions generally without regard to such constraints or conventions. Instead, enforcement of such sequencing constraints and/or conventions may be deferred to one or more pipeline stages associated with commitment or retirement of instructions. Higher fetch bandwidth may be achieved in some realizations when, for example, DCTI couples are encountered in an execution sequence.

Abstract: Methods and apparatus for identifying a first flow control instruction in an executing program, the first instruction being associated with a first program address at which program execution will continue after execution of the first instruction. A determination is made as to whether the first program address is protected. If the first program address is protected, a first alternate program address is substituted for the first program address such that program execution will continue at the first alternate program address after execution of the first instruction.

Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.

Abstract: A method and system for relative multiple-target branch instruction execution in a processor is provided. One implementation involves receiving an instruction for execution; determining a next instruction to execute based on multiple condition bits or outcomes of a comparison by the current instruction; obtaining a specified instruction offset in the current instruction; and using the offset as the basis for multiple instruction targets based on said outcomes, wherein the number of conditional branches is reduced.

Abstract: A data processing apparatus includes: a branch-metric computation section configured to compute a branch metric; a state-metric computation section configured to compute a state metric; a detection section configured to detect a minimum state metric; a storage section configured to store states as surviving states; and a selection section configured to select a candidate.

Abstract: Methods, systems and computer program products for concomitant pair per-fetching. Exemplary embodiments include a method for concomitant pair prefetching, the method including detecting a stride pattern, detecting an indirect access pattern to define an access window, prefetching candidates within the defined access window, wherein the prefetching comprises obtaining prefetch addresses from a history table, updating a miss stream window, selecting a candidate of a concomitant pair from the miss stream window, producing an index from the candidate pair, accessing an aging filter, updating the history table and selecting another concomitant pair candidate from the miss stream window.

Abstract: In one embodiment, the present invention includes a predictor to predict contention of an operation to be executed in a program. The operation may be processed based on a result of the prediction, which may be based on multiple independent predictions. In one embodiment, the operation may be optimized if no contention is predicted. Other embodiments are described and claimed.

Abstract: An apparatus for implementing branch intensive algorithms is disclosed. The apparatus includes a processor containing a plurality of ALUs and a plurality of result registers. Each result register has a guard input which allows the ALU to write a result to the register upon receipt of a selection signal at the guard input. A lookup table is dynamically programmed with logic to implement an upcoming branching portion of program code. Upon evaluation of the branch conditions of the branching portion of code, the lookup table outputs a selection signal for writing the correct results of the branching portion of code based on the evaluation of the branch condition statements and the truth table programmed into the lookup table to the result register.

Abstract: The present invention generates state machines that can be used in a scanner and/or a parser for software program compilation. The state machines are not table-driven, but rather are encoded directly by creating jumps and branches in bytecodes, which are machine-independent codes generated by a Java compiler and can be executed on any Java-enabled device. Such state machines can be much faster than those based on tables, and much smaller in code size than those implemented in executable codes. In addition, such state machines can be optimized to reduce the number of states and the amount of codes required to encode each state in it. This can allow these state machines to meet strict code size restrictions specified by certain virtual machines, such as the Java virtual machine.

Abstract: Methods and apparatus are disclosed to prefetch memory objects. An example method includes identifying program states associated with an executing program; associating memory profiles with respective ones of the program states; identifying at least one next probable state based on calculated entropy values; and prefetching memory objects associated with the at least one memory profile corresponding to the at least one next probable state.

Abstract: State machines can be used in a scanner and a parser for program compilation. The state machines can be non-table-driven, but rather are encoded directly in bytecodes. A special algorithm can be used to generate the multi-way branch associated with a state in a state machine so that the multi-way branch meets specified optimality requirements on the size of the bytecodes. The bytecodes so implemented can be more compact and run faster than those generated un-optimized. The algorithm for obtaining an optimal implementation of the multi-way branch can be conceptually divided into three phases: first, it constructs a set of subarrays that form a disjoint covering for the target array; second, it determines an optimal branch implementation for each subarray; and third, it determines the optimal branch implementation for each union of one or more adjacent subarrays, culminating to the optimal implementation for the entire target array.

Abstract: Disclosed is an automated synthesis system in which a generalized condition vector (GCV) is generated at a node that is the leaf of a tree indicating a conditional branch of a control/data flow graph representing the flow of behavioral control and data of a circuit. The GVC is a condition vector includes valid bits that are set as a condition vector of code 1 only at one component in a case where an outer conditional operation to a certain operation node is unresolved and, moreover, an inner conditional operation to said certain operation node is resolved, the valid bits being bits at positions where components of a vector of the inner side resolved conditional operation are 1's. The GVC of the operation node is calculated by taking a bitwise logical OR with the condition vector of the unresolved conditional operation.

Abstract: A branch aware first-in first-out (FIFO) memory may include a memory array to store data; a push pointer to address memory locations therein to write data; a pop pointer to address memory locations therein to read data; a pointer memory; and control logic coupled to the pointer memory. The pointer memory saves prior pop pointer values of the pop pointer. The control logic may restore prior pop pointer values from the pointer memory into the pop pointer in response to receiving program branching information.

Abstract: A microprocessor, including a plurality of registers and an instruction execution module which is adapted to process a sequence of conditional tests. The module uses an instruction set that has the following instructions: A test-and-condition instruction which evaluates each of the conditional tests as true or false and responsive thereto sets respective values in the registers. A priority-test-branch instruction, which causes the instruction execution module, responsive to one of the conditional tests evaluating as true and to the respective values in the registers, to execute a priority code module. A combination-test-branch instruction, which causes the instruction execution module, responsive to evaluations of the conditional tests and to the respective values in the registers, to execute a combination code module.

Abstract: A branch prediction apparatus having a primary predictor and a secondary predictor that selectively overrides the primary predictor based on the type of branch instruction decoded. A branch target address cache in the primary branch predictor speculatively predicts a branch target address and direction based on an instruction cache fetch address prior to decoding the instruction, and the processor branches to the speculative target address if the speculative direction is predicted taken. Later in the pipeline, decode logic decodes the instruction and determines the branch instruction type, such as whether the branch instruction is a conditional branch, a return instruction, a program counter-relative type branch, an indirect branch, etc. Depending upon the branch type, if the primary and secondary predictions do not match, the processor branches based on the secondary prediction to override the branch taken based on the primary prediction.

Abstract: A method and apparatus for a loop predictor for predicting the end of a loop is disclosed. In one embodiment, the loop predictor may have a predict counter to hold a predict count representing the expected number of times that a predictor stew value will repeat during the execution of a given loop. The loop predictor may also have one or more running counters to hold a count of the times that the stew value has repeated during the execution of the present loop. When the counter values match the predictor may issue a prediction that the loop will end.

Abstract: Improved Branch prediction utilizes both a Branch Target Buffer (BTB) and a Multiple Target Table (MTT) for providing the capability to predict multiple targets for a single branch. A MTT when used in conjunction with a BTB allows for branches which have changing targets to be able to selectively choose the target of choice based on the execution path that was taken that lead to the given branch. The method predicts traget addresses, and between the static and dynamic target address, and upon finding a hit, the target is sent to the instruction cache such that a fetch can begin for the current target address and the target address is sent back to the Branch Target Buffer (BTB) to begin the search for the next branch given the current target predicted address. Upon resolving a branch the dynamic target is placed in MTT for future use.

Abstract: An apparatus and method for implementing a switch instruction in the IA64 architecture is provided. With the apparatus and method, a first register is used to identify whether a low is either 0, 1 or some other value, and a second register is used to identify a shift amount. The first register is then shifted by the shift amount in the second register. The first register value is then moved to the predicate register set in the IA64 architecture, thereby identifying which branch is to be taken. If the first register is shifted outside the predicate registers, a default address is provided.

Abstract: A method of identifying pseudo-invariant instructions in computer program hot paths, comprising the steps of creating an intermediate representation of a hot path in a software buffer, executing instructions in the program image for the computer program until a hot path is detected, copying computer machine state and computer processor register contents to a context in memory, and using this context to compute an output a plurality of times for each instruction in the hot path using an interpreter that emulates the computer processor. Results of the interpreter computations are stored with the frequency count for each unique output in a table that is readable by a program optimizer. Frequency counts for each instruction are compared with a pseudo-invariant threshold to classify an instruction as pseudo-invariant.

Abstract: An apparatus to perform no-latency conditional branching has a sequencer for executing program instructions including one or more conditional branch instructions. The conditional branch instruction is a binary word specifying a branch condition address and a conditional instruction. The branch unit has a programmable flag selection memory and a plurality of first flag selectors and determines in hardware whether to branch according to the conditional instruction. Each first flag selector accepts a plurality of available flags and selects a flag based upon contents in the flag selection memory. A second flag selector accepts the flags from the first flag selectors and selects one of the flags to present as a branch flag based upon the branch condition address. The branch flag indicates whether to branch to the destination address.

Abstract: A method and apparatus for providing full accessibility to on-chip instruction cache and microcode ROM are described. A dummy tag and a dummy instruction are written into a cache tag array and an instruction array, respectively, during a test mode. The dummy tag is concatenated with a predetermined set number and a predetermined word address to form a dummy address having a dummy tag field, a set field and a word address field. An instruction fetch is invoked using the dummy address. The instruction cache is accessed with the dummy address, and a cache miss is forced to occur. The dummy tag field of the dummy address is written into the tag array at a row specified by the predetermined set number, and the dummy instruction is written into the instruction array at the same row. Execution of the dummy instruction is suppressed. A read operation is performed in a similar manner, except in that case an instruction cache hit is forced to occur to cause data to be read from the instruction cache.

Abstract: A data processor executes an instruction (JAVASW) to implement efficient interpreter functionality by combining the tasks of table jumps and thread or task switching which is controlled by a running value such as a counter or a timer. Execution of the instruction always requires a change of flow to be taken. In one form, the instruction may cause a hardware accelerator to be signaled to complete instruction execution. Additionally, a memory table containing emulation code correlated to specific byte codes may be compressed for a large number of identified byte codes by the use of separate storage. Further, use of a same portion of the memory table may occur in connection with execution of different bytecodes. While discussed in the context of Java bytecodes, the instruction is applicable to any programming language and processor architecture.

Abstract: A system and method for performing a general ternary branch instruction is provided. Additionally, different approaches are provided for reducing the complexity of a ternary branch instruction word and corresponding hardware.

Abstract: An order placement and acceptance system includes a first data processing device for sending a design data for processing and manufacture of a predetermined item, a second data processing device for obtaining the design data sent from the first data processing device and for sending at least a part of the design data, and a third data processing device for obtaining at least the part of the design data sent from the second data processing device.

Abstract: In a conventional information processor that performs speculative execution of a following instruction having a data dependency, since an arithmetic and logical unit is used in performing the speculative execution and the same ALU is used again when the prediction is wrong, the frequency of use of the ALU increases. To prevent this, a history ALU for outputting a past execution result of an instruction, as it is, as an execution result of the instruction and an instruction issue circuit for issuing an instruction whose operand is the same as a past value to the history ALU are provided with an intention of omitting the actual speculative execution. A Guard cache provided in the history cache stores addresses of instructions that give low prediction accuracy, whereby any instruction whose address has been registered in the Guard cache is prevented from being registered again in the history cache.

Abstract: Methods and systems are provided to selectively log branch trace store data associated with the execution of an application. A privilege level is received, which identifies an execution mode for a processor for which branch trace store data is to be logged to a buffer. The privilege level is used to set one or more privilege flags that permit selective branch trace store data to be logged in the buffer when the application is executed. In one embodiment, the privilege level represents a user application mode, a supervisory application mode, or a mode representing both a user application mode and a supervisory application mode.

Abstract: A method of initializing random access memory during a BIOS process executed by a processor that is configured to perform speculative reading. The ROM BIOS is modified such that speculative reading is prevented during the memory initialization.

Abstract: A method and system for monitoring execution performance of a program is provided. Profiling functionality may be qualified by setting various qualifying flags at the request of a user. These qualifying flags may be used to limit the amount of trace data being generated or processed, thereby providing a more focused picture of an application's execution to the user. One or more trace,qualifying conditions are selectable by a user and are used during a profiling phase of application execution or during a post-processing phase of analyzing the application execution. During a profiling phase, an occurrence of a selected event or a timer interrupt is detected, and a determination is made as to whether a trace qualifying condition has been previously selected. In response to a determination that a trace qualifying condition has been selected, a trace record is then generated.

Abstract: Hardware device for parallel processing a determined instruction of a set of instructions having a same format defining operand fields and other data fields, the execution of this determined instruction being represented as an algorithm comprising a plurality of processes, the processing of which depending on decisions. Such a device comprises means (22-30) for activating the processing of one or several processes (32-38) determined by the operand fields of the instruction, decision macroblocks (12-20) each being associated with a specific instruction of the set of instructions, only one decision marcoblock being selected by the determined instruction in order to determine which are the process(es) to be activated for executing the determined instruction.

Abstract: An exemplary embodiment of the present invention is a method and system for reducing the number of branch instructions required to test combinations of millicode branch points. The method is implemented via a pipe-lined computer processor executing a millicode routine. The processor interrogates a millicode condition code; interrogates a first field of the TMBP instruction, the results of which determine a logical function to be performed on the millicode condition code; interrogates a second field of the TMBP instruction which specifies a first millicode branch point; interrogates a third field of the TMBP instruction, which specifies a second millicode branch point; and sets a millicode condition code based upon the results of the interrogating and used for executing subsequent TMBP instructions or conditional branch instructions.

Abstract: A system of the present invention utilizes memory for storing a computer program and processing circuitry for processing and executing instructions of the computer program. In particular, the computer program includes a set of code and an unconditional branch instruction. The processing circuitry, in executing the computer program, receives run time data indicative of whether the set of code is enabled or disabled, and based on the run time data, the processing circuitry sets a value of a mode indicator. While the program is running, the processing circuitry receives and processes the unconditional branch instruction. When the set of code is disabled, the processing circuitry executes the unconditional branch instruction based on the mode indicator, thereby preventing execution of the set of code. However, when the set of code is enabled, the processing circuitry refrains from executing the unconditional branch instruction based on the mode indicator and executes the set of code.

Abstract: The present invention relates to a method and system for providing an N-way select instruction in a processor. Specifically, a method for providing an N-way select instruction includes decoding an instruction as an N-way select instruction. The method also includes selecting at least one pair of source operands from a plurality of instruction operands using information from a plurality of parallel control registers. The method, further includes selecting a final source operand from each of the selected at least one pair of source operands, and outputting each of the selected final source operands. In general, any N-way select instruction will have M=log2N stages of operation.

Abstract: The present invention relates to a method and system for providing an N-wide add-compare-select instruction includes decoding an instruction as an N-wide add-compare-select instruction and selecting a plurality of branch metrics. The method also includes combining the plurality of branch metrics with a plurality of source operands and outputting a pair of maximum values.

Abstract: The present invention relates to a method and system for providing a 2N-way comparison instruction in a processor. Specifically, a method for providing comparison instruction includes decoding an instruction as one of 2N-way MAX instruction and a 2N-way MIN instruction. The method also includes one of computing a maximum value for each of a plurality of pairs and computing a minimum value for each of the plurality of pairs of values. The method, further includes one of computing a maximum of the computed maximum values and computing a minimum of the computed minimum values and outputting one of the computed minimum and the computed minimum values.

Abstract: A branch resolution logic for an in-order processor is provided which scans the stages of processor pipeline to determine the oldest branch instruction having sufficient condition codes for resolution. The stages are scanned in order from the latter stages to the earlier stages, which allows quick and simple branch resolution. Therefore, because branches are resolved as soon as the necessary condition codes are generated in a specific stage, branch mispredict penalties are minimized.

Abstract: Methods and apparatus for efficiently enabling an alternate return address associated with a function call to essentially be stored such that the alternate return address may be readily accessed are disclosed. According to one aspect of the present invention, a method for enabling a return address associated with a function called by a routine to be efficiently stored includes calling the function from within the routine while the routine is executing. In general, the function is external to the routine. The function, once called, begins executing. Eventually, the function returns to the routine. Specifically, the function returns to a location in the routine that is identified by an expected return point, or normal return address. The instruction in the routine that corresponds to the expected return point is a dummy instruction that executes with a low computational overhead but does not affect program execution.

Abstract: A branch predictor for improving branch prediction accuracy is provided. The branch predictor includes global and local Agree dynamic branch predictors, one of which is selected for correlation with a static branch prediction made based upon a test type of a conditional branch instruction specifying a condition upon which the branch will be taken. In one embodiment, the selection is made by correlating a selection prediction made the static predictor based on the test type and an Agree prediction made by a selector history table based on the branch instruction address. In an alternate embodiment, the selection is made directly by the selector history table, without the benefit of the static prediction. In addition, the static predictor makes its predictions based upon an opcode of an instruction preceding the conditional branch instruction and upon a sign of a displacement for calculating a target address of the conditional branch instruction.

Abstract: In accordance with methods and systems consistent with the present invention, an improved processor performance instrumentation system is provided that allows a software tester to measure more performance indicators than there are hardware counters during a single execution of a tested program. The improved processor performance instrumentation system accomplishes this by “multiplexing” performance indicators while executing the tested program. In effect, methods and systems consistent with the present invention extend the abilities of the limited number of hardware counters to allow them to measure a number of performance indicators otherwise not allowed during one execution of the tested program.

Abstract: An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the predictor can predict the outcome of a second branch instruction following closely in the pipeline with the benefit of the first prediction. This improves the prediction accuracy where the first branch has not been resolved prior to the time when the second prediction is ready to be made. If the first prediction turns out to be incorrect, the global branch history is restored from a previously saved copy and updated with the first branch instruction's actual outcome.

Abstract: A branch prediction apparatus that employs dual call/return stacks to predict return addresses in a microprocessor. The apparatus includes a first call/return stack that provides a speculative return address based upon a return instruction hit in a speculative branch target address cache (BTAC) of an instruction cache fetch address prior to decoding of the instruction to know whether it is actually a return instruction. The speculative return address is provided early in the pipeline and the microprocessor speculatively branches to the speculative return address. Later in the pipeline, a second call/return stack provides a non-speculative return address after the instruction is decoded and verified to be a return instruction. A comparator compares the speculative and non-speculative return addresses, and if the two addresses mismatch, the microprocessor branches to the non-speculative return address.