Branch Prediction Patents (Class 712/239)
  • Patent number: 10776457
    Abstract: Systems and method provide for generation of a unique key pair having a public and private key for an individual device. The public key may be embedded (e.g., burned or etched) into a central processing unit (CPU) during the manufacturing process. The burning or etching process may make the public key unmodifiable. The matching private key may then be stored in a secure database. Software code may be available through download over a computer based network (e.g., the Internet). A request may be made for the software code. Prior to delivery, the software code may be digitally signed with the private key corresponding to the individual device. Logic programmed into the CPU may prevent the execution of code that is not signed with the private key that corresponds to the public key.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: September 15, 2020
    Assignee: EPIC GAMES, INC.
    Inventor: Gil Wheaton Gribb
  • Patent number: 10754781
    Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 25, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz, Ashutosh Misra, Brian R. Prasky
  • Patent number: 10740126
    Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: August 11, 2020
    Assignee: Intel Corporation
    Inventors: Mohammad Abdallah, Ankur Groen, Erika Gunadi, Mandeep Singh, Ravishankar Rao
  • Patent number: 10732977
    Abstract: The bytecode processing device includes a branch target buffer including a tag field, a target address field corresponding to the tag field and an operation code bit field for representing whether a value stored in the tag field is an operation code, a bytecode fetch unit configured to fetch a bytecode including an operation code, an operation code extraction unit configured to extract the operation code from the bytecode, a branch target buffer search unit configured to perform a search to determine whether the extracted operation code exists in the tag field of the branch target buffer, and if the operation code exists in the tag field, extract a target address corresponding to the operation code from the target address field, and a bytecode execution unit configured to execute the bytecode by branching to the target address.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: August 4, 2020
    Assignee: Seoul National University R&DB Foundation
    Inventors: JaeWook Lee, ChanNoh Kim, SungMin Kim
  • Patent number: 10719329
    Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 21, 2020
    Assignee: Arm Limited
    Inventors: Vladimir Vasekin, David Michael Bull, Chiloda Ashan Senarath Pathirane, Alexei Fedorov
  • Patent number: 10713050
    Abstract: Table of Contents (TOC)-setting instructions are replaced in code with TOC predicting instructions. A determination is made as to whether code includes an instruction sequence to compute a value of a pointer to a reference data structure, such as a TOC. Based on determining the code includes the instruction sequence, the instruction sequence in the code is replaced with a set instruction. The set instruction predicts the value of the pointer to the reference data structure.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: July 14, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K. Gschwind, Valentina Salapura
  • Patent number: 10642621
    Abstract: In one embodiment, a branch prediction circuit includes: a first bimodal predictor having a first plurality of entries each to store first prediction information for a corresponding branch instruction; a global predictor having a plurality of global entries each to store global prediction information for a corresponding branch instruction; a second bimodal predictor having a second plurality of entries each to store second prediction information for a corresponding branch instruction; a monitoring table having a plurality of monitoring entries each to store a counter value based on the second prediction information for a corresponding branch instruction; and a control circuit to allocate a global entry within the global predictor based at least in part on the counter value of a monitoring entry of the monitoring table for a corresponding branch instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: May 5, 2020
    Assignee: Intel Corporation
    Inventors: Ragavendra Natarajan, Niranjan Soundararajan, Sreenivas Subramoney
  • Patent number: 10607137
    Abstract: Disclosed aspects relate to branch predictor selection management in a pipelined microprocessor architecture. A set of selection factor data may be collected in the pipelined microprocessor architecture. The set of selection factor data may be analyzed using a perceptron-based learning technique with respect to a set of candidate branch predictors. A chosen branch predictor may be selected from the set of candidate branch predictors based on analyzing the set of selection factor data with respect to the set of candidate branch predictors using the perceptron-based learning technique. The chosen branch predictor may be invoked in the pipelined microprocessor architecture.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Satish Kumar Sadasivam, Puneeth A. H. Bhat, Shruti Saxena
  • Patent number: 10607003
    Abstract: A method, computer program product and/or system is disclosed. According to an aspect of this invention, one or more processors receive an indirect jump instruction comprising a target address offset and a maximal offset value. One or more processors determine whether the target address offset is valid by comparison of the target address offset and the maximal offset value and one or more processors execute a jump operation based on whether the target address offset is valid. In some embodiments of the present invention, the jump operation comprises one or more processors executing an instruction located at a target address referenced by the target address offset if the target address offset is valid. In some embodiments, the jump operation further comprises one or more processors raising an exception if the target address offset is not valid.
    Type: Grant
    Filed: June 29, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventor: Nitzan Peleg
  • Patent number: 10565093
    Abstract: A method, system and computer program product for detecting potential failures in a continuous delivery pipeline. A machine learning model is created to predict whether changed portion of codes under development at various stages of the continuous delivery pipeline will result in a pipeline failure. After creating the machine learning model, log file(s) may be received that were generated by development tool(s) concerning a changed portion of code under development at a particular stage of the continuous delivery pipeline. The machine learning model provides relationship information between the log file(s) and the changed portion of code. A message is then generated and displayed based on this relationship information, where the message may provide a prediction or a recommendation concerning potential failures in the continuous delivery pipeline. In this manner, the potential failures in the continuous delivery pipeline may be prevented without requiring context switching.
    Type: Grant
    Filed: October 9, 2018
    Date of Patent: February 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bradley C. Herrin, Alexander Sobran, Bo Zhang, Xianjun Zhu
  • Patent number: 10565379
    Abstract: In one embodiment, an apparatus includes an execution monitor to monitor an application in execution, identify a code region, generate region information for the code region, and analyze the code region to identify potential malicious behavior, and if the potential malicious behavior is identified, to alert a security agent, and otherwise to enable the code region to execute, where the execution monitor is isolated from the application. Other embodiments are described and claimed.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: February 18, 2020
    Assignee: Intel Corporation
    Inventors: Koichi Yamada, Tugrul Ince, Paul A. Campbell, Jiunn-Yeu Chen
  • Patent number: 10552159
    Abstract: A computer processor includes a branch prediction unit that includes a local branch predictor and a global branch predictor. Managing power consumption in such a computer processor includes, for each of a plurality of branch instructions: performing, by the local branch predictor, a local branch prediction; performing, by each of the global branch predictors, a global branch prediction; determining to utilize the local branch prediction over the global branch predictions as a branch prediction for the branch instruction; incrementing a value of a counter; determining whether the value of the counter exceeds a predetermined threshold; and if the value of the counter exceeds the predetermined threshold, powering down at least one of the global branch predictors and configuring the branch prediction unit to bypass the powered down global branch predictor for branch predictions of subsequent branch instructions.
    Type: Grant
    Filed: June 1, 2018
    Date of Patent: February 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Nicholas R. Orzol, Robert A. Philhower
  • Patent number: 10536168
    Abstract: The present disclosure relates to a safety system having a memory unit configured to store a series of executable instructions. In some embodiments, the executable instructions are grouped into code parts, and each code part is assigned a predefined code value. A processor is configured to execute the series of executable instructions, and to output the predefined code values respectively as the code parts are executed. A program flow monitoring (PFM) unit is configured to respectively receive the predefined code values from the processor, such that the PFM unit generates an error-checking value from the predefined code values. A verification unit is configured to compare the error-checking value to an expected return value to determine whether the series of executable instructions executed properly.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: January 14, 2020
    Assignee: Infineon Technologies AG
    Inventor: Bernhard Gstoettenbauer
  • Patent number: 10489218
    Abstract: A method of monitoring, by one or more cores of a multi-core processor, speculative instructions, where the speculative instructions store data to a shared memory location, and where a semaphore, associated with the memory location, specifies the availability of the memory location to store data. One or more speculative instructions are flushed based on when the semaphore specifies the memory location is unavailable. Any further speculative instructions are suppressed from being issued based on a count of flushed speculation instructions above a specified threshold, executing the speculative instructions when the semaphore specifies the memory location is available, and storing the data to the memory location.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: November 26, 2019
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Douglas Benson Hunt, William E. Jones
  • Patent number: 10481914
    Abstract: Program flow prediction circuitry comprises a history register to store history data for at least one or more most recently executed branch instructions; a memory to store a plurality of sets of weight values, one set for each of a group of portions of one or more bits of the history data; access circuitry to access, for a current branch instruction to be predicted, a weight value for each of the portions of one or more bits of the history data by selecting from the set of weight values in dependence upon a current value of the portions of the history data; a combiner to generate a combined weight value by combining the weight values accessed by the access circuitry; a comparator to compare the combined weight value with a prediction threshold value to detect whether or not a branch represented by the current branch instruction is predicted to be taken; and weight modifier circuitry to modify the accessed weight values in dependence upon a resolution of whether the branch represented by the current branch ins
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: November 19, 2019
    Assignee: ARM Limited
    Inventors: Guillaume Bolbenes, Houdhaifa Bouzguarrou, Luc Orion, Eddy Lapeyre
  • Patent number: 10423422
    Abstract: A processor may include a baseline branch predictor and an empirical branch bias override circuit. The baseline branch predictor may receive a branch instruction associated with a given address identifier, and generate, based on a global branch history, an initial prediction of a branch direction for the instruction. The empirical branch bias override circuit may determine, dependent on a direction of an observed branch direction bias in executed branch instruction instances associated with the address identifier, whether the initial prediction should be overridden, may determine, in response to determining that the initial prediction should be overridden, a final prediction that matches the observed branch direction bias, or may determine, in response determining that the initial prediction should not be overridden, a final prediction that matches the initial prediction.
    Type: Grant
    Filed: December 19, 2016
    Date of Patent: September 24, 2019
    Assignee: Intel Corporation
    Inventors: Niranjan K. Soundararajan, Sreenivas Subramoney, Rahul Pal, Ragavendra Natarajan
  • Patent number: 10372459
    Abstract: Systems and methods for branch prediction include identifying a subset of branch instructions from an execution trace of instructions executed by a processor. The identified subset of branch instructions have greater benefit from branch predictions made by a neural branch predictor than branch predictions made by a non-neural branch predictor. During runtime, the neural branch predictor is selectively used for obtaining branch predictions of the identified subset of branch instructions. For remaining branch instructions outside the identified subset of branch instructions, branch predictions are obtained from a non-neural branch predictor. Further, a weight vector matrix comprising weight vectors for the identified subset of branch instructions of the neural branch predictor is pre-trained based on the execution trace.
    Type: Grant
    Filed: September 21, 2017
    Date of Patent: August 6, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Gurkanwal Brar, Christopher Ahn, Gurvinder Singh Chhabra
  • Patent number: 10372453
    Abstract: A method in an instruction fetch unit configured to initiate a fetch of an instruction bundle from a first memory and to initiate a fetch of an instruction bundle from a second memory, wherein a fetch from the second memory takes a predetermined fixed plurality of processor cycles, the method comprising: identifying that an instruction bundle is to be selected for fetching from the second memory in a predetermined future processor cycle; and initiating a fetch of the identified instruction bundle from the second memory a number of processor cycles prior to the predetermined future processor cycle based upon the predetermined fixed plurality of processor cycles taken to fetch from the second memory.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: August 6, 2019
    Assignee: MIPS Tech, LLC
    Inventors: Andrew David Webber, Daniel Ángel Chaver Martínez, Enrique Sedano Algarabel
  • Patent number: 10353710
    Abstract: A technique for operating a processor includes identifying a difficult branch instruction (branch) whose target address (target) has been mispredicted multiple times. Information about the branch (which includes a current target and a next target) is learned and stored in a data structure. In response to the branch executing subsequent to the storing, whether a branch target of the branch corresponds to the current target in the data structure is determined. In response to the branch target of the branch corresponding to the current target of the branch in the data structure, the next target of the branch that is associated with the current target of the branch in the data structure is determined. In response to detecting that a next instance of the branch has been fetched, the next target of the branch is utilized as the predicted target for execution of the next instance of the branch.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: July 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Richard J. Eickemeyer, Naga P. Gorti, David S. Levitan, Albert J. Van Norstrand, Jr.
  • Patent number: 10268480
    Abstract: A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: April 23, 2019
    Assignee: III HOLDINGS 2, LLC
    Inventors: Saurabh Chheda, Kristopher Carver, Raksit Ashok
  • Patent number: 10261797
    Abstract: Provided is a method for predicting a target address using a set of Indirect Target TAgged GEometric (ITTAGE) tables and a target address pattern table. A branch instruction that is to be executed may be identified. A first tag for the branch instruction may be determined. The first tag may be a unique identifier that corresponds to the branch instruction. Using the tag, the branch instruction may be determined to be in a target address pattern table, and an index may be generated. A predicted target address for the branch instruction may be determined using the generated index and the largest ITTAGE table. Instructions associated with the predicted target address may be fetched.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: April 16, 2019
    Assignee: International Business Machines Corporation
    Inventors: Satish Kumar Sadasivam, Puneeth A. H. Bhat, Shruti Saxena
  • Patent number: 10248397
    Abstract: Exemplary embodiments for deploying code in a computing sysplex environment are provided. In one embodiment, by way of example only, a system-wide trending mechanism is applied. At least one of an idle time and a low Central Processing Unit (CPU) utilization time of one system in the sysplex environment is matched with an estimated deployment time obtained from at least one of a latest measured period of time and a calculated time trend. A system-wide coordinating mechanism is applied. A staggered code deployment operation is recommended for at least one node of the system at an optimum system time generated from the matching.
    Type: Grant
    Filed: November 10, 2017
    Date of Patent: April 2, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Joseph W. Dain
  • Patent number: 10235172
    Abstract: A branch predictor for predicting branch instructions performs different branch prediction operations for branches executing in a transaction than those not-executing in a transaction, including suppressing branch prediction functions based on progress of a re-execution of a previously aborted transaction, the transaction buffering data and committing the buffered data to memory when the transaction completes, but discarding the buffered data when the transaction aborts.
    Type: Grant
    Filed: June 2, 2014
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael K Gschwind, Valentina Salapura
  • Patent number: 10228949
    Abstract: A method of identifying instructions including accessing a plurality of instructions that comprise multiple branch instructions. For each branch instruction of the multiple branch instructions, a respective first mask is generated representing instructions that are executed if a branch is taken. A respective second mask is generated representing instructions that are executed if the branch is not taken. A prediction output is received that comprises a respective branch prediction for each branch instruction. For each branch instruction, the prediction output is used to select a respective resultant mask from among the respective first and second masks. For each branch instruction, a resultant mask of a subsequent branch is invalidated if a previous branch is predicted to branch over said subsequent branch. A logical operation is performed on all resultant masks to produce a final mask. The final mask is used to select a subset of instructions for execution.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: March 12, 2019
    Assignee: INTEL CORPORATION
    Inventor: Mohammad Abdallah
  • Patent number: 10223123
    Abstract: In an embodiment, an apparatus includes a plurality of memories configured to store respective data in a plurality of branch prediction entries. Each branch prediction entry corresponds to at least one of a plurality of branch instructions. The apparatus also includes a control circuit configured to store first data associated with a first branch instruction into a corresponding branch prediction entry in at least one memory of the plurality of memories. The control circuit is further configured to select a first memory of the plurality of memories, to disconnect the first memory from a power supply in response to a detection of a first power mode signal, and to cease storing data in the plurality of memories in response to the detection of the first power mode signal.
    Type: Grant
    Filed: April 20, 2016
    Date of Patent: March 5, 2019
    Assignee: Apple Inc.
    Inventors: Conrado Blasco, Brett S. Feero, David Williamson, Ian D. Kountanis, Shih-Chieh Wen
  • Patent number: 10210328
    Abstract: A method, computer program product and/or system is disclosed. According to an aspect of this invention, one or more processors receive an indirect jump instruction comprising a target address offset and a maximal offset value. One or more processors determine whether the target address offset is valid by comparison of the target address offset and the maximal offset value and one or more processors execute a jump operation based on whether the target address offset is valid. In some embodiments of the present invention, the jump operation comprises one or more processors executing an instruction located at a target address referenced by the target address offset if the target address offset is valid. In some embodiments, the jump operation further comprises one or more processors raising an exception if the target address offset is not valid.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: February 19, 2019
    Assignee: International Business Machines Corporation
    Inventor: Nitzan Peleg
  • Patent number: 10191741
    Abstract: A computer system may recognize a busy-wait loop in program instructions at compile time and/or may recognize busy-wait looping behavior during execution of program instructions. The system may recognize that an exit condition for a busy-wait loop is specified by a conditional branch type instruction in the program instructions. In response to identifying the loop and the conditional branch type instruction that specifies its exit condition, the system may influence or override a prediction made by a dynamic branch predictor, resulting in a prediction that the exit condition will be met and that the loop will be exited regardless of any observed branch behavior for the conditional branch type instruction. The looping instructions may implement waiting for an inter-thread communication event to occur or for a lock to become available. When the exit condition is met, the loop may be exited without incurring a misprediction delay.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: January 29, 2019
    Assignee: Oracle International Corporation
    Inventors: David Dice, Mark S. Moir
  • Patent number: 10157063
    Abstract: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.
    Type: Grant
    Filed: September 28, 2012
    Date of Patent: December 18, 2018
    Assignee: Intel Corporation
    Inventors: Polychronis Xekalakis, Pedro Marcuello, Alejandro Vicente Martinez, Christos E. Kotselidis, Grigorios Magklis, Fernando Latorre, Raul Martinez, Josep M. Codina, Enric Gibert Codina, Crispin Gomez Requena, Antonio Gonzelez, Mirem Hyuseinova, Pedro Lopez, Marc Lupon, Carlos Madriles, Daniel Ortega, Demos Pavlou, Kyriakos A. Stavrou, Georgios Tournavitis
  • Patent number: 10049212
    Abstract: In one embodiment, a processor includes at least one execution unit. The processor also includes a Return Oriented Programming (ROP) logic coupled to the at least one execution unit. The ROP logic may validate a return pointer stored on a call stack based on a secret ROP value. The secret ROP value may only be accessible by the operating system.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: August 14, 2018
    Assignee: Intel Corporation
    Inventor: Stephen A. Fischer
  • Patent number: 10037207
    Abstract: A computer processor includes a branch prediction unit that includes a local branch predictor and a global branch predictor. Managing power consumption in such a computer processor includes, for each of a plurality of branch instructions: performing, by the local branch predictor, a local branch prediction; performing, by each of the global branch predictors, a global branch prediction; determining to utilize the local branch prediction over the global branch predictions as a branch prediction for the branch instruction; incrementing a value of a counter; determining whether the value of the counter exceeds a predetermined threshold; and if the value of the counter exceeds the predetermined threshold, powering down at least one of the global branch predictors and configuring the branch prediction unit to bypass the powered down global branch predictor for branch predictions of subsequent branch instructions.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: July 31, 2018
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Nicholas R. Orzol, Robert A. Philhower
  • Patent number: 10013326
    Abstract: A combination of hardware and software collect profile data for asynchronous events, at code region granularity. An exemplary embodiment is directed to collecting metrics for prefetching events, which are asynchronous in nature. Instructions that belong to a code region are identified using one of several alternative techniques, causing a profile bit to be set for the instruction, as a marker. Each line of a data block that is prefetched is similarly marked. Events corresponding to the profile data being collected and resulting from instructions within the code region are then identified. Each time that one of the different types of events is identified, a corresponding counter is incremented. Following execution of the instructions within the code region, the profile data accumulated in the counters are collected, and the counters are reset for use with a new code region.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: July 3, 2018
    Assignee: Intel Corporation
    Inventors: Raul Martinez, Enric Gibert Codina, Pedro Lopez, Marti Torrents Lapuerta, Polychronis Xekalakis, Georgios Tournavitis, Kyriakos A. Stavrou, Demos Pavlou, Daniel Ortega, Alejandro Martinez Vicente, Pedro Marcuello, Grigorios Magklis, Josep M. Codina, Crispin Gomez Requena, Antonio Gonzalez, Mirem Hyuseinova, Christos Kotselidis, Fernando Latorre, Marc Lupon, Carlos Madriles
  • Patent number: 10007524
    Abstract: Branch history information characterizes results of branch instructions previously executed by a processor. A count is stored of a number of consecutive branch instructions previously executed by the processor whose results all indicate a not taken branch. In a first pipeline stage, a predicted branch result is provided based on at least a portion of the branch history information, and one or more of the branch history information, and the count, is updated based on the predicted branch result. In a second pipeline stage an actual branch result is provided based on an executed branch instruction, and the branch history information is updated based on the actual branch result. If the predicted branch result indicates a taken branch, the branch history information is updated based on the count, and if the predicted branch result indicates a not taken branch, the count is updated but not the branch history information.
    Type: Grant
    Filed: November 14, 2014
    Date of Patent: June 26, 2018
    Assignee: Cavium, Inc.
    Inventor: David Albert Carlson
  • Patent number: 9996351
    Abstract: A computer processor includes a branch prediction unit that includes a local branch predictor and a global branch predictor. Managing power consumption in such a computer processor includes, for each of a plurality of branch instructions: performing, by the local branch predictor, a local branch prediction; performing, by each of the global branch predictors, a global branch prediction; determining to utilize the local branch prediction over the global branch predictions as a branch prediction for the branch instruction; incrementing a value of a counter; determining whether the value of the counter exceeds a predetermined threshold; and if the value of the counter exceeds the predetermined threshold, powering down at least one of the global branch predictors and configuring the branch prediction unit to bypass the powered down global branch predictor for branch predictions of subsequent branch instructions.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: June 12, 2018
    Assignee: International Business Machines Corporation
    Inventors: David S. Levitan, Nicholas R. Orzol, Robert A. Philhower
  • Patent number: 9983884
    Abstract: An apparatus and method for a SIMD structured branching. For example, one embodiment of a processor comprises: an execution unit having a plurality of channels to execute instructions; and a branch unit to process control flow instructions and to maintain a per channel count for each channel and a control instruction count for the control flow instructions, the branch unit to enable and disable the channels based at least on the per channel count.
    Type: Grant
    Filed: September 26, 2014
    Date of Patent: May 29, 2018
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Darin M. Starkey, Thomas A. Piazza
  • Patent number: 9940262
    Abstract: A system and method for efficiently indicating branch target addresses. A semiconductor chip predecodes instructions of a computer program prior to installing the instructions in an instruction cache. In response to determining a particular instruction is a control flow instruction with a displacement relative to a program counter address (PC), the chip replaces a portion of the PC relative displacement in the particular instruction with a subset of a target address. The subset of the target address is an untranslated physical subset of the full target address. When the recoded particular instruction is fetched and decoded, the remaining portion of the PC relative displacement is added to a virtual portion of the PC used to fetch the particular instruction. The result is concatenated with the portion of the target address embedded in the fetched particular instruction to form a full target address.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: April 10, 2018
    Assignee: Apple Inc.
    Inventors: Shyam Sundar, Richard F. Russo, Ronald P. Hall, Conrado Blasco
  • Patent number: 9934040
    Abstract: According to an aspect, virtualized weight perceptron branch prediction is provided in a processing system. A selection is performed between two or more history values at different positions of a history vector based on a virtualization map value that maps a first selected history value to a first weight of a plurality of weights, where a number of history values in the history vector is greater than a number of the weights. The first selected history value is applied to the first weight in a perceptron branch predictor to determine a first modified virtualized weight. The first modified virtualized weight is summed with a plurality of modified virtualized weights to produce a prediction direction. The prediction direction is output as a branch predictor result to control instruction fetching in a processor of the processing system.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Matthias D. Heizmann, Daniel Lipetz, Brian R. Prasky
  • Patent number: 9921814
    Abstract: A method and systems generate a control flow graph including an edge of the control flow graph from a branch instruction to a target address of the branch instruction in an abstract interpretation for an assignment instruction to a branch target variable of a program. The program allocates a particular branch target variable to a branch instruction having a plurality of branch targets. The branch target address is loaded from the branch target variable upon branching, a branch address of a branch instruction having one branch target as well as the address assigned by the assignment instruction to the branch target variable being determined as certain constant values determined by compiling the program. The target address assigned by the assignment instruction is added to an object of the abstract interpretation. A current abstract interpretation is terminated if the abstract interpretation reaches an instruction already subjected to the abstract interpretation.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: March 20, 2018
    Assignee: International Business Machines Corporation
    Inventors: Reid T. Copeland, Toshihiko Koju
  • Patent number: 9886362
    Abstract: A method for checking the integrity of a program executed by an electronic circuit and including at least one conditional jump, wherein: a first value is updated for any instruction which does not correspond to a jump instruction; a second value is updated with the first value for each conditional jump instruction; and the second value is compared with a third value, calculated according to the performed conditional jumps.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: February 6, 2018
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Gilles Van Assche, Ronny Vankeer
  • Patent number: 9880897
    Abstract: When a software component is starting, such as but not limited to a task or a subtask, the component pushes its identification (ID) onto a stack. The component executes its other instructions. If the component completes its instructions so that it can terminate normally, it pops the stack, which removes its ID from the stack. If the component fails, such as by not being able to complete its instructions, it will not be able to pop the stack so its ID will remain in the stack. Another software process can read the IDs in the stack to identify which components have failed and can automatically take a specified action, such as by sending an email message to, sending a text message to, or calling by telephone, a person or persons responsible for that software component.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: January 30, 2018
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Tarkan Sevilmis, Arshish Cyrus Kapadia, Maxim Lukiyanov, Tittu Jose, Gheorghita Irimescu, Janak Madhusudan Agarwal, Stephen John Clark, Hardik Shah, Sreekanth Lingannapeta
  • Patent number: 9875106
    Abstract: A computer processor is provided that executes sequences of instructions stored in memory. The sequences of instructions are organized as one or more instruction blocks each having an entry point and at least one exit point offset from the entry point. An apparatus for predicting control flow through sequences of instructions includes a table storing a plurality of entries each associated with an instruction block or part thereof. At least one entry of the table corresponding to a given instruction block or part thereof includes a predictor corresponding to a predicted execution path that exits the given Instruction block or part thereof. The table is queried in order to generate a chain of predictors corresponding to a sequence of instruction blocks or parts thereof that is predicted to be executed by the computer processor.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: January 23, 2018
    Assignee: Mill Computing, Inc.
    Inventors: Roger Rawson Godard, Arthur David Kahlich
  • Patent number: 9794350
    Abstract: Generating first and second probabilities of first and second presence variables, wherein the first and second probabilities are based on a historical presence data archive based on presence data obtained before a first time. The first and second probabilities further based on first and second unified presence data, which are based on raw presence data collected at a second time after the first, and first and second user profile rules that identify first and second groups of presence data sources. First presence information is obtained based on the first probability and the first user profile rules. Second presence information is obtained based on the second probability and the second user profile rules. The presence variables are selected from a group consisting of availability, willingness, location and combinations thereof, and wherein the group of presence variables allowable for release are identified by first or second user profile rules.
    Type: Grant
    Filed: February 20, 2015
    Date of Patent: October 17, 2017
    Assignee: AT&T INTELLECTUAL PROPERTY I, L.P.
    Inventors: Christopher W. Rice, Rittwik Jana, John F. Murray, Ron Shacham
  • Patent number: 9778934
    Abstract: A method and apparatus for branch prediction is disclosed. A pattern history table (PHT) is accessed based on at least one global history value to obtain a prediction value. The prediction value and the at least one global history value used to obtain the prediction value are placed in a queue. If a branch prediction is requested, the queue is accessed to obtain a prediction value. The queue may include any number of entries and the queue maintains the oldest prediction value at the head of the queue. The prediction value at the head of the queue is used when a branch prediction is needed.
    Type: Grant
    Filed: November 16, 2010
    Date of Patent: October 3, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Anthony Jarvis, James David Dundas
  • Patent number: 9690587
    Abstract: Embodiments relate to variable branch prediction. An aspect includes determining a branch selection of an execution unit of a processor and determining whether a present prediction state of the state machine correctly predicted the branch selection by the execution unit. The aspect includes determining whether a predetermined condition is met for performing an alternative state transition and, based on determining that the predetermined condition is met, changing the present prediction state of the branch prediction state machine from the one state to another state according to an alternative state transition process based on the branch selection of the execution unit and the determination whether the present prediction state of the state machine correctly predicted the branch selection by the execution unit.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: June 27, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Narasimha R. Adiga, James J. Bonanno, Ashutosh Misra, Anthony Saporito
  • Patent number: 9652245
    Abstract: Branch prediction for indirect jumps, including: receiving, by a branch prediction module, a branch address for each of a plurality of executed branch instructions; receiving, by the branch prediction module, an instruction address of a current branch instruction; creating, by the branch prediction module, an execution path identifier in dependence upon the branch address for each of the plurality of executed branch instructions and the instruction address of the current branch instruction; and searching, by the branch prediction module, a branch prediction table for an entry that matches the execution path identifier.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: May 16, 2017
    Assignee: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.
    Inventors: Andrew D. Hilton, Brian M. Rogers, Kenichi Tsuchiya
  • Patent number: 9575763
    Abstract: A method includes undoing, in reverse program order, changes in a state of a processing device caused by speculative instructions previously dispatched for execution in the processing device and concurrently deallocating resources previously allocated to the speculative instructions in response to interruption of dispatch of instructions due to a flush of the speculative instructions. A processor device comprises a retire queue to store entries for instructions that are awaiting retirement and a finite state machine. The finite state machine is to interrupt dispatch of instructions in response to a flush of speculative instructions previously dispatched for execution in the processing device and to undo, in reverse program order, changes in a state of the processing device caused by the speculative instructions while concurrently deallocating resources previously allocated to the speculative instructions.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: February 21, 2017
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jay Fleischman, Michael Estlick
  • Patent number: 9547358
    Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: January 17, 2017
    Assignee: NVIDIA CORPORATION
    Inventors: Aneesh Aggarwal, Ross Segelken, Paul Wasson
  • Patent number: 9524166
    Abstract: Tracking global history vector in high performance out of order superscalar processors, in one aspect, may comprise providing a shift register storing global history vector that stores branch predictions and outcomes. A counter is maintained to determine a number of bits to shift the shift register to recover branch history. In another aspect, the global history vector may be implemented with a circular buffer structure. Youngest and oldest pointers to the circular buffer are maintained and used in recovery.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: December 20, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Richard J. Eickemeyer, Tejas Karkhanis, Brian R. Konigsburg, David S. Levitan, Douglas R. G. Logan, Jose E. Moreira, Mauricio J. Serrano
  • Patent number: 9495138
    Abstract: Techniques relate for verifying an effect of software program optimization. A determination is made whether a fingerprint is present in a software application that is currently executing on a processor of a computer system, where the fingerprint includes a representation of a sequence of behavior that occurs on the processor while the software application is executing. The fingerprint corresponds to an optimization made to the software application. In response to determining that the fingerprint is not present in the software application currently executing on the processor, it is determined that the optimization to the software application did not have an intended effect. In response to determining that the fingerprint is present in the software application executing on the processor, it is recognized that the optimization to the software application has the intended effect.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: November 15, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Giles R. Frazier, Michael Karl Gschwind, Christian Jacobi, Anthony Saporito, Chung-Lung K. Shum
  • Patent number: 9471314
    Abstract: According to an aspect, branch prediction in a processing system that includes a primary branch predictor and an auxiliary perceptron branch predictor is provided. The primary branch predictor and the auxiliary perceptron branch predictor are searched to make a branch prediction. A perceptron magnitude of a perceptron branch predictor from the auxiliary perceptron branch predictor is compared to a magnitude usage limit. An auxiliary predictor result from the auxiliary perceptron branch predictor is selected as the branch prediction based on the perceptron magnitude exceeding the magnitude usage limit. A primary predictor result from the primary branch predictor is selected as the branch prediction based on the perceptron magnitude not exceeding the magnitude usage limit.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: October 18, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: James J. Bonanno, Michael J. Cadigan, Jr., Adam B. Collura, Daniel Lipetz
  • Patent number: 9454376
    Abstract: Provided is a processor with a multi-pipeline fetch structure or a multi-cycle cache structure, including: an integer core which reads instruction transmitted from a lower block, executes an operation corresponding to the instruction, and transmits an instruction address to the lower block; an instruction buffer which stores instruction data which are requested by the integer core by using the instruction address and transmits the instruction data in response to the request of the integer core; and an instruction cache which stores a portion of data of a program memory and transmit the data to the instruction buffer in response to the request of the instruction buffer.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: September 27, 2016
    Assignee: ADVANCED DIGITAL CHIPS INC.
    Inventors: Young Ho Cha, Kwang Ho Lee, Kwan Young Kim, Byung Gueon Min