Abstract: An apparatus, method and computer program, the apparatus comprising processing circuitry to execute instructions, issue circuitry to issue the instructions for execution by the processing circuitry, and candidate instruction storage circuitry to store a plurality of condition-dependent instructions, each specifying at least one condition. The issue circuitry is configured to issue a given condition-dependent instruction in response to a determination or a prediction of the at least one condition specified by the given condition-dependent instruction being met, and when the given condition-dependent instruction is a sequence-start instruction, the issue circuitry is responsive to the determination or prediction to issue a sequence of instructions comprising the sequence-start instruction and at least one subsequent instruction.

Abstract: An apparatus has processing circuitry, load tracking circuitry and load prediction circuitry to determine a prediction for a predicted load operation. It is determined whether the prediction is correct, and whether the tracking information indicates that, for a given younger load operation issued before it is known whether the prediction is correct, there is a risk of second target data associated with that given load operation having changed after having been loaded. Independent of whether the addresses of the predicted load operation and younger load operation correspond, at least the given load operation is re-processed when the prediction is correct and the tracking information indicates there is a risk of the second target data having changes after being loaded. This protects against ordering violations.

Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

Abstract: Performing branch predictor training using probabilistic counter updates in a processor is disclosed herein. In some aspects, a branch predictor training circuit of a processor is configured to determine whether a first branch prediction generated for a first conditional branch instruction by a branch predictor circuit of the processor is correct. Based on determining whether the first branch prediction is correct, the branch predictor training circuit probabilistically updates a first counter, corresponding to the first branch prediction, of a plurality of counters of a first branch predictor table of a plurality of branch predictor tables.

Abstract: Apparatus and methods are disclosed for throttling processor operation in block-based processor architectures. In one example of the disclosed technology, a block-based instruction set architecture processor includes a plurality of processing cores configured to fetch and execute a sequence of instruction blocks. Each of the processing cores includes function resources for performing operations specified by the instruction blocks. The processor further includes a core scheduler configured to allocate functional resources for performing the operations. The functional resources are allocated for executing the instruction blocks based, at least in part, on a performance metric. The performance metric can be generated dynamically or statically based on branch prediction accuracy, energy usage tolerance, and other suitable metrics.

Abstract: Methods and systems for analog-to-digital conversion using two side branches that may be operated with overlapped timing such that a sampling phase may be overlapped with a previous conversion phase. Some embodiments provide a method of successive approximation A/D converting, comprising sampling a first signal onto a first capacitor that is configured to selectively couple to an analog input of a comparator, sampling a second signal onto capacitors that are coupled to a second analog input of the comparator and configured for charge redistribution successive approximation A/D conversion; carrying out, based on the first signal and the second signal, a charge redistribution successive approximation A/D conversion using the capacitors; and while carrying out the charge redistribution successive approximation A/D conversion based on the first and second signals, sampling a third signal onto a third capacitor that is configured to selectively couple to the analog input of a comparator.

Abstract: An execution method includes supplying of a machine code, the machine code being formed by a succession of base blocks and each base block being associated with a signature and comprising instructions to be protected. Each instruction to be protected is immediately preceded or followed by an instruction for constructing the value of the signature associated with the base block. Each construction instruction is coded on strictly less than N bits, and each word of the machine code which comprises at least one portion of one of said instructions to be protected also comprises one of the construction instructions so that A is not possible to load an instruction to be protected into an execution file, without at the same time loading a construction instruction which modifies the value of the signature associated with the base block when it is executed.

Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N-1), and the branch history in table T(N-1) is of greater length than the branch history of table T(N-2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

Abstract: Techniques are disclosed relating to signature-based instruction prefetching. In some embodiments, processor pipeline circuitry executes a computer program that includes control transfer instructions, such that the execution follows a taken path through the computer program. First signature prefetch table circuitry indicates prefetch addresses for signatures generated using a first signature generation technique and second signature prefetch table circuitry indicates prefetch addresses for signatures generated using a second, different signature generation technique. Signature prefetch circuitry, in response to a prefetch training event, determines a first signature according to the first technique and a second signature according to the second technique and selects one but not both of the first and second signature prefetch tables to train using the first signature or the second signature.

Abstract: A data processing apparatus is provided that includes global-history prediction circuitry that provides a prediction of an outcome of a given control flow instruction based on a result of execution of one or more previous control flow instructions. Correction circuitry provides a corrected prediction of the global-history prediction circuitry in respect of the given control flow instruction and cache circuitry, separate from the correction circuitry, stores the corrected prediction in respect of the given control flow instruction.

Abstract: Disclosed is a computer-implemented method to increase the efficiency of a prefetch system. The method includes receiving a system call including an instruction address. The method includes determining a confidence score. The method further includes creating an entry, including the instruction address, an associated data address, and the confidence score. The method includes determining the instruction address is not present in a history table, where the history table includes a plurality of entries. The method further includes determining, in response to adding the first entry to the history table, a second entry is evicted from the history table. The method includes entering the second entry into a filter table in response to determining the second confidence score is a moderate confidence score, where the moderate confidence score is any confidence score that is greater than a predefined low threshold and less than a predefined high threshold.

Abstract: Exemplary aspects disclosed herein include detecting a repetitive pattern in an instruction pipeline of a processor to reduce repeated fetching. The processor includes a pattern record circuit configured to receive information in a data stream (e.g., instructions or consumed data) in the instruction pipeline. The pattern record circuit includes a first in, first out (FIFO) table circuit that contains an input record column and plurality of additional adjacent record columns. As new data occurs in the data stream, the data record circuit is configured to sequentially record next incoming data from the data stream into a next input entry of an input record column and then shift previously recorded data into adjacent entries of adjacent record columns. The distance between the input record column and the additional record column that has matching data is the distance in the data stream between a reoccurrence of data in the data stream.

Abstract: The disclosure provides a database operation method and apparatus. The method comprises: sequentially acquiring, during a process of executing a target transaction by an application server, database operation commands executed by the application server for the target transaction; executing a prediction algorithm on the database operation commands, returning predicted execution results to the application server so that the application server determines a next to-be-executed database operation command, and locally recording the database operation commands and predicted execution data generated from the executing of the prediction; and when acquiring a transaction commit command regarding the target transaction, controlling a database corresponding to the application server to actually execute the target transaction according to the locally recorded database operation commands and the predicted execution data. The disclosed embodiments improve transaction execution efficiency and increase transaction throughput.

Abstract: Described herein are techniques for performing ray tracing operations. A command processor executes custom instructions for orchestrating a ray tracing pipeline. The custom instructions cause the command processor to perform a series of loop iterations, each at a particular recursion depth. In a first loop iteration, a ray generation shader is executed that triggers execution of a trace ray operation. In any other iteration, zero or more shaders are executed based on the contents of a shader queue. Any shader may trigger execution of a trace ray operation. The trace ray operation determines whether a ray specified by the shader intersects a triangle. The ray trace operation places shader entries into a shader queue, at the current recursion depth plus 1. The command processor updates the current recursion depth based on whether a trace ray operation is executed. The loop ends when the recursion depth is less than a threshold.

Abstract: A system and method for efficiently protecting branch prediction information. In various embodiments, a computing system includes at least one processor with a branch predictor storing branch target addresses and security tags in a table. The security tag includes one or more components of machine context. When the branch predictor receives a portion of a first program counter of a first branch instruction, and hits on a first table entry during an access, the branch predictor reads out a first security tag. The branch predictor compares one or more components of machine context of the first security tag to one or more components of machine context of the first branch instruction. When there is at least one mismatch, the branch prediction information of the first table entry is not used. Additionally, there is no updating of any branch prediction training information of the first table entry.

Abstract: An electronic device includes a processor, a branch predictor in the processor, and a predictor controller in the processor. The branch predictor includes multiple prediction functional blocks, each prediction functional block configured for generating predictions for control transfer instructions (CTIs) in program code based on respective prediction information, the branch predictor configured to select, from among predictions generated by the prediction functional blocks for each CTI, a selected prediction to be used for that CTI. The predictor controller keeps a record of prediction functional blocks from which the branch predictor previously selected predictions for CTIs. The predictor controller uses information from the record for controlling which prediction functional blocks are used by the branch predictor for generating predictions for CTIs.

Abstract: Systems, methods, and apparatuses relating to instructions to reset software thread runtime property histories in a hardware processor are described. In one embodiment, a hardware processor includes a hardware guide scheduler comprising a plurality of software thread runtime property histories; a decoder to decode a single instruction into a decoded single instruction, the single instruction having a field that identifies a model-specific register; and an execution circuit to execute the decoded single instruction to check that an enable bit of the model-specific register is set, and when the enable bit is set, to reset the plurality of software thread runtime property histories of the hardware guide scheduler.

Abstract: Systems and methods are disclosed for secure predictors for speculative execution. Some implementations may eliminate or mitigate side-channel attacks, such as the Spectre-class of attacks, in a processor. For example, an integrated circuit (e.g., a processor) for executing instructions includes a predictor circuit that, when operating in a first mode, uses data stored in a set of predictor entries to generate predictions. For example, the integrated circuit may be configured to: detect a security domain transition for software being executed by the integrated circuit; responsive to the security domain transition, change a mode of the predictor circuit from the first mode to a second mode and invoke a reset of the set of predictor entries, wherein the second mode prevents the use of a first subset of the predictor entries of the set of predictor entries; and, after completion of the reset, change the mode back to the first mode.

Abstract: Branch prediction in an instruction using a tag orientation predictor (TOP) is described. When a branch instruction is hotly mis-predicted by a hybrid branch predictor, the branch is tracked over a longer time period using the TOP. Once the TOP has collected enough data to confidently predict a branch prediction, the TOP is used to override a branch prediction from the hybrid predictor when the TOP branch prediction.

Abstract: An apparatus comprises: processing circuitry 18 to process instructions from a plurality of software workloads; a branch prediction cache 40-42 to cache branch prediction state data selected from a plurality of sets of branch prediction state data 60 stored in a memory system 30, 32, 34, each set of branch prediction state data corresponding to one of said plurality of software workloads; and branch prediction circuitry 4 to predict an outcome of a branch instruction of a given software workload based on branch prediction state data cached in the branch prediction cache from the set of branch prediction state data corresponding to said given software workload. This is useful for mitigating against speculation side-channel attacks which exploit branch mispredictions caused by malicious training of a branch predictor.

Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and a previous calculation result of the arithmetic and logic unit.

Abstract: Described herein are systems and methods for dynamic designation of instructions as sensitive. For example, some methods include detecting that a first instruction of a first process has been designated as a sensitive instruction; checking whether a sensitive handling enable indicator in a process state register storing a state of the first process is enabled; responsive to detection of the sensitive instruction and enablement of the sensitive handling enable indicator, invoking a constraint for execution of the first instruction; executing the first instruction subject to the constraint; and executing a second instruction of the first process without the constraint.

Abstract: A method is provided for reducing memory consumption by a rule engine. The method includes receiving attack trees, each having nodes and edges. Each node represents a security event and is associated with a detection rule for detecting an occurrence thereof. Each edge connects a respective node pair. The method includes assigning a watchpoint to each leaf node. The method includes moving the watchpoint assigned to any leaf node to a next upstream node, responsive to detecting an occurrence of the security event represented by the leaf node. The method includes erasing the watchpoint assigned to all downstream nodes relative to the next upstream node, responsive to the next upstream node being connected to a next downstream node using an edge having an “OR” join type. Only the rules for nodes currently having the watchpoint assigned are loaded into a memory device during runtime, while excluding rules for remaining nodes.

Abstract: In an embodiment, an indirect branch predictor generates indirect branch predictions for indirect branch instructions. For relatively static branch instructions, the indirect branch predictor may be configured to use a PC corresponding to the indirect branch instruction to generate a target prediction. The indirect branch predictor may be configured to identify at least one dynamic indirect branch instruction and may use a different PC than the PC corresponding to the indirect branch instruction to generate the target prediction (e.g. the most recent previous PC associated with a taken branch (“the previous taken PC”). For some dynamic indirect branch instructions, the previous taken PC may disambiguate different target addresses (e.g. there may be a correlation between the previous taken PC and the target address of the indirect branch instruction).

Abstract: Circuitry comprises a prediction register having one or more entries each storing prediction data; prediction circuitry configured to map a value of the stored prediction data to a prediction of whether or not a branch represented by a given branch instruction is predicted to be taken, according to a data mapping; and control circuitry configured to selectively vary the data mapping between the prediction and the value of the stored prediction data.

Abstract: The present disclosure relates to a safety system having a memory unit configured to store a series of executable instructions. In some embodiments, the executable instructions are grouped into code parts, and each code part is assigned a predefined code value. A processor is configured to execute the series of executable instructions, and to output the predefined code values respectively as the code parts are executed. A program flow monitoring (PFM) unit is configured to respectively receive the predefined code values from the processor, such that the PFM unit generates an error-checking value from the predefined code values. A verification unit is configured to compare the error-checking value to an expected return value to determine whether the series of executable instructions executed properly.

Abstract: An apparatus and method are described, the apparatus comprising processing circuitry to perform data processing operations, microarchitecture circuitry used by the processing circuitry during performance of the data processing operations, and an interface to receive interrupt requests. The processing circuitry is responsive to a received interrupt request to perform an interrupt service routine, and the apparatus comprises prediction circuitry to determine a predicted time of reception of a next interrupt of at least one given type. The apparatus also comprises microarchitecture control circuitry arranged to vary a configuration of the microarchitecture circuitry between a performance based configuration and a responsiveness based configuration in dependence on the predicted time, so as to seek to increase the responsiveness of the apparatus to interrupts as the predicted time is approached.

Abstract: In a general aspect, a method can include: executing an operation of a program that loads an arbitrarily chosen value of an initial data item of a series of ordered data; executing a series of calculation operations distributed in the program, that calculate a current data item based on a preceding data item; performing a final calculation operation of the series of operations that calculates a final data item of the data series; and executing an operation of the program that detects a program execution error by comparing the current data item of the data series with an expected value of the current data item or the final data item, the final data item having an expected value that is independent of the number of data items in the data series and is calculated based on the current data item of the data series and a final compensation data item.

Abstract: A fusion opportunity is detected for a sequence of instructions. The sequence of instructions include an indication of an affiliated location and an indication of an affiliated derived location. Based on the detecting, a value to be stored in the affiliated derived location is generated. The value is a predicted value. The value is stored in the affiliated derived location, and the affiliated derived location is accessed to use the value by one or more instructions executing within the computing environment.

Abstract: A processor device capable of raising a hit rate of branch destination prediction is provided. Every time a load instruction to a data cache is generated, an equivalent value judgment circuit judges accord/disaccord of present load data and previous load data from a corresponding line. In an N bit region, as history records, a judgment history record circuit records judgment results of N times by the equivalent value judgment circuit before a conditional branch instruction is generated. When the conditional branch instruction is generated, based on the history records in the N bit region, a branch prediction circuit predicts the same branch destination as the previous branch destination obtained by a previous execution result of the conditional branch instruction or a branch destination different from the previous destination. Further, the branch prediction circuit issues an instruction fetch direction of the predicted branch destination to a processor main-body circuit.

Abstract: In one embodiment, a microprocessor, comprising: first logic configured to detect that a fetched cache address matches at least one of two previous cache addresses; and second logic configured to adjust a branch pattern used for conditional branch prediction based on the match and combine the cache address with the adjusted branch pattern to form a conditional branch predictor address.

Abstract: Circuitry comprises memory circuitry providing a plurality of memory locations; location selection circuitry to select a set of one or more of the memory locations by which to access a data item according to a mapping relationship between an attribute of the data item and the set of one or more memory locations; the location selection circuitry being configured to initiate an allocation operation for a data item when that data item is to be newly stored by the memory circuitry and the selected set of one or more of the memory locations are already occupied by one or more other data items, the allocation operation comprising an operation to replace at least a subset of the one or more other data items from the set of one or more memory locations by the newly stored data item; and detector circuitry to detect a data access conflict in which a group of two or more data items having different respective attributes are mapped by the mapping relationship to the same set of one or more memory locations; the locat

Abstract: Techniques are disclosed for address manipulation using indices and tags. A first index is generated from bits of a processor program counter, where the first index is used to access a branch predictor bimodal table. A first branch prediction is provided from the bimodal table, based on the first index. The first branch prediction is matched against N tables, where the tables contain prior branch histories, and where: the branch history in table T(N) is of greater length than the branch history of table T(N?1), and the branch history in table T(N?1) is of greater length than the branch history of table T(N?2). A processor address is manipulated using a greatest length of hits of branch prediction matches from the N tables, based on one or more hits occurring. The branch predictor address is manipulated using the first branch prediction from the bimodal table, based on zero hits occurring.

Abstract: An arithmetic processing apparatus includes weight tables each configured to store weighting factors in one-to-one correspondence with indexes associated with instruction addresses, a first weight arithmetic unit configured to perform a first operation and a second operation based on the weighting factors retrieved from the weight tables in response to an instruction fetch address, the first operation producing a first value for branch prediction for the instruction fetch address, the second operation producing second values for future branch prediction, and a second weight arithmetic unit configured to perform, in parallel with the second operation, a third operation equivalent to the second operation based on the weighting factors retrieved from the weight tables in response to an address of a completed branch instruction, wherein the second values stored in the first weight arithmetic unit are replaced with the third values upon detection of a wrong branch prediction.

Abstract: An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

Abstract: Embodiments described herein provide for system and methods to enable an operating environment that supports multi-OS applications. One embodiment provides for a non-transitory machine-readable medium storing instructions to perform operations comprising parsing a set of object files to generate a graph of code and data for each object file, group elements from the graphs of code and data into a master graph of elements, and generating an annotated output file including compiled code for the dynamic library, the annotated output file having a header and a first set of load commands, the first set of load commands to specify multiple target platforms for the dynamic library.

Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions; and a branch predictor to predict a branch outcome for a given branch instruction as one of taken and not-taken, based on branch prediction state information indexed based on at least one property of the given branch instruction. In a static branch prediction mode of operation, the branch predictor predicts the branch outcome based on static values of the branch prediction state information set independent of actual branch outcomes of branch instructions which are executed by the processing circuitry while in the static branch prediction mode. The static values of the branch prediction state information are programmable.

Abstract: In one embodiment, an apparatus includes a context-based prediction circuit to receive an instruction address for a branch instruction and a plurality of predictions associated with the branch instruction from a global prediction circuit. The context-based prediction circuit may include: a table having a plurality of entries each to store a context prediction value for a corresponding branch instruction; and a control circuit to generate, for the branch instruction, an index value to index into the table, the control circuit to generate the index value based at least in part on at least some of the plurality of predictions associated with the branch instruction and the instruction address for the branch instruction. Other embodiments are described and claimed.

Abstract: A method for verifying program flow during execution of a software program in a computer system is disclosed. Program code of the software program includes multiple program instructions and checkpoint data structures, where a given checkpoint data structure is associated with a given program instruction and is linked to at least one other checkpoint data structure. A fault monitor circuit may receive a particular checkpoint data structure and compare the particular checkpoint data structure to a previously received checkpoint data structure that is associated with another program instruction. Based on results of the comparison, the software fault monitor circuit may signal a program flow error.

Abstract: A fusion opportunity is detected for a sequence of instructions. The sequence of instructions include an indication of an affiliated location and an indication of an affiliated derived location. Based on the detecting, a value to be stored in the affiliated derived location is generated. The value is a predicted value. The value is stored in the affiliated derived location, and the affiliated derived location is accessed to use the value by one or more instructions executing within the computing environment.

Abstract: A method, system and computer program product for detecting potential failures in a continuous delivery pipeline. A machine learning model is created to predict whether changed portion of codes under development at various stages of the continuous delivery pipeline will result in a pipeline failure. After creating the machine learning model, log file(s) may be received that were generated by development tool(s) concerning a changed portion of code under development at a particular stage of the continuous delivery pipeline. The machine learning model provides relationship information between the log file(s) and the changed portion of code. A message is then generated and displayed based on this relationship information, where the message may provide a prediction or a recommendation concerning potential failures in the continuous delivery pipeline. In this manner, the potential failures in the continuous delivery pipeline may be prevented without requiring context switching.

Abstract: In one example in accordance with the present disclosure, enforcement of memory reference object loading indirection is described. According to a method, at a register, it is determined from an indirection counter of a first memory referencing object (MRO) in one of a number of registers of a processor of the computing device, whether a second MRO is loadable. When the indirection counter of the first MRO indicates a second MRO is loadable, the second MRO is loaded from the memory device to one of the number of registers. The second MRO also includes an indirection counter. The indirection counter of the loaded second MRO is changed, at the register that contains it, based on the indirection counter of the first MRO to enforce a degree of MRO loading indirection. Further, MRO loading is prohibited when an indirection counter reaches zero by invalidating a capability counter of a subsequent MRO at the register.

Abstract: The present disclosure is directed to systems and methods for mitigating or eliminating the effectiveness of a side channel attack, such as a Spectre type attack, by limiting the ability of a user-level branch prediction inquiry to access system-level branch prediction data. The branch prediction data stored in the BTB may be apportioned into a plurality of BTB data portions. BTB control circuitry identifies the initiator of a received branch prediction inquiry. Based on the identity of the branch prediction inquiry initiator, the BTB control circuitry causes BTB look-up circuitry to selectively search one or more of the plurality of BTB data portions.

Abstract: Systems and method provide for generation of a unique key pair having a public and private key for an individual device. The public key may be embedded (e.g., burned or etched) into a central processing unit (CPU) during the manufacturing process. The burning or etching process may make the public key unmodifiable. The matching private key may then be stored in a secure database. Software code may be available through download over a computer based network (e.g., the Internet). A request may be made for the software code. Prior to delivery, the software code may be digitally signed with the private key corresponding to the individual device. Logic programmed into the CPU may prevent the execution of code that is not signed with the private key that corresponds to the public key.

Abstract: Embodiments are directed to a method for optimizing performance of a microprocessor. The method includes monitoring the performance of the microprocessor in each of a plurality of performance modes. The method further includes choosing a performance mode based on the monitoring. Thereafter, using the performance mode for a predetermined amount of time. Each of the plurality of performance modes is a branch prediction mode.

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

Abstract: The bytecode processing device includes a branch target buffer including a tag field, a target address field corresponding to the tag field and an operation code bit field for representing whether a value stored in the tag field is an operation code, a bytecode fetch unit configured to fetch a bytecode including an operation code, an operation code extraction unit configured to extract the operation code from the bytecode, a branch target buffer search unit configured to perform a search to determine whether the extracted operation code exists in the tag field of the branch target buffer, and if the operation code exists in the tag field, extract a target address corresponding to the operation code from the target address field, and a bytecode execution unit configured to execute the bytecode by branching to the target address.

Abstract: An apparatus and method are provided for using predicted result values. The apparatus has a processing unit that comprises processing circuitry for executing a sequence of instructions, and value prediction circuitry for identifying a predicted result value for at least one instruction. A result producing structure is provided that is responsive to a request issued from the processing unit when the processing circuitry is executing a first instruction, to produce a result value for the first instruction and return that result value to the processing unit. While waiting for the result value from the result producing structure, the processing circuitry can be arranged to speculatively execute at least one dependent instruction using a predicted result value for the first instruction as obtained from the value prediction circuitry.

Abstract: Table of Contents (TOC)-setting instructions are replaced in code with TOC predicting instructions. A determination is made as to whether code includes an instruction sequence to compute a value of a pointer to a reference data structure, such as a TOC. Based on determining the code includes the instruction sequence, the instruction sequence in the code is replaced with a set instruction. The set instruction predicts the value of the pointer to the reference data structure.

Abstract: In one embodiment, a branch prediction circuit includes: a first bimodal predictor having a first plurality of entries each to store first prediction information for a corresponding branch instruction; a global predictor having a plurality of global entries each to store global prediction information for a corresponding branch instruction; a second bimodal predictor having a second plurality of entries each to store second prediction information for a corresponding branch instruction; a monitoring table having a plurality of monitoring entries each to store a counter value based on the second prediction information for a corresponding branch instruction; and a control circuit to allocate a global entry within the global predictor based at least in part on the counter value of a monitoring entry of the monitoring table for a corresponding branch instruction. Other embodiments are described and claimed.