Abstract: Embodiments relate to confidence threshold-based opposing path execution for branch prediction. An aspect includes determining a branch prediction for a first branch instruction that is encountered during execution of a first thread, wherein the branch prediction indicates a primary path and an opposing path for the first branch instruction. Another aspect includes executing the primary path by the first thread. Another aspect includes determining a confidence of the branch prediction and comparing the confidence of the branch prediction to a confidence threshold. Yet another aspect includes, based on the confidence of the branch prediction being less than the confidence threshold, starting a second thread that executes the opposing path of the first branch instruction, wherein the second thread is executed in parallel with the first thread.

Abstract: A circuit for implementing a branch target buffer. The branch target buffer may include a memory that stores a plurality of entries. Each entry may include a tag value, a target value, and a prediction accuracy value. A received index value corresponding to an indirect branch instruction may be used to select one of entries of the plurality of entries, and a received tag value may then be compared to the tag value of the selected entries in the memory. An entry in the memory may be selected in response to a determination that the received tag does not match the tag value of compared entries. The selected entry may be allocated to the indirect instruction branch dependent upon the prediction accuracy values of the plurality of entries.

Abstract: A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.

Abstract: Branch instructions are provided for improved execution performance. The branch instruction includes one or more paths that are marked as a safe path for execution. If a marked path is executed based on a branch prediction, the execution continues until completion after it is determined that the other path is the correct path.

Abstract: A processing system to reduce energy consumption and improve performance in a processor, controlled by compiler inserted information ahead of a selected branch instruction, to statically expose and control how the prediction should be completed and which mechanism should be used to achieve energy and performance efficiency.

Abstract: A branch target address table is provided for each branch instruction having a plurality of branch targets. Each branch target address table stores a history of a plurality of branch target addresses determined in the past by executing a corresponding branch instruction. A branch target prediction unit predicts a predicted branch target address with respect to a branch instruction with reference to the history of branch target addresses stored in the branch target address table corresponding to the branch instruction. The predicted branch target address obtained as a result of the prediction is stored, for example, in a predicted branch target address storage unit in association with the branch instruction, and is referenced by an instruction fetch control unit at the time of prefetching a branch target instruction.

Abstract: Techniques are described for enabling and/or disabling a secondary jump execution unit (JEU) in a micro-processor. The secondary JEU is incorporated in the micro-processor to operate concurrently with a primary JEU, and to enable the handling of simultaneous branch mispredicts on multiple branches. Activation and deactivation of the secondary JEU may be controlled by a pressure counter or a confidence counter. A pressure counter mechanism increments a count for each branch operation executed within the processor and decrements the count by a decay value during each cycle. A confidence counter mechanism increments a count for each correctly predicted branch, and decrements the count for each mispredict. Each counter signals an activation component, such as a port binding hardware component, to begin binding micro-operations to the secondary JEU when the counter exceeds an activation threshold. The counter mechanism may be thread-agnostic or thread-specific.

Abstract: Establishing a branch target instruction cache (BTIC) entry for subroutine returns to reduce pipeline bubbles, and related systems, methods, and computer-readable media are disclosed. In one embodiment, a method of establishing a BTIC entry includes detecting a subroutine call in an execution pipeline. In response, at least one instruction fetched sequential to the subroutine call is written as a branch target instruction in a BTIC entry for a subroutine return. A next instruction fetch address is calculated, and is written into a next instruction fetch address field in the BTIC entry. In this manner, the BTIC may provide correct branch target instruction and next instruction fetch address data for the subroutine return, even if the subroutine return is encountered for the first time or the subroutine is called from different calling locations.

Abstract: In one embodiment, a processor includes at least one execution unit. The processor also includes prediction gating logic coupled to the at least one execution unit. The prediction gating logic may be to, in response to a first prediction that a first branch is taken, obtain a distance value to a second branch using a target array, and gate a branch prediction unit for a number of instruction blocks equal to the distance value to the second branch. Other embodiments are described and claimed.

Abstract: An apparatus includes a network interface, memory, and a processor. The processor is coupled with the network interface and memory. The processor is configured to determine that an instruction instance is a branch instruction instance. Responsive to a determination that an instruction instance is a branch instruction instance, the processor is configured to obtain a branch prediction for the branch instruction instance and a confidence value of the branch prediction. The processor is further configured to determine that the confidence for the branch prediction is low based on the confidence value, and responsive to such a determination, generate predicated instruction instances based on the branch instruction instance.

Abstract: Embodiments of the disclosure include mitigating instruction prediction latency with independently filtered instruction prediction presence predictors coupled to the processor pipeline. The prediction presence predictor includes a plurality of presence predictors configured to each receive an instruction address in parallel and to generate an unfiltered indication of an associated instruction prediction. The prediction presence predictor includes a plurality of dynamic filters that are each coupled to one of the plurality of presence predictors. Each dynamic filter is configured to block the unfiltered indications based on a performance of the presence predictor it is coupled to. The prediction presence predictor further including stall determination logic coupled to the plurality of dynamic filters.

Abstract: Methods and systems for executing a code stream of non-native binary code on a computing system are disclosed. One method includes parsing the code stream to detect a plurality of elements including one or more branch destinations, and traversing the code stream to detect a plurality of non-native operators. The method also includes executing a pattern matching algorithm against the plurality of non-native operators to find combinations of two or more non-native operators that do not span across a detected branch destination and that correspond to one or more target operators executable by the computing system. The method further includes generating a second code stream executable on the computing system including the one or more target operators.

Abstract: A method and apparatus to utilize a branch prediction scheme that limits the expenditure of power and the area consumed caused by branch prediction schemes is provided. The method includes accessing a first entry and a second entry of the data structure, wherein each entry stores a portion of a predicted target address, determining the predicted target address using the portion of the predicted target address stored in the first entry and a portion of a branch address of a fetched branch instruction for a fetched branch instruction of a first type, and determining the predicted target address using the portion of the predicted target address stored in the first entry and the portion of the predicted target address stored in the second entry for a fetched branch instruction of a second type.

Abstract: A computer-readable storage medium, method and system for optimization-level aware branch prediction is described. A gear level is assigned to a set of application instructions that have been optimized. The gear level is also stored in a register of a branch prediction unit of a processor. Branch prediction is then performed by the processor based upon the gear level.

Abstract: Embodiments relate to instruction filtering. An aspect includes a computer-implemented method for instruction filtering. The method includes detecting, by a processor, a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in a tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. The method further includes marking, by the processor, instruction text of the subsequently fetched instruction to indicate that the subsequently fetched instruction is a previously executed tracked instruction based on the indication of the tracked instruction from the tracking array.

Abstract: A method and apparatus are provided for increasing the accuracy of a branch predictor. A branch prediction table provides a first instance of a branch prediction value associated with an instruction being speculatively executed a first time; and provides a second instance of the branch prediction value associated with the instruction being speculatively executed a second rime. The first instance of the branch prediction value may be subsequently revised after the instruction associated with the first instance of the branch prediction value is retired. Information regarding whether that branch instruction was accurately predicted may then be used to update the branch prediction table and the second instance of the branch prediction value.

Abstract: Techniques are disclosed relating to improving the performance of branch prediction in processors. In one embodiment, a processor is disclosed that includes a branch prediction unit configured to predict a sequence of instructions to be issued by the processor for execution. The processor also includes a pattern detection unit configured to detect a pattern in the predicted sequence of instructions, where the pattern includes a plurality of predicted instructions. In response to the pattern detection unit detecting the pattern, the processor is configured to switch from issuing instructions predicted by the branch prediction unit to issuing the plurality of instructions. In some embodiments, the processor includes a replay unit that is configured to replay fetch addresses to an instruction fetch unit to cause the plurality of predicted instructions to be issued.

Abstract: Instruction cache memory having a plurality of memory (for example, cache WAY), means 3 for storing prediction data of a conditional branch of a branch instruction being taken or not taken and for storing prediction data of memory storing the branch instruction data of the plurality of memory when the prediction is the branch being taken, and means for, when an instruction to be executed is a branch instruction, outputting a read active control signal to the plurality of memories 1 by using two pieces of prediction data obtained from the means by an index corresponding to the branch instruction, are comprised.

Abstract: A branch target address cache (BTAC) caches history information associated with branch and switch key instructions previously executed by a microprocessor. The history information includes a target address and an identifier (index into a register file) for identifying key values associated with each of the previous branch and switch key instructions. A fetch unit receives from the BTAC a prediction that the fetch unit fetched a previous branch and switch key instruction and receives the target address and identifier associated with the fetched branch and switch key instruction. The fetch unit also fetches encrypted instruction data at the associated target address and decrypts (via XOR) the fetched encrypted instruction data based on the key values identified by the identifier, in response to receiving the prediction. If the BTAC predicts correctly, a pipeline flush normally associated with the branch and switch key instruction is avoided.

Abstract: A multi-mode register file is described. In one embodiment, the multi-mode register file includes an operand in a first mode. The multi-mode register file further includes auxiliary information which replaces the operand in a second mode.

Abstract: A microprocessor includes a storage element that stores decryption key data and a fetch unit that fetches and decrypts program instructions using a value of the decryption key data stored in the storage element. The fetch unit fetches an instance of a branch and switch key instruction and decrypts it using a first value of the decryption key data stored in the storage element. If the branch is taken, the microprocessor loads the storage element with a second value of the decryption key data for subsequent use by the fetch unit to decrypt an instruction fetched at a target address specified by the branch and switch key instruction. If the branch is not taken, the microprocessor retains the first value of the decryption key data in the storage element for subsequent use by the fetch unit to decrypt an instruction sequentially following the branch and switch key instruction.

Abstract: A method of predicting a backward conditional branch instruction used in a vector partitioning loop includes detecting the first conditional branch instruction that occurs after consumption of a dependency index vector by a predicate generating instruction. The dependency index vector includes information indicative of a number of iterations of the vector partitioning loop, and the conditional branch instruction may branch backwards when taken. The conditional branch instruction may then be predicted to be taken a number of times that is determined by the dependency index vector.

Abstract: A microprocessor includes a memory that stores an exception handler to handle an exception condition. The exception handler is a non-user program private to the microprocessor and includes a conditional branch instruction. A first fetch unit fetches instructions of a user program that includes a user program instruction that causes the exception condition. An execution unit executes the user program instructions fetched by the first fetch unit and executes instructions of the exception handler. The execution unit also saves a state in response to detecting the exception condition caused by the user program instruction. A second fetch unit fetches the exception handler instructions from the memory and resolves the conditional branch instruction based on the saved state without sending the conditional branch instruction to the execution unit to resolve the conditional branch instruction.

Abstract: Branch prediction for indirect jumps, including: receiving, by a branch prediction module, a branch address for each of a plurality of executed branch instructions; receiving, by the branch prediction module, an instruction address of a current branch instruction; creating, by the branch prediction module, an execution path identifier in dependence upon the branch address for each of the plurality of executed branch instructions and the instruction address of the current branch instruction; and searching, by the branch prediction module, a branch prediction table for an entry that matches the execution path identifier.

Abstract: The present invention discloses a starting method of a WiMAX terminal and a terminal thereof, wherein, the starting method comprises: step S202, calculating a load command and a firmware required to be loaded for starting the terminal in advance to obtain a first firmware Hash and a first load command Hash, and storing the first firmware Hash and the first load command Hash in a predefined memory of the terminal; step S204, in response to a starting operation of the terminal, performing starting process and starting a boot loader; step S206, the boot loader executing the load command transmitted by a driver of the terminal to download the firmware to the terminal; step S208, the boot loader calculating a second firmware Hash of the downloaded firmware and a second load command Hash of the load command transmitted by the driver; step 210, the boot loader judging whether the first firmware Hash matches with the second firmware Hash, and judging whether the first load command Hash matches with the second load co

Abstract: Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.

Abstract: Embodiments relate to selectively blocking branch instruction predictions. An aspect includes computer implemented method for performing selective branch prediction. The method includes detecting, by a processor, a branch-prediction blocking instruction in a stream of instructions and blocking, by the processor, branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.

Abstract: Embodiments relate to branch prediction preloading. A method for branch prediction preloading includes fetching a plurality of instructions in an instruction stream, and decoding a branch prediction preload instruction in the instruction stream. The method also includes determining, by a processing circuit, an address of a predicted branch instruction based on the branch prediction preload instruction, and determining, by the processing circuit, a predicted target address of the predicted branch instruction based on the branch prediction preload instruction. The method further includes identifying a mask field in the branch prediction preload instruction, and determining, by the processing circuit, a branch instruction length of the predicted branch instruction based on the mask field.

Abstract: Embodiments relate to asynchronous lookahead hierarchical branch prediction. An aspect includes a system for asynchronous lookahead hierarchical branch prediction. The system includes a first-level branch target buffer and a second-level branch target buffer coupled to a processing circuit. The processing circuit is configured to perform a method. The method includes receiving a search request to locate branch prediction information associated with a search address, and searching for an entry corresponding to the search request in the first-level branch target buffer. Based on failing to locate a matching entry in the first-level branch target buffer corresponding to the search request, a secondary search is initiated to locate entries in the second-level branch target buffer having a memory region corresponding to the search request. Based on locating the entries in the second-level branch target buffer, a bulk transfer of the entries is performed from the second-level branch target buffer.

Abstract: Embodiments relate to using a fast index tree for accelerated branch prediction. A system includes a branch target buffer, a FIT structure, and a processing circuit configured to perform a method. The method includes determining that searching of the branch target buffer is to be performed under FIT control. A current search address for searching of the branch target buffer is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from the FIT structure. The searching of the branch target buffer is re-indexed based on the FIT next-search address. It is determined whether the searching at the saved current search address located the branch prediction.

Abstract: Embodiments relate to using a fast index tree for accelerated branch prediction. A computer-implemented method includes determining, by a computer, that searching of a branch target buffer is to be performed under FIT control. A current search address is saved. The branch target buffer is searched at the saved current search address for a branch prediction. A FIT next-search address is determined based on reading branch taken and branch not taken paths for a next search level of predicted branches from a FIT structure. The searching is re-indexed based on the FIT next-search address. Based on locating the branch prediction, the searching is continued under FIT control with the current search address set based on the FIT next-search address. Based on failing to locate the branch prediction, the searching is re-indexed with the saved current search address, and the searching is performed without FIT control.

Abstract: A scalable processing system includes a memory device having a plurality of executable program instructions, wherein each of the executable program instructions includes a timetag data field indicative of the nominal sequential order of the associated executable program instructions. The system also includes a plurality of processing elements, which are configured and arranged to receive executable program instructions from the memory device, wherein each of the processing elements executes executable instructions having the highest priority as indicated by the state of the timetag data field.

Abstract: A method for suppressing branch misprediction behavior is contemplated in which a branch-optional instruction that would cause the flow of control to branch around instructions in response to a determination that a predicate vector is null is predicted not taken. However, in response to detecting that the prediction is incorrect, misprediction behavior is inhibited.

Abstract: The disclosure relates to predicting simple and polymorphic branch instructions. An embodiment of the disclosure detects that a program instruction is a branch instruction, determines whether a program counter for the branch instruction is stored in a program counter filter, and, if the program counter is stored in the program counter filter, prevents the program counter from being stored in a first level predictor.

Abstract: A method for outputting alternative instruction sequences. The method includes tracking repetitive hits to determine a set of frequently hit instruction sequences for a microprocessor. A frequently miss-predicted branch instruction is identified, wherein the predicted outcome of the branch instruction is frequently wrong. An alternative instruction sequence for the branch instruction target is stored into a buffer. On a subsequent hit to the branch instruction where the predicted outcome of the branch instruction was wrong, the alternative instruction sequence is output from the buffer.

Abstract: An apparatus and method for calculating flag bits is disclosed. The flag bits may be used in a processor utilizing branch predication. More particularly, the apparatus and method may be used to calculate a predicate that can be used by a branch unit to evaluate whether a branch is to be taken. In one embodiment, the apparatus is coupled to receive a condition code associated with an instruction, and flag bits generated responsive to execution of the instruction. The condition code is indicative of a condition to be checked resulting from execution of the instruction. The apparatus may then provide an indication of whether the condition is true.

Abstract: A data processing apparatus and method of data processing are provided. The data processing apparatus comprises execution circuitry configured to execute a sequence of program instructions. Checkpoint circuitry is configured to identify an instance of a predetermined type of instruction in the sequence of program instructions and to store checkpoint information associated with that instance. The checkpoint information identifies a state of the data processing apparatus prior to execution of that instance of the predetermined type of instruction, wherein the predetermined type of instruction has an expected long completion latency.

Abstract: A high-performance information processing technique permitting updating of an instruction buffer ready for effective prefetching to branch instructions and returning to the subroutine with a small volume of hardware is to be provided at low cost. It is an information processing apparatus equipped with a CPU, a memory, prefetch means and the like, wherein a prefetch address generator unit in the prefetch means decodes a branching series of instructions including at least one branched address calculating instruction and branching instruction to a branched address out of a current instruction buffer storing the series of instructions currently accessed by the CPU, and thereby looks ahead to the branching destination address. The information processing apparatus further comprises a RTS instruction buffer for storing a series of instructions of the return destinations of RTS instructions, and series of instructions stored in the current instruction buffer are saved into the RTS instruction buffer.

Abstract: One aspect of the embodiments utilizes a branch instruction predicting unit includes a history memory to store a branch address as history information, a selecting unit to select a storing place with reference to selection information for selecting either one of storing places when the branch address of the branch instruction is stored as the history information, In the case that there are a plurality of branch addresses to be stored at a storing place, when a first branch address is stored at a storing place, a second branch address is stored at a storing place in accordance with selection information updated by the updating unit.

Abstract: In one embodiment, a microprocessor is provided. The microprocessor includes a branch prediction unit. The branch prediction unit is configured to track the presence of branches in instruction data that is fetched from an instruction memory after a redirection at a target of a predicted taken branch. The branch prediction unit is selectively powered up from a powered-down state when the fetched instruction data includes a branch instruction and is maintained in the powered-down state when the fetched instruction data does not include an instruction branch in order to reduce power consumption of the microprocessor during instruction fetch operations.

Abstract: Methods and apparatus for restoring a meta predictor system upon detecting a branch or binary misprediction, are disclosed. An example apparatus may include a base misprediction history register to store a set of misprediction history values each indicating whether a previous branch prediction taken by a previous branch instruction was predicted correctly or incorrectly. The apparatus may comprise a meta predictor to detect a branch misprediction of a current branch prediction based at least in part on an output of the base misprediction history register. The meta predictor may restore the base misprediction history register based on the detecting of the branch misprediction. Additional apparatus, systems, and methods are disclosed.

Abstract: An electronic device includes a memory, a processor coupled to the memory, and one or more policies stored in the memory. The policies include a resource availability policy determining whether the processor should continue evaluating the software, and a job availability policy determining whether new jobs will be created for unexplored branches. The processor is configured to receive a job to be executed, evaluate the software, select a branch to explore and store an initialization sequence of one or more unexplored branches if a branch in the software is encountered, evaluate the job availability policy, decide whether to create a job for each of the unexplored branches based on the job availability policy, evaluate the resource availability policy, and decide whether to continue evaluating the software at the branch selected to explore based on the resource availability policy. The job indicates of a portion of software to be evaluated.

Abstract: Systems, apparatuses, and methods for determinative branch prediction indexing are described herein. The determinative branch prediction indexing method includes receiving a program counter address for a branch instruction, dynamically selecting a branch indexing scheme from a plurality of branch indexing schemes, and generating a branch prediction index based at least in part on selected branch indexing scheme and the program counter address. Other embodiments may be described and claimed.

Abstract: A method for managing branch instructions, the method includes: providing, to pipeline stages of a processor, multiple variable length groups of instructions; wherein each pipeline stage executes a group of instruction during a single execution cycle; receiving, at a certain execution cycle, multiple instruction fetch requests from multiple pipeline stages, each pipeline stage that generates an instruction fetch request stores a variable length group of instructions that comprises a branch instruction; sending to the fetch unit an instruction fetch command that is responsive to a first in order branch instruction in the pipeline stages; wherein if the first in order fetch command is a conditional fetch command then the instruction fetch command comprises a resolved target address; wherein the sending of the instruction fetch command is restricted to a single instruction fetch command per a single execution cycle.

Abstract: A method for suppressing branch misprediction behavior is contemplated in which a conditional branch instruction that would cause the flow of control to branch around instructions in response to a determination that a predicate vector is null is predicted not taken. However, in response to detecting that the prediction is incorrect, misprediction behavior is inhibited.

Abstract: A computer system may recognize a busy-wait loop in program instructions at compile time and/or may recognize busy-wait looping behavior during execution of program instructions. The system may recognize that an exit condition for a busy-wait loop is specified by a conditional branch type instruction in the program instructions. In response to identifying the loop and the conditional branch type instruction that specifies its exit condition, the system may influence or override a prediction made by a dynamic branch predictor, resulting in a prediction that the exit condition will be met and that the loop will be exited regardless of any observed branch behavior for the conditional branch type instruction. The looping instructions may implement waiting for an inter-thread communication event to occur or for a lock to become available. When the exit condition is met, the loop may be exited without incurring a misprediction delay.

Abstract: Declarations from an input source code are serialized into a stream of tokens produced by following each branch of a preprocessor conditional directive statement that interrupts a declaration. Tokens are labeled with a parsing path indicator corresponding to a parsing path induced by branches of a preprocessor conditional directive. The declarations that are formed along the different parsing paths are serialized by fetching the tokens that belong to the first parsing path in a first pass, and passing the tokens on to a next phase of a compiler. The pointer that marks the next token is repositioned to return to the start of the declaration. The declaration may be serialized again through the second parsing path in a second pass. The operation may be repeated until each of the parsing paths induced by the presence of branches of the preprocessor conditional directives in the source code is exhausted.

Abstract: Systems and methods for history based pipelined branch prediction. In one example, access to prediction information to predict a plurality of branches within an instruction block is initiated in a same clock cycle of the computer processor as a fetch of the instruction block. The prediction information may be available to the predictor not later than a clock cycle of the computer processor in which the plurality of branches are decoded.

Abstract: An apparatus for extracting instructions from a stream of undifferentiated instruction bytes in a microprocessor having an instruction set architecture in which the instructions are variable length. Decode logic decodes the instruction bytes of the stream to generate for each a corresponding opcode byte indictor and end byte indicator and receives a corresponding taken indicator for each of the instruction bytes. The taken indicator is true if a branch predictor predicted the instruction byte is the opcode byte of a taken branch instruction. The decode logic generates a corresponding bad prediction indicator for each of the instruction bytes. The bad prediction indicator is true if the corresponding taken indicator is true and the corresponding opcode byte indicator is false. The decode logic sets to true the bad prediction indicator for each remaining byte of an instruction whose opcode byte has a true bad prediction indicator.

Abstract: A method and system are described for generating reference tables in object code which specify the addresses of branches, routines called, and data references used by routines in the code. In a suitably equipped processing system, the reference tables can be passed to a memory management processor which can open the appropriate memory pages to expedite the retrieval of data referenced in the execution pipeline. The disclosed method and system create such reference tables at the beginning of each routine so that the table can be passed to the memory management processor in a suitably equipped processor. Resulting object code also allows processors lacking a suitable memory management processor to skip the reference table, preserving upward compatibility.