Abstract: An interrupt controller specifies and outputs the most highly prioritized one of a plurality of interrupt signal requested for output. A CPU executes a process corresponding to an interrupt signal from the interrupt controller and executes OS-provided programs. Based on reception of a request to execute a task level process, the CPU requests the interrupt controller to output an interrupt signal corresponding to the task level process.

Abstract: A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for handling the interrupt request, an interrupt service is performed by select processing units of the reconfigurable array in response to the interrupt request. Upon completion of the interrupt service, the register values are restored, and the reconfigurable array resumes execution of the operation.

Abstract: A multi-threaded processor is configured to detect excepted instructions from a first program, and to stop fetching younger instructions from that same program, to thereby conserve system resources that can be used by other programs. Each fetched program instruction has an associated status bit, which is set if the instruction excepts. Each excepting instruction is logged in an exception logging unit, which causes the associated status bit to be set. Each program has an associated in-flight vector table that tracks the instructions that have been fetched for that program. The status bits are compared with the in-flight vector table to identify the program that is associated with an excepted instruction. That program is then disabled, thereby preventing further fetching of instructions for that program until the excepted instruction clears.

Abstract: A multiprocessor system has a plurality of CPUs with respective local buses, and a memory which stores a plurality of programs to be executed by the CPUs and is connected to a common bus which can be accessed via the local buses, each local bus being connected to a CPU identification register which stores an identification value for identifying the corresponding CPU. When a program which is specific to a CPU is to be executed by that CPU, the corresponding identification value is read out from the identification register of the CPU and is judged, and branching to the appropriate program is performed based on the judgement result.

Abstract: In order to manage, in the interrupt stage, a memory stack associated with a microcontroller according to a Program Counter signal and to a Condition Code Register signal that can be contained in respective registers, a first part of memory stack is provided which comprises a register for the Program Counter signal, and a second part of memory stack consisting of a bank of memory elements equal in number to the number of bits of the Condition Code Register signal for the number of the interrupts of the microcontroller. The two parts of stack are made to function in parallel by respective stack-pointer signals.

Abstract: The processing of instructions from multiple threads using a shared dispatch pipeline is controlled by invoking a dispatch flush operation wherein instructions of a selected thread in the shared dispatch pipeline are flushed in response to resource requirements. An exception condition detected in one thread can be resolved by issuing a following instruction for that thread. Until the exception condition is resolved, resources are not released that allow the second thread to dispatch which in turn prevents dispatch from the first thread to resolve the exception condition. A flush of the first thread is not issued to resolve the stall. Instead, a dispatch flush of the second thread is issued. If a second thread instruction has long latency resource requirements that prevent the first thread from dispatching to resolve the exception, then a hold is issued controlling when the second thread instruction is refetched.

Abstract: The method and apparatus feature detecting an interrupt service request; storing into an instruction cache interrupt service instructions in response to detecting the interrupt service request; and fetching instructions from the instruction cache into an instruction stream sequence, the instruction stream sequence including mainline program instructions and the interrupt service instructions resulting in allocating core processor bandwidth between the interrupt servicing and mainline program instructions while executing the instruction stream sequence based on an interrupt priority; and processing instructions within the instruction stream sequence including the mainline program instructions and the inserted interrupt servicing instructions. The method and apparatus further feature recycling of executed micro-ops and detecting imminent context switch for interrupt service instruction preparation.

Abstract: In a data processing apparatus using a register window method performing data transmission from a master register to a work register during an exception handling, detecting a trap, discriminating whether or not a data transmission is required for the global registers by the trap, and transmitting data from the master register to the work register for only the global registers if the trap requires transmitting data for the global registers, thereby providing the data processing apparatus performing data transmission to the global registers if the occurring trap requires data for the global registers.

Abstract: A data processing system 2 having a nested interrupt controller 24 supports nested active interrupts. The priority levels associated with different interrupts are alterable (possibly programmable) whilst the system is running. In order to prevent problems associated with priority inversions within nested interrupts, the nested interrupt controller when considering whether a pending interrupt should pre-empt existing active interrupts, compares the priority of the pending interrupt with the highest priority of any of the currently active interrupts that are nested together.

Abstract: There is provided a microprocessor system that can execute a specific set of instructions at a high speed while limiting the increase in size of the circuitry. The microprocessor system, which executes instructions described in a program, comprises a main processor which executes a first set of instructions by means of hardware and executes a second set of instructions by means of software and a co-processor which operates under the control of the main processor to execute the second set of instructions by means of hardware. When the co-processor encounters a specific instructions of the second set for which data under the control of the main processor needs to be operated, the co-processor issues a notification of this fact to the main processor to request it to execute the specific instruction. In this case, the co-processor updates its stack pointer and program counter by itself by means of hardware.

Abstract: A method for creating precise exceptions including checkpointing an exception causing instruction. The checkpointing results in a current checkpointed state. The current checkpointed state is locked. It is determined if any of a plurality of registers require restoration to the current checkpointed state. One or more of the registers are restored to the current checkpointed state in response to the results of the determining indicating that the one or more registers require the restoring. The execution unit is restarted at the exception handler or the next sequential instruction dependent on whether traps are enabled for the exception.

Abstract: A load/store centric exception handling system provided in accordance with the principles of this invention that provides a more efficient processor exception handling system wherein a speculative commit control signal (SpecComId) is generated whenever a load or store instructions is detected by the pipeline issuing unit (PIU). This speculative commit signal is sent to a Load Store Unit (LSU) which combines the SpecComID with the completed instructions in its pipeline to generate an actual commit signal (ComId) that is coupled to other processor units. Depending on what type of instructions are in the pipeline, SpecComID can be generated as early as Q stage or as late as C stage. LSU or Exc Free instructions can be speculatively committed in Q stage to move the speculative commit point up in processor pipeline. Exc Taking instructions speculatively commit in the C stage to move the speculative commit point down pipeline.

Abstract: A computer implemented method to be implemented by a computer, which sequentially consecutively performs a plurality of predetermined process, when the computer receives an interrupt request to supply monitoring information which represents the processing state of the computer. The computer implemented method determines whether or not to execute an interrupt process, in which the monitoring information is supplied to the monitoring unit based on the information received when the computer receives the interrupt request. The interrupt program module further supplies the monitoring information which corresponds to the computer process which occurred immediately before deciding to execute an interrupt process. The interrupt program module also cancels an interrupt process after the monitoring information is sent to the monitoring unit.

Abstract: A locking mechanism for use in a multi-thread environment supporting self-modifying code in which modifications to the code are made at runtime. The locking mechanism having associated helper code accessed by a call from the first instruction address in the code block. The helper code calculating the binary encoding for the call instruction and using an atomic compare and exchange instruction to compare the calculated binary encoding with the actual contents of the first instruction address. Where there is a match, a self loop instruction is written to the first instruction address to lock the specified code block for subsequent threads. The helper code contains instructions to resolve the references in the specified block. The last such instruction is an atomic store operation to replace the self loop instruction at the first instruction address with the appropriate modified instruction.

Abstract: A group of bit set and bit clear instructions are provided for a microprocessor to allow atomic modification of privileged architecture control registers. The bit set and bit clear instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers. Two operands are provided for the instructions, the first designating which of the privileged control registers is to be modified, the second designating a general purpose register that contains a bit mask. The bit set instructions set bits in the designated control register according to bits set in the bit mask. The bit clear instructions clear bits in the designated control register according to bits set in the bit mask. By atomically modifying privileged control registers, a requirement for strict nesting of interrupt routines is eliminated.

Abstract: In one embodiment, a processor comprises an instruction cache and a fetch generator circuit coupled thereto. The fetch generator circuit is configured to generate at least one fetch request to the instruction cache for at least one of the plurality of threads. The fetch generator circuit is also configured to monitor for a plurality of conditions for each thread, wherein each of the plurality of conditions defined to inhibit the thread from being fetched. The fetch generator circuit is configured to speculatively generate a first fetch request for a first thread of the plurality of threads if each thread is inhibited from fetching and the first thread is inhibited from fetching only due to a first predetermined condition of the plurality of conditions. In one particular implementation, the first predetermined condition is a lack of room in a corresponding one of a plurality of instruction buffers.

Abstract: Mechanisms and techniques operate in a scalable or non-scalable processing architecture computerized device to execute critical code while overcoming interference from interruptions. A critical signal handler is registered and a non-operating system thread sets a value of a critical code register to indicate a critical execution condition. The non-operating system thread then executes a critical code section until an interruption occurs. In response to the interruption to the critical code section, an operating system thread detects if the critical code register is equivalent to a critical execution condition and if so, sets the value of the critical code register to indicate a critical execution failure. Upon returning to execution of the critical code section, the critical code section attempts to execute a contingent instruction in the critical code section that is contingent upon the value of the critical code register.

Abstract: One embodiment of an event management system, operating on a computer system having event producers and event consumers, includes an initial event handler program and an event queue having a first event. The initial event handler program retrieves the first event from the event queue for event processing. This event processing returns a first response to the initial event handler program, wherein the initial event handler program manages the first event on the event queue based on the first response.

Abstract: An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.

Abstract: Unhandled operation of a program instruction of a first instruction set, such as a Java bytecode, is detected. Instead of invoking a mechanism for directly dealing with that unhandled operation, one or more instructions from a second instruction set, such as ARM instructions, are instead used to emulate the instruction that was subject to the unhandled operation. If these instructions of the second instruction set are also subject to unhandled operation, then the mechanisms for dealing with unhandled operation within that second instruction set may be invoked to repair that operation. This approach is well suited to dealing with unhandled operation of variable length instructions being interpreted with a processor core having a native fixed length instruction set. In particular, prefetch aborts and unhandled floating point operations may be conveniently dealt with in this way.

Abstract: The invention relates to an automatic register backup/restore system. The system comprises: a general register file, a backup register file, at least one backup mode signal and at least one selector for selecting the general register file. The general register file comprises a plurality of general registers, and the backup register file comprises a plurality of backup registers. According to the system of the invention, upon exception, a backup mode is determined according to the cause of the exception. Then, according to the determined backup mode, the contents of at least one general register are automatically copied into at least one backup register. Upon leaving the exception process, according to the determined backup mode, the contents of the corresponding general registers are restored from the corresponding backup registers by using at least one selector. Therefore, the system of the invention can reduce the data moving activities between memory and registers during exception process.

Abstract: An interrupt controlling method is provided that is capable of executing an interrupt process while avoiding slowing-down in execution speed of a task process. When an interrupt request occurs while a task processing program is being executed, the task processing program is suspended and execution of an interrupt handler is started. By the interrupt handler, a plurality of breakpoints are set in an interrupt process-enabled area (R2). Execution of the resumed task processing program soon reaches one of the plurality of breakpoints. Then, the microprocessor (1) suspends the execution of the task processing program and starts execution of a breakpoint handler. By the breakpoint handler, the interrupt process is executed, and thereafter, the settings of the breakpoints are cleared.

Abstract: A system and method for pacing writes to a legacy peripheral device includes a control block configured to trap on the address of the legacy peripheral device and slows the rate that the CPU posts writes to avoid backpressure.

Abstract: A system may include an instruction cache, a trace cache including a plurality of trace cache entries, and a trace generator coupled to the instruction cache and the trace cache. The trace generator may be configured to receive a group of instructions output by the instruction cache for storage in one of the plurality of trace cache entries. The trace generator may be configured to detect an exceptional instruction within the group of instructions and to prevent the exceptional instruction from being stored in a same one of the plurality of trace cache entries as any non-exceptional instruction.

Abstract: The present invention relates to a method and system for efficiently identifying errant processes in a computer system using an operating system (OS) error recovery method that identifies if the error caused by the errant process can be recovered and, if so, can recover from the error. The method and system of the present invention operates after standard Error Correcting Code (ECC) and parity check bit methods and systems are unsuccessful in recovering from the error. In accordance with an embodiment of the present invention, the method and system includes detecting an error during instruction execution, storing a physical address of an errant process that caused the error, and storing an execution instruction pointer (IP) in a processor including at least one critical memory structure to detect an error and a processor error processing logic hardware coupled to the at least one critical memory structure.

Abstract: A method of controlling a secure execution mode-capable processor includes allowing a plurality of interrupts to interrupt the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a non-secure execution mode. The method also includes disabling the plurality of interrupts from interrupting the secure execution mode-capable processor when the secure execution mode-capable processor is operating in a secure execution mode.

Abstract: A programmable unit includes a command execution unit for carrying out commands, a memory device for storing data required for command execution and data emitted from the command execution unit, and a buffer-storage device for buffer storing the data emitted from the command execution unit. The command execution unit writes to the buffer-storage device data to be transferred to the memory device. The data written to the buffer storage device is transferred to the memory device at a later time. The programmable unit is distinguished by forming the buffer-storage device as a stack, and/or by providing a control apparatus that, when required, causes data stored in the buffer-storage device to be moved temporarily to another memory device. Such a programmable unit can carry out any buffer storage of events that may possibly be required quickly and easily in all circumstances.

Abstract: A method and apparatus for implementing vertical multi-threading in a microprocessor without implementing additional signal wires in the processor has been developed. The method uses a pre-existing signal to serve as a multi-function signal such that the multi-function signal can be used for clock enable, clock disable, and scan enable functions. The single multi-function signal exhibits multiple functionalities as needed by a flip-flop to operate in a plurality of modes. The method allows for the use of a pre-existing signal wire to be used as a process thread switch signal that would otherwise have to be explicitly hard-wired in the absence of the multi-functioning signal. The method further includes allowing multiple-bit flip-flops to be placed at sequential stages in a pipeline in order to facilitate vertical multi-threading and, in effect, increase processor performance. The apparatus provides means for distinguishing between specific characteristics exhibited by the multi-function signal.

Abstract: A data processing system having multiple register contexts is described. One embodiment of the present invention uses a user programmable context control register for each of the multiple register contexts to allow for the mapping of portions of an alternate register context into a current register context. The context control register may also be used to provide for the sharing of common stack pointers among multiple register contexts. Therefore, when operating in a current register context, the context control register may be used to access portions of an alternate register context in place of accessing corresponding portions of the current register context.

Abstract: Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, demand evaluation of values, parallel access of multiple threads to a list, synchronized and unsynchronized access to a data buffer, use of forwarding to avoid checking for an end of a buffer, use of sentinel word to detect access past a data structure, concurrent access to a word of memory using different synchronization access modes, and use of trapping to detect access to restricted memory.

Abstract: A method, apparatus, and computer instructions in a data processing system for processing instructions are provided. Instructions are received at a processor in the data processing system. If a selected indicator is associated with the instruction, counting of each event associated with the execution of the instruction is enabled. In some embodiments, when it is determined that a cache line is being falsely shared using the performance indicators and counters, an interrupt may be generated and sent to a performance monitoring application. An interrupt handler of the performance monitoring application will recognize this interrupt as indicating false sharing of a cache line. Rather than reloading the cache line in a normal fashion, the data or instructions being accessed may be written to a separate area of cache or memory area dedicated to false cache line sharing data. The code may then be modified by inserting a pointer to this new area of cache or memory.

Abstract: To obtain a correct vector address even if an interrupt occurs during erasing or programming of the data in a built-in ROM 18 by moving a part of a built-in RAM 13 to a vector address area by a bus controller 27. Thereby, a microcomputer is prevented from running away and the safety of a system is improved at the time of on-board programming of the built-in ROM 18.

Abstract: When processor instructions are required for execution, a misaligned address is sent to the processor. The misaligned instruction address causes a computer processor exception. The computer system automatically executes an exception handling routine that transforms data into at least one executable instruction for the processor. In embodiments, data is transformed by decompressing a compressed instruction, decrypting an encrypted instruction, decoding a macro instruction, or transforming a non-native instruction into at least one instruction.

Abstract: An apparatus and method for performing single-instruction multiple-data instructions using a single multiply-accumulate unit while minimizing operational latency. The multiply-accumulate unit generates a first half and a second half of a data result. A register stores the first half of the data result. A miscellaneous-logic unit determines when to release the first half of the data result from the register to synchronize the first half and the second half of the data result.

Abstract: A method and system for recovering a global history vector. In the event of a non-branch flush, a tag may be received by a queue configured to store information about branch instructions. The queue may read a copy of the global history vector from an entry indexed by the tag. This copy may be inserted in a global history vector mechanism (“GHV mechanism”) configured to manage the global history vector. If the flush operation is a flush to a group of instructions that contains no branch instructions and the tag does not equal the next-to-write pointer in the queue, then the queue may transmit a command to the GHV mechanism to enter a mode where the GHV mechanism does not update the global history vector until the next branch instruction is fetched.

Abstract: A processor includes a memory execution unit for executing load and store instructions and a replay system for replaying instructions which have not executed properly. The memory execution unit including an invalid store flag that is set for a store instruction if the replay system detects that the store instruction has not executed properly and is cleared if the store instruction has executed properly. If an invalid store flag is set for a store instruction, the replay system replays load instructions which are programmatically younger than the invalid store instruction until the store instruction executes properly.

Abstract: A processor avoids or eliminates repetitive replay conditions and frequent instruction resteering through various techniques including resteering the fetch after the branch instruction retires, and delaying branch resolution. A processor resolves conditional branches and avoids repetitive resteering by delaying branch resolution. The processor has an instruction pipeline with inserted delay in branch condition and replay control pathways. For example, an instruction sequence that includes a load instruction followed by a subtract instruction then a conditional branch, delays branch resolution to allow time for analysis to determine whether the condition branch has resolved correctly. Eliminating incorrect branch resolutions prevents flushing of correctly predicted branches.

Abstract: Unaligned accesses to memory are circumvented by an address exception handler mechanism, which decodes an exception-triggering instruction, and reads from or writes to, in a byte-by-byte manner, addressed portions of memory which are unaligned with an addressing scheme through which accesses to memory may be performed, and thereby give rise to unaligned memory access exceptions. The handler simulates the execution of the instruction with reference to an exception stack frame, to which the contents of all registers at the time of the unaligned address exception are saved. This allows the handler to controllably define values that are restored into registers during the processor's execution of a general exception vector. After handling the exception, program execution transitions to the next instruction that directly follows the exception-causing instruction.

Abstract: When a decoding circuit (22a) decodes an instruction code stored in a pipeline register (21d), the decoding circuit (22a) decodes the device address. Based on this, it is decided which one of the device information of a RAM (11) and a RAM (12) is to be used. When the area of the RAM (12) has been assigned, the decoding circuit (22a) outputs a signal showing that the number of stop of pipeline processing is 0, unlike the assignment of the RAM (11). Therefore, a pipeline register section (21) does not set the pipeline stop signal to 1. Consequently, the reading of the instruction code from the RAM (11) and the pipeline processing are not interrupted. As a result, it is possible to realize a structure in which execution of a high-speed processing is possible and a compact/low-cost structure in the same hardware.

Abstract: System for providing transitions between operating modes of a device. The system includes a method for providing transitions between a privileged and a non-privileged operating mode. The method comprises executing an application in the non-privileged mode, generating an interrupt to request the services of a privileged function, and transitioning to the privileged mode to execute the privileged function, wherein the privileged function is executed as part of the same thread of execution as the application.

Abstract: A method and system for intelligent trap analysis for debugging software on a computer system. Instead of dumping only a register context snapshot or all of memory to a file, a trap handler determines a likely cause of a trapped instruction and selects relevant memory addresses for copying to a file. The relevant memory addresses and their contents are preserved for later analysis. The trap handler may step back through the process instruction list searching for relevant memory addresses referenced by the instructions preceding the trapped instruction. The module may undo the effect of instructions as it steps back through the instruction list.

Abstract: A processor having a cache memory structure which improves an operation speed of the processor and a method of managing cache memory of the processor are provided. The cache memory is divided into a cache memory for normal programs which stores instructions required for running normal programs and a cache memory for exception programs. An instruction register fetches and stores instructions from one of the cache memories according to the type of program currently running. The method includes dividing the cache memory into a cache memory for normal programs and a cache memory for exception programs, storing instructions and/or data for running the normal and exception programs in their respective cache memories, determining a type of a currently running program, fetching instructions from either cache memory according to the type of program currently running, and inputting the fetched instructions to the instruction register.

Abstract: Unified exception handling may be provided by processing a data packet through at least two pipelined processing stages in a data packet processor such as a switch, router, bridge, or similar network device, each of the data packets having associated with it (while it is being processed) an exception map disposed in a memory of the network device. The bits in the exception map are set, modified, or reset in response to exception conditions detected at the various processing stages. After the packet has been fully processed, an exception handler takes as an input the exception map and further processes the packet in response to the state of the exception map.

Abstract: It is one object of the present invention to provide effective optimization for a program that includes commands that may cause exception processes. A novel compiler for converting source code for a program written in a programming language into object code in a machine language comprises: an optimization execution unit for performing an optimization process for an object program written in a machine language; and a pre-processor and a post-processor for modifying the object program in order to absorb a difference in content between the point of origin of an exception process, which occurs in response to the execution of a command in the object program, and a location whereat the exception process is performed.

Abstract: Fusing micro-operations (uops) together. Intra-instruction fusing can increase cache memory storage efficiency and computer instruction processing bandwidth within a microprocessor without incurring significant computer system cost. Uops are fused, stored in cache memory, un-fused, executed in parallel, and retired in order to optimize cost and performance.

Abstract: A method and system for nearly immediately trapping a failure-to-check-a-return-value error in a computer program. Modern processor architectures, such as the Intel® IA-64 processor architecture, provide for control speculation of load instructions, including 1-bit NAT registers, associated with general registers, that indicate occurrences of deferred exceptions arising during execution of control-speculative load instructions targeting the corresponding general registers. One embodiment of the present invention employs the NAT registers associated with general-purpose registers to distinguish special values, often indicating error conditions, stored in general-purpose registers serving to store the return values of functions and routines.

Abstract: A data processing apparatus 2 supports multiple memory access program instructions LDM, STM which serve to load data values from multiple program registers 16 to respective memory locations or to store data values from multiple memory locations to respective program registers. A memory management unit 8 within the system stores device or strongly ordered memory attribute values which control whether or not a multiple memory access instruction involving such a memory location may be early terminated when an interrupt is received during its operation. Early termination is permitted in those circumstances where the multiple memory access instruction may be safely restarted and rerun in its entirety, whereas early termination is not permitted and the operation completes before the interrupt is taken in those circumstances where the memory locations are subject to a guaranteed number of memory accesses as this appears within the controlling program instructions.

Abstract: A method is provided that allows a general set of watchpoints to be defined for a computer system (a watchpoint is a memory address that triggers an interrupt for debugging or tracing purposes). This is accomplished by modifying the system page table for the memory page containing a watchpoint, such that a page fault interrupt is triggered whenever said memory page is accessed (for example by marking the page as not present). The paging mechanism of the computer system is then adapted, so that responsive to a page fault interrupt, a determination is made as to whether such interrupt has resulted from an access to the watchpoint, and if so, control is passed to a watchpoint handler. Alternatively, if there is no watchpoint, normal paging operations can be resumed if necessary.

Abstract: Systems, methods, and software for reducing system management interrupt (SMI) latency while operating in system management mode. The present invention implements a technique for exiting system management mode while waiting for polled hardware events, handling any pending lower-priority interrupts and then resuming polling. The present invention does this by multi-threading SMI source handlers, using an idle thread, and using protocols for software-generated system management interrupts that insure that lower priority interrupts are serviced.

Abstract: Systems and methods for implementing an execution stack which stores frames for functions written in multiple programming languages are provided. The frames for functions written in different programming languages may be interleaved on the same execution stack. A data block on the execution stack may be utilized to traverse the execution stack around a frame by storing a stack pointer and frame pointer to a previous frame. Additionally, exceptions may be propagated, with conversion if necessary, through frames on the execution stack that are written in different programming languages.