Abstract: A plan executing apparatus includes: an executing unit that executes a plan which is a sequence of processes; a processing state retaining unit that retains a processing state of a target object of the plan; an execution information retaining unit that retains execution information which is information relating to execution of a plan in execution; an interrupt instruction accepting unit that accepts an interrupt instruction during execution of the plan; an interrupt information identifying unit that identifies interrupt information relating to execution of an interrupting plan, on accepting the interrupt instruction for the interrupting plan; and an interrupt possibility determining unit that determines whether the interrupting plan is to be executed or not based on the processing state, the execution information of the plan in execution, and the interrupt information.

Abstract: Exception handling is simulated. An exception simulator is employed to simulate exceptions generated from routines simulating operations. The exception simulator provides an indication of the exception and invokes an interruption, when appropriate. The exception simulator includes an instruction invoked to handle the exception and any interruption.

Abstract: Embodiments of the present invention may provide for architectural and compiler approaches to optimizing processors by packing instructions into instruction register files. The approaches may include providing at least one instruction register file, identifying a plurality of frequently-used instructions, and storing at least a portion of the identified frequently-used instructions in the instruction register file. The approaches may further include specifying a first identifier for identifying each of instructions stored within the instruction register file, and retrieving at least one packed instruction from an instruction cache, wherein each packed instruction includes at least one first identifier. The packed instructions may be tightly packed or loosely packed in accordance with embodiments of the present invention. Packed instructions may also be executed alongside traditional non-packed instructions.

Abstract: The present invention relates to a device for an interrupt verification support mechanism and the method for operating said device comprising a processor and an input for external interrupt requests or interrupt pseudo-instructions communicatively coupled to the processor. The method comprises the steps of processing at least one actual instruction in the processor in an instruction pipeline, and if an external interrupt request is received by the processor, the actual instruction is replaced with the pseudo-instruction. Pursuant to the method, instructions are concurrently processed in the processor in an instruction pipeline with several stages. In the instruction pipeline, instructions are processed by an instruction fetch stage, an instruction decode stage, an instruction issue stage, an execute stage and a result write-back stage. Thereby, interrupt requests are only processed at the fetch stage of the instruction pipeline.

Abstract: A method of handling an exception in a parallel system includes constructing a task object, executing a method with the task object, and catching an exception with the task object during execution of the method. The exception is propagated in response to the task object becoming inaccessible without the exception having been observed.

Abstract: Software defects (e.g., array access out of bounds, stack overflow, infinite loops, and data corruption) occur due to integer values falling outside their expected range. Because programming languages do not include range-checking instructions as part of their language, to detect software defects and ensure that the code runs smoothly, programmers generally use 1) runtime assertions and/or 2) sub-range data types. However, these techniques cause additional conditional branches, incur additional overhead, and decrease processor performance. Processors comprising a range checking hardware feature supported by machine instructions for runtime integer range checking can eliminate the conditional branches generated during runtime integer range checks. Programming language extensions for the range checking hardware can allow dynamic range bounds to be defined during runtime without decreasing the processor's performance. This can allow for easier programming and code that is easier to maintain.

Abstract: This invention relates to multi-core, multi-processing, factory multi-core and DSP multi-core. The nature of the invention is related to more optimal uses of a multi-core system to maximize utilization of the processor cores and minimize power use. The novel and inventive steps are focused on use of interrupts and prioritized interrupts, along with optional in-built methods, to allow systems to run more efficiently and with less effort on the part of the programmer.

Abstract: Architecture for efficient translation and processing of PowerPC guest instructions on an x86 host machine. In an x86-based architecture, signed integer values are projected into the unsigned integer value space for processing by the host using the negation of the left-most (sign) bit. Compare operations are performed in the unsigned space and the compare results are written into the host flags register. Once the compare results are written into the host flags register, the flag values can be read out and used in a table lookup to retrieve the corresponding values for the guest register. The guest flag values are then passed into the guest flags register for processing by the guest application.

Abstract: A stack pointer is copied to a stack pointer base to debug stack underflow. A move instruction, used to initialize the stack pointer, is modified to additionally copy the stack pointer to a stack pointer base register. During a course of execution in a single context, the stack pointer base sticks to the initial base value while the stack pointer is altered by a succession of PUSH and POP instructions. By monitoring for equivalence in the stack pointer and the stack pointer base values, a balanced number of PUSH and POP instructions is detected. If an equal number of PUSH and POP instructions is detected and an additional POP instruction is programmed, a stack underflow condition exists, an exception condition signaled, and exception flag produced. The exception condition allows the stack to be protected from an excessive POP instruction retrieving data out of context and subsequent loss of stack data.

Abstract: In one embodiment, the present invention includes a method for controlling redundant execution such that if an exceptional event occurs, the redundant execution is stopped, non-redundant execution is performed in one of the threads until the exceptional event has been-resolved, after which a state of the threads is synchronized, and redundant execution is continued. Other embodiments are described and claimed.

Abstract: An information handling system includes a processor that may perform general purpose register recovery operations after an instruction flush operation that an exception, such as a branch misprediction causes. The processor receives an instruction stream that may include multiple instructions that operate on a particular target register that stores instruction result information. The general purpose register may temporarily store instruction opcode and register bits information for use during dispatch, execution and other operations. The processor includes a recovery buffer unit for use during flush recovery operations. The processor may use recovery valid and recovery pending bits that correspond with each instruction during the register recovery from flush operation.

Abstract: Systems, methodologies, media, and other embodiments associated with acquiring instruction addresses associated with performance monitoring events are described. One exemplary system embodiment includes logic for recording instruction and state data associated with events countable by performance monitoring logic associated with a pipelined processor. The exemplary system embodiment may also include logic for traversing the instruction and state data on a cycle count basis. The exemplary system may also include logic for traversing the instruction and state data on a retirement count basis.

Abstract: A multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs), each having a program counter and a general purpose register set for executing a thread. The OS includes a data structure having an entry for each of the plurality of TCs, each entry containing information describing capabilities of the corresponding one of the plurality of TCs. Each entry further comprises a TC identifier field for identifying a corresponding one of the plurality of TCs. The OS populates the TC identifier field for each of the entries with a unique identifier value.

Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors.

Abstract: An event-driven system enables handlers to be specified for success and failure, among other things. In other words, events can be explicitly encoded with an option of returning either a success or a failure result. In this manner, asynchronous programming and events can be unified. Multiple event streams can be employed to represent success and/or exceptional values. Alternatively, a disjoint union of regular and exceptional values can be employed with respect to a single event stream.

Abstract: a multiprocessing system, including a multithreading microprocessor and a multiprocessor operating system (OS), is disclosed. The microprocessor includes a plurality of thread contexts (TCs) configured as an array, each having a program counter, a general purpose register set for executing a thread, and a register for storing an index of the respective TC within the array. The OS maintains a table of entries, each the entry for storing a CPU-unique value for a respective one of the TCs. The OS comprises a respective thread configured to execute on each of the respective TCs and to read the index from the register of the respective one of the TCs and to read the respective CPU-unique value for the respective one of the TCs using the index.

Abstract: Method, apparatus and system embodiments provide a register to track the oldest exception event or sticky event in a processor. The processor may be an out-of-order processor. Dispatched instructions (or micro-ops) may be maintained in a queue, such as a reorder buffer (ROB), for in-order retirement. For at least one embodiment, event information is maintained only in the register and is not maintained in a ROB. For at least one other embodiment, event information is maintained in a ROB entry for some events and in the register for others. For such latter embodiment, a retire engine takes the contents of both the ROB entry and the register into account when determining whether to take an exception or otherwise initiate a handling sequence during in-order instruction retirement. Other embodiments are also described and claimed.

Abstract: A method and apparatus for handling exceptions during execution of a transaction is herein described. A compiler associates a transaction exception handler (TEH) with a transaction in program code, such as through insertion of a call to the TEH. The TEH is also associated with an exception data structure, such as an unwind table, that is utilized during runtime to call an appropriate handler in response to an exception. Additionally, the TEH code is generated by the compiler and inserted into the program code. Upon encountering an exception during execution of the transaction, the TEH is capable of dynamically resizing the transaction to the point of the exception through an attempted commit.

Abstract: A method, computer-readable medium, and apparatus for context switching between a first thread and a second thread. The method includes detecting an exception, wherein the exception is generated in response to receiving a packet of information directed to one of the first thread and the second thread, and in response to detecting the exception, invoking an exception handler. The exception handler is configured to execute one or more instructions removing access to at least a portion of a processor cache. The portion of the processor cache contains cached information for the first thread using a first address translation. Removing access to the portion of the processor cache prevents the second thread using a second address translation from accessing the cached information in the processor cache. The exception handler is also configured to branch to at least one of the first thread and the second thread.

Abstract: A trap-based mechanism is provided for gaining greater visibility into the memory usage of a process. To detect and record the memory accesses of a process, a virtual address range (or a plurality of address ranges) of the process is set to a protected status. This address range represents the range of virtual addresses that are to be monitored for access. By setting the address range to a protected status, whenever a memory access (in one implementation, whenever a memory write) is made to a virtual address within that address range, a trap arises. When the trap arises, a trap handler is invoked. When invoked, the trap handler records the virtual address that was accessed. In this manner, the access of the virtual address is detected and recorded without having to add extensive instrumentation code to the process.

Abstract: A network device to selectively filter the exception data units based on the type of the exception data units. The network device generates a first threshold value for a first type of exception data units and a second threshold value for a second type of exception data units. The first threshold value and the second threshold value are determined based on the weight factors associated with each the first type and the second type of exception data units and a scratch pad threshold value. The network data unit determines the type of exception data units and a scratch pad fullness value and filters the first type and the second type of exception data units based on the first and the second threshold values.

Abstract: A system for tagged interrupt forwarding comprises a multiprocessor including a first and a second processor, an I/O device, and I/O management software. In response to an application I/O request, the I/O management software may be configured to prepare a request descriptor at the first processor, including an identification of the first processor. The I/O management software may then send a hardware or device-level I/O request to the I/O device. When the I/O device completes the requested hardware I/O operation, it may send a response, which may be received at the second processor. I/O management software at the second processor may be configured to transfer control for processing the response back to the first processor at which the I/O request was initiated, using the tag to identify the first processor. Processing of the response may then be completed at the first processor.

Abstract: Techniques for the design and use of a digital signal processor, including (but not limited to) processing transmissions in a communications (e.g., CDMA) system. The disclosed method and system process interrupts arising in a multithreaded processor by receiving in an interrupt register a plurality of interrupts of a statistically indeterminate interrupt type and then associating a plurality of processing threads with the interrupt register for receiving the interrupt from the interrupt register. The method and system mask at least a subset of the plurality of processing threads so as to receive within each of the threads within the subset only ones of the plurality of interrupts of one or more predetermined types, thereby controlling on a per thread basis the processing of the plurality of interrupts according to the mask associated with a particular thread.

Abstract: A multiplexed hierarchical array of interrupt controllers is configured to enable low latency task switching of a processor. The hierarchical array comprises a plurality of interrupt controllers coupled to a root interrupt controller. For each task that the processor is configured to execute, a corresponding interrupt controller is provided. To switch the processor to a task, the corresponding interrupt controller signals the root interrupt controller which, in turn, sends an interrupt and a Task Identifier to the processor. The root interrupt controller also cooperates with an access multiplexer/demultiplexer to select the corresponding interrupt controller for communication with the processor. By providing interrupt controller selection as well as task identification, the hierarchical array offloads arbitration and context switching overhead from the processor. That is, in response to the interrupt, the processor switches to the identified task and may access a memory address space dedicated to the task.

Abstract: A method that allows the context of an SMI task to be saved between SMIs. Upon entering an SMI handler for a task that needs to be split up into shorter SMIs, a new task context stack is created in memory. From that point forward, the SMI handler uses the task context, leaving the original stack unchanged. When the time limit for a single SMI is about to be reached, the CPU is directed back to the original stack, and the task context stack persists in memory and retains the context of the task in hand. The soft SMI exits with a return code or other indication to signify that a new SMI should be invoked to continue processing. The driver or other software that caused the first soft SMI then invokes another, passing in a code or other indication to signify that this is a continuation of a previously started task. On entering the SMI handler for the second time, the handler notes the request for continuation, switches back to the saved task context stack and continues processing where it left off.

Abstract: A data processing apparatus processes a stream of instructions from an instruction set. The instruction set includes exception instructions and non-exception instructions. Exception instructions may cause a break in an instruction flow, and non-exception instructions execute in a statically determinable way. At least two processing blocks process instructions from the stream of instructions. A first processing block has a set of physical registers associated with it for storing data values being processed by the first processing block. Renaming circuitry associated with the first processing block maps architectural registers specified in instructions to be processed by the first processing block to physical registers within the set of physical registers. A second processing block has a set of physical registers associated with it for storing data values being processed by the second processing block. The second processing block and registers do not support renaming.

Abstract: Methods and arrangements to handle non-queued commands for data storage devices, such as Parallel and Serial ATA hard drives, are disclosed. Embodiments may comprise a host and/or a data storage device. The host and data storage device may form, e.g., a handheld device such as an MP3 player, a cellular phone, or the like. The storage device may comprise a new method of responding to a non-queued command while the storage device may be processing a queue of commands. In many embodiments, the method involves processing queued commands until the drive receives a non-queued command that requires immediate processing by the drive. In many of these embodiments, the drive will respond in a new manner to process the non-queued command, the end result having no or minimal impact on host system operation.

Abstract: A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables.

Abstract: An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in the determination. The determination does not include performing a memory access that uses the first address value to determine a memory location of the memory access. The determination is based at least in part on more than one of the following: a group of one or more marker bits included in the first address value, a matrix entry located at least in part using one or more bits of the first address value, a Translation Look-aside Buffer entry associated with the first address value, whether the first address value is associated with stack allocated memory, and whether the first address value includes a null value.

Abstract: Disclosed is a method, system, and computer readable medium for completing critical write functions to a non-volatile memory (NVM) system within an electronic device upon experiencing a sudden or unexpected loss of the main power to the electronic device. A sudden loss of main external power is detected and determined if the loss of power crosses a minimum threshold level. If it does, an interrupt is generated to prevent new write requests. One embodiment uses a software interrupt and another embodiment uses a hardware interrupt. A switch over to a short term reserve internal power source occurs and the NVM write function in progress at the time of the power loss is completed. Upon completion of the NVM write operation, less critical shutdown activities can commence.

Abstract: A system, apparatus and method for efficiently processing interrupts using general purpose registers in a pipelined processor. In accordance with the present disclosure, a register file may be updated to efficiently save an interrupt return address. When an interrupt request is received by the system's processor, or when the request is issued in the execution of a program, a pseudo-instruction is generated. This pseudo-instruction travels down the pipeline in the same way as other instructions and updates the register file by causing the register file to be written with the return address of the last instruction for which processing has not been completed.

Abstract: A multiprocessing system including a multithreading microprocessor and multiprocessor operating system (OS) is disclosed. The microprocessor includes a first and a second plurality of thread contexts (TCs), each TC having a program counter and a general purpose register set for executing a thread. The microprocessor also includes a first and a second shared privileged resource, shared by the first and second respective plurality of TCs rather than being replicated for each of the respective first and second plurality of TCs, and privileged to be managed only by operating system-privileged threads rather than by user-privileged threads. The OS manages the first and second shared privileged resource and schedules execution of both the operating system-privileged threads and the user-privileged threads on the plurality of TCs.

Abstract: In various embodiments of the present invention, a virtual monitor can arrange to properly emulate execution of a cover instruction by operating-system code, or other code assuming to run at highest privilege level, by monitoring a window of instruction execution in which a cover instruction may be executed. Upon occurrence of an interruption, the virtual monitor may configure performance monitoring by the IA-64 processor to count the number of times a cover instruction is executed.

Abstract: An apparatus for processing data includes a processor operable in a plurality modes including at least one secure mode being a mode in a secure domain and at least one non-secure mode being a mode in a non-secure domain. When the processor is executing a program in a secure mode the program has access to secure data which is not accessible when the processor is operating in a non-secure mode. The processor is responsive to one or more exception conditions for triggering exception processing using an exception handler. The processor is operable to select the exception handler from among a plurality of possible exception handlers in dependence upon whether the processor is operating in the secure domain or the non-secure domain.

Abstract: An apparatus and method for communicating information within a network having one or more communication buses (5, 6, 7, 8), consisting of one or more elements (20, 30, 40) to maximise throughput and minimise CPU involvement by executing the following. Compare incoming message identifiers (14) against a set of predetermined identifiers (22). Transpose data sets (12) within the incoming message data frame and where necessary, save and/or transmit new frames as defined by operations dependent upon the incoming identifier. By utilising an optimal set of operands the memory requirement is satisfied by a minimal size of standard type.

Abstract: A method and a program network for exception handling are described. At least one error program element including an input and an output and an item of exception information stored for exception handling in the form of a data structure are defined in a graphical programming language.

Abstract: Apparatus and a method for handling nested faults including the steps of determining whether a fault is a first level fault, responding to a determination of a first level fault by saving a first amount of state sufficient to handle a first level fault, and responding to a determination of a nested fault by saving an additional amount of state before handling the fault.

Abstract: An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register.

Abstract: In one embodiment, the present invention includes a method of determining a relative priority between a first agent and a second agent, and assigning the first agent to a first channel and the second agent to a second channel according to the relative priority. Depending on the currently programmed status of the channels, information stored in at least one of the channels may be dynamically migrated to another channel based on the assignments. Other embodiments are described and claimed.

Abstract: An event notifying method notifies one or a plurality of events from a device to a processor by queuing to a queue in a processor system having one or a plurality of processors. A number of non-notified events existing in the queue is managed by a counter unit, and an inconsistent state of the counter unit caused by differences in updating timings of the counter unit from the device and the processor is temporarily permitted.

Abstract: One embodiment disclosed relates to a method of compiling a program to be executed on a target central processing unit (CPU). The method includes opportunistically scheduling diagnostic testing of CPU registers. The method may include use of a predetermined level of aggressiveness for the scheduling of the register diagnostic testing. The scheduled diagnostic testing may include writing known data to a register, reading data from the register, and comparing the known data with the data that was read. If the comparison indicates a difference, then a jump may occur to a fault handler routine.

Abstract: An integrated circuit processor core 4 is provided with an instruction pipeline 20 along which program instructions advance. When an exception condition occurs part way through execution of a particular program instruction, then a prefetch of the exception handling program instruction corresponding to that exception is initiated before the currently executing program instruction has completed. In this way the exception handling program instruction is more rapidly available to start the exception processing. The early prefetch may involve performing a lookup in a cache memory 6 and any necessary linefill upon a miss. In addition, the exception handling program instruction amy also be fed into the instruction pipeline 20 before an instruction boundary is reached.

Abstract: A system and method is provided to simulate hardware interrupts by inserting instructions into a stream of instructions where a “no operation” (or NOOP) instruction would normally be inserted. The instruction is inserted is a conditional branch instruction, called a BISLED, that branches if there is external data in a known memory area. In one embodiment, the processor has at least two pipelines that need to be aligned so that certain instructions are scheduled for the first pipeline and other instructions are scheduled for the other. In this embodiment, the BISLED also serves the purpose of re-aligning the instruction stream so that instructions are placed in the correct pipeline based upon the function performed by the instruction.

Abstract: A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

Abstract: A data processing system 2 supporting interrupt handling is provided with an interrupt controller 24. The interrupt controller is responsive to save state data when interrupt processing is commenced by pre-emption of existing processing, whether that be background processing or another interrupt. If a further interrupt is required to be executed immediately after the interrupt which triggered the pre-emption, then the speed with which interrupt processing can be started is advantageously increased if that subsequent interrupt processing is performed without restoring and then resaving the original state data. The interrupts in this arrangement can be considered to be chained together without intervening save and restore operations.

Abstract: Embodiments include a controller apparatus, a computerized apparatus, a device, an apparatus, and a method. A controller-apparatus includes a monitoring circuit for detecting a computational error corresponding to an execution of an instruction of a sequence of instructions by a processor subsystem having an adjustable operating parameter. The controller apparatus also includes a recovery circuit for rolling back an execution of the sequence of instructions to a checkpoint in response to the detected computational error. The controller apparatus further includes a control circuit for adjusting the adjustable operating parameter in response to a performance criterion.

Abstract: A method may include distributing ranges of addresses in a memory among a first set of functions in a first pipeline. The first set of the functions in the first pipeline may operate on data using the ranges of addresses. Different ranges of addresses in the memory may be redistributed among a second set of functions in a second pipeline without waiting for the first set of functions to be flushed of data.

Abstract: An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates the instructions are to be executed in privileged (kernel) state only, and are to communicate with privileged control registers. The instructions designate which of a plurality of privileged architecture registers is to be modified, which bit fields within the designated privileged architecture register is to be modified, and whether the designated bit fields are to be set or cleared. An instruction atomically sets or clears bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.

Abstract: A condition management callback system and method for use with a processor employing a hierarchical register consolidation structure. In one embodiment, the system includes: (1) a condition management structure, (2) a callback abstraction subsystem configured to register a callback for at least one element object in the condition management structure and store logically abstracted data associated with the callback and (3) an abstraction retrieval subsystem configured to employ the condition management structure to determine a condition of at least one status indicator in the condition management structure by traversing the hierarchical register consolidation structure, initiate the callback based on the condition and pass the logically abstracted data if the element object representing the status indicator has the callback registered.

Abstract: An execution unit supports data dependent conditional write instructions that write data to a target only when a particular condition is met. In one implementation, a data dependent conditional write instruction identifies a condition as well as data to be tested against that condition. The data is tested against that condition, and the result of the test is used to selectively enable or disable a write to a target associated with the data dependent conditional write instruction. Then, a write is attempted while the write to the target is enabled or disabled such that the write will update the contents of the target only when the write is selectively enabled as a result of the test. By doing so, dependencies are typically avoided, as is use of an architected condition register that might otherwise introduce branch prediction mispredict penalties, enabling improved performance with z-buffer test and similar types of algorithms.