Abstract: A pipeline processing microprocessor includes a storage unit for storing instructions and a fetch unit for requesting and fetching an instruction from the instructions in the storage unit. Upon an interrupt condition, the fetch unit eliminates from a request queue a previously requested instruction that precedes the interrupt condition.

Abstract: A method for processing interrupt requests in a processor is suitable for executing at least two threads in parallel, wherein an instruction pipeline is provided for each of the at least two threads. One of the at least two threads is defined as a main thread for processing programs. Another thread of the at least two threads is assigned to the main thread as an interrupt thread. After an interrupt request is received, the processor stores interrupt data in a register assigned to the interrupt thread. Subsequently, the processing of an interrupt routine is started in the interrupt thread and at least part of the interrupt routine is executed in the interrupt thread.

Abstract: Embodiments of the invention provide a method for regaining memory consistency after a trap via transactional memory. Transactional memory and a transactional memory log are used to undo changes made to memory from a transaction start point up to the point of a trap event. After the trap event is processed, and the changes are rolled back, the program can resume execution at the beginning of the transaction.

Abstract: When a normal interrupt occurs, data of processor operation before the normal interrupt are held in a normal return address register (452), a normal previous state register (453), and a normal factor register (454). When a break-interrupt occurs, data of processor operation before the break-interrupt is held in another break return address register (455). Hence, a break-interrupt can occur even within an interrupt inhibition period by a normal interrupt. Besides, when a break-interrupt occurs, the break-interrupt state is set in a flag register (456). By referring to the flag register (456) in executing an interrupt return instruction, the operation data before the break-interrupt or before the normal interrupt can accurately be restored.

Abstract: In a programmed computer system, normal processing results generated by a called method are returned to one or more calling methods by an exception rather than by the more conventional single-type return value. The programmer is granted flexibility through the ability to use multiple normal return types while retaining strong data typing. Better programming practices are promoted through the use of a single exception-technique for handling normal results as well as abnormal (i.e. error) results. The disclosed technique can be used with existing programming languages/environments such as the Java® language, and can provide a basis for new languages/environments that are specifically tailored to this processing technique.

Abstract: Techniques for routing exceptions to operating system subsystems are provided. In various embodiments, a software developer may add a global exception handler software component to an application. The global exception handler may operate in a process relating to a subsystem. Upon receiving an exception, the global exception handler may route the exception to another subsystem.

Abstract: Management of a process having a kernel mode and a user mode and executed on an operation system is performed by receiving a request for moving to a user system mode from a user process, and changing the user process into a kernel mode in response to the request.

Abstract: Methods and apparatuses are provided that enable software designed to be operated with an embedded system to be tested in the absence of a physical embodiment of the embedded system. A simulation of the embedded system may be employed to operate the software. Various implementations of the invention provide for the processing of requests by the software to access memory within the embedded system. Still, various implementations of the invention provide for the identification of these memory access request and for the mapping of the desired memory location to a valid memory location.

Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.

Abstract: Methods and apparatuses enable on-demand instruction emulation via user-level exception handling. A non-supported instruction triggers an exception during runtime of a program. In response to the exception, a user-level or application-level exception handler is launched, instead of a kernel-level handler. Then the exception handler can execute at the application layer instead of the kernel level. The handler identifies the instruction and emulates the instruction, where emulation of the instruction is supported by the handler. Emulating the instructions enables the program to continue execution. Repeated instruction emulation is amortized via dynamic binary translation of hot code.

Abstract: A method includes determining a plurality of memory addresses, each memory address being different from one another. The method further includes generating a plurality of system management interrupt interprocessor interrupts, each system management interrupt interprocessor interrupt having a corresponding processor in a plurality of processors in a system and each system management interrupt interprocessor interrupt including one of the plurality of memory addresses. The method further includes directing each system management interrupt interprocessor interrupt to the corresponding processor. An associated machine readable medium is also disclosed.

Abstract: A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.

Abstract: An apparatus and method are provided for extending a microprocessor instruction set to allow for selective suppression of interrupts at the instruction level. The apparatus includes translation logic and extended execution logic. The translation logic translates an extended instruction into corresponding micro instructions. The extended instruction has and extended prefix and an extended prefix tag. The extended prefix specifies that interrupt processing be suppressed until execution of the extended instruction is completed, where the extended instruction prescribes an operation to be performed according to an existing instruction set. The extended prefix tag is an otherwise architecturally specified opcode within an existing instruction set. The extended execution logic is coupled to the translation logic. The extended execution logic receives the corresponding micro instructions, and completes execution of the corresponding micro instructions prior to processing a pending interrupt.

Abstract: A method of processing data comprising: processing a function using a processor operable to perform a plurality of functions, the processor having interrupts enabled; receiving an interrupt at the processor; suspending processing of the function; accessing at least one control parameter, the at least one control parameter indicating whether processing of the function should be resumed from the point where it was interrupted or whether the function should be repeated following the interrupt; following completion of the interrupt continuing processing of the function either at a start of the function or at a point at which it was interrupted dependent upon the control parameter. A function being an application, a thread, a system software routine, or multiple processing steps defined by software.

Abstract: A processor including a coarse grained array including a plurality of function units and a plurality of register files, wherein a loop to be executed by the coarse grained array is split into a plurality of sub-loops, and when an interrupt request occurs while executing the sub-loop in the coarse grained array, the interrupt request is processed after the executing of the sub-loop is completed.

Abstract: An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results.

Abstract: An exception handling system for a packet processing system is described. In this exception handling system, there are several exception handlers. One of the exception handlers is selected based on packet processing state data relating to a packet undergoing processing by the packet processing system. The selected exception handler is configured to check for the presence of one or more potential exception conditions associated with the selected exception handler. If one or more of these potential exception conditions are determined to be present, a packet processor selectively modifies the packet processing state data relating to the packet.

Abstract: A source computer system with one instruction set architecture (ISA) is configured to run on a target hardware system that has its own ISA, which may be the same as the source ISA. In cases where the source instructions cannot be executed directly on the target system, the invention provides binary translation system. During execution from binary translation, however, both synchronous and asynchronous exceptions may arise. Synchronous exceptions may be either transparent (requiring processing action wholly within the target computer system) or non-transparent (requiring processing that alters a visible state of the source system). Asynchronous exceptions may also be either transparent or non-transparent, in which case an action that alters a visible state of the computer system needs to be applied.

Abstract: A method, system, apparatus, and computer program product is presented for processing instructions. A processor is able to receive multiple types of interruptions while executing instructions, such as aborts, faults, interrupts, and traps. A set of processor fields are used to indicate whether or not one or more trap modes are active, such as a single-step trap mode or a taken-branch trap mode. The activity of a trap mode is conditioned, i.e., restricted, modified, or qualified, with a trap mode conditioning field that indicates whether or not the trap mode should remain active during interruption processing. The use of a trap mode conditioning field allows an interruption handler to run at full speed without being interrupted by the trap mode, yet the trap mode is preserved so that other processing, such as instruction tracing, may continue after interruption processing.

Abstract: A system and method for including independent instructions into a test case for intentionally provoking interrupts that may be used in conjunction with an instruction shuffling process is presented. A test case generator builds a test case that includes intentional interrupt instructions, which are constructed to intentionally provoke an interrupt, such as an instruction storage interrupt (ISI), a data storage interrupt (DSI), and alignment interrupt, and/or a program interrupt (PI). When a processor executes the test case and invokes an interrupt to an interrupt handler, the interrupt handler does not resolve the interrupt, but rather increments an instruction address register or a link register and resumes test case execution at an instruction subsequent to the instruction that caused the interrupt.

Abstract: A processor chip that provides a dynamically selectable operating mode in which particular sequences of instructions are executed without an external interrupt. The processor chip comprises an architected bit that may be set by software and which enables the external interrupt of the processing system to be dynamically enabled/disabled. When a sequence of instructions constituting a data move operation is being issued, the architected bit is toggled to an interrupt disabled state so that execution of the sequence of instructions occurs without an external interrupt. Following the execution of the sequence of instructions, the architected bit is toggled to an interrupt enabled state, which causes instruction execution to be subjected to external interrupts.

Abstract: A method and apparatus are disclosed for discovering and selecting faults where more than one programming model is involved. The present invention enables selection of faults and the mappings necessary to handle exceptions across multiple code environments.

Abstract: A computer implemented method, data processing system, and computer program product for generating and applying a model to predict hardware performance hazards in a machine instruction sequence. The illustrative embodiments generate rules which specify relationships between a first instruction code sequence and hardware performance hazards. This rule generation is performed as a machine task rather than a human task (e.g., traditional hand coding tools). When a second instruction code sequence is received, the rules are applied to the second instruction code sequence. Responsive to a prediction that execution of the second instruction code sequence will cause the hardware performance hazards, instructions in the second instruction code sequence that cause the hardware performance hazards are identified.

Abstract: One or more new methods are added to existing object code. The existing object code includes a first method that is capable of producing a result. New code is added to the first method. The new code provides the result to one or more of the new methods. After the modification, the result (e.g. a return value or exception) from the first method can be accessed and used by other threads, processes, systems, entities etc. that were not originally programmed to access the result or exception.

Abstract: This invention provides flexible load latency to pipeline cache misses. A memory controller selects the output of one of a set of cascades inserted execute stages. This selection may be controlled by a latency field in a load instruction or by a latency specification of a prior instruction. This invention is useful in the great majority of cases where the code can tolerate incremental increases in load latency for a reduction in cache miss penalty.

Abstract: Tracking the order of issued instructions using a counter is presented. In one embodiment, a saturating, decrementing counter is used. The counter is initialized to a value that corresponds to the processor's commit point. Instructions are issued from a first issue queue to one or more execution units and one or more second issue queues. After being issued by the first issue queue, the counter associated with each instruction is decremented during each instruction cycle until the instruction is executed by one of the execution units. Once the counter reaches zero it will be completed by the execution unit. If a flush condition occurs, instructions with counters equal to zero are maintained (i.e., not flushed or invalidated), while other instructions in the pipeline are invalidated based upon their counter values.

Abstract: A system and method for instrumentation of software, the software comprising a set of instructions (program or code) which are executable on a processor of a system, for example a computer system. A location in the instruction to insert a probe is first identified. The instruction is replaced with the probe by copying the instruction to a predefined location. The instruction is executed in the kernel space. A first exception is generated upon encountering the probe and calling a first exception handler, and the first exception handler is configured to call an instrumentation routine. A second exception is generated when the instrumentation routine encounters an error and calling a second exception handler, recovering from the exceptions and returning to a sane state to continue normal execution of the instruction.

Abstract: In one embodiment, the present invention includes a method for communicating a request for handling of a fault or exception occurring in an accelerator to a first instruction sequencer coupled thereto. The accelerator may be a heterogeneous resource with respect to the first instruction sequencer, e.g., of a different instruction set architecture. Responsive to the request, the fault or exception may be handled in the first instruction sequencer. Other embodiments are described and claimed.

Abstract: A computer-readable medium stores computer-executable instructions. The medium may hold: one or more instructions for executing a first code block; one or more instructions for generating an exception object based on the executing of the first code block; one or more instructions for receiving the exception object at a second code block; and one or more instructions for storing the exception object in a memory.

Abstract: A method, system and processor for improving the performance of an in-order processor. A processor may include an execution unit with an execution pipeline that includes a backup pipeline and a regular pipeline. The backup pipeline may store a copy of the instructions issued to the regular pipeline. The execution pipeline may include logic for allowing instructions to flow from the backup pipeline to the regular pipeline following the flushing of the instructions younger than the exception detected in the regular pipeline. By maintaining a backup copy of the instructions issued to the regular pipeline, instructions may not need to be flushed from separate execution pipelines and re-fetched. As a result, one may complete the results of the execution units to the architected state out of order thereby allowing the completion point to vary among the different execution pipelines.

Abstract: Mapping fault processing may be provided. First, user selectable elements may be received defining a process comprising a plurality of activities. Next, code may be produced, based on the received user selectable element, configured to implement the process. Then the code may be executed and an exception may be detected during the code execution. The exception may be scheduled in a queue and one of the following may be performed: handling the exception and compensating for the exception. Handing the exception may comprise undoing one of the plurality of activities that was partially completed and unsuccessful. Compensating for fie exception may comprise undoing one of the plurality of activities that was completed.

Abstract: A microcontroller comprising a central processing unit and a further fault processing unit suitable for performing validation of operations of said central processing unit. The further fault processing unit is external and different with respect to said central processing unit and said further fault processing unit comprises at least a module for performing validation of operations of said central processing unit and one or more modules suitable for performing validation of operations of other functional parts of said microcontroller. Validation of operations of said central processing unit is performed by using one or more of the following fault tolerance techniques: data shadowing; code&flow signature; data processing legality check; addressing legality check; ALU concurrent integrity checking; concurrent mode/interrupt check.

Abstract: A processing device includes a timer and an exception controller configured to provide an exception indicator representative of a first exception. The processing device further includes a timer controller configured to selectively enable/disable the timer in response to the exception and based on a characteristic of the exception. A method of utilizing the processing device includes receiving an exception and determining a characteristic of the exception. The method further includes, at a first time, selectively enabling/disabling the timer of the processing device based on the characteristic, and, at a second time subsequent to the first time, accessing a count value stored at the timer. The method further includes providing the count value for output from the processing device.

Abstract: Various technologies and techniques are disclosed for providing concurrent exception handling. When one or more exceptions are received from concurrent workers, one or more exception handler functions are supplied. For each respective exception in the exception results, determine if the respective exception is one of a kind of exceptions handled by the one or more exception handler functions. If the respective exception is one of a kind handled by the exception handler functions, then run a particular handler of the exception handler functions and mark the respective exception as handled. Any unhandled exceptions are then processed appropriately. In one implementation, a collection of input data is processed to produce a collection of output results, with the exceptions being interleaved with other output results. In another implementation, a particular exception is selected that represents the multiple exceptions. The selected one particular exception is then thrown.

Abstract: A process executing on a computing system may encounter an exception. Pointers or other references created by the exception may identify portions of the computing system's memory containing the binary code that was executing at the time of the exception. The exception-causing code from the system memory may be compared to an original version of the code from a non-volatile source. If the comparison identifies a hardware corruption pattern, the computing system may communicate information about the process and the exception to an error analysis server. Using historical exception data, the error analysis server may determine if the identified corruption pattern is most likely the result of corrupt hardware at the computing system. If corrupt hardware was the most likely result of the exception, then the server may communicate with the computing system to recommend or initiate a hardware diagnostic routine at the computing system to identify the faulty hardware.

Abstract: Apparatus and processes, including computer implemented processes, for managing exceptions throwable during execution of methods in one or more classes by a machine. Each method includes an exception handler array defining exception handlers associated with the method. The method includes combining the exception handler arrays for all methods into a single exception handler table.

Abstract: Mock exceptions, including mock exception types, are defined by a host to be raised in a plug-in. The mock exceptions might be sanitized. They might be transported from the plug-in to the host. Mock exceptions might also be mapped to real exceptions, which are raised in the host and handled by the host.

Abstract: One embodiment of the present invention provides a system that uses an M-bit operating system (OS) kernel to support N-bit user processes. During operation, the system receives an exception. Note that the exception can be any event that needs to be handled by executing OS kernel code. Specifically, the exception can be a hardware interrupt, a software interrupt, an asynchronous interrupt, a synchronous interrupt, a signal, a trap, or a system call. Next, the system handles the exception by first switching the processor to the M-bit mode, and then executing M-bit OS kernel code which is designed to handle the exception. Note that the processor may primarily be designed to operate in the N-bit mode; the M-bit mode may primarily be provided for backward compatibility reasons.

Abstract: A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets a Bit flag in memory indicating that execution for the thread has been paused. The SET instruction is placed in the pipeline for execution. The following READ instruction for that thread, however, is prevented from entering the pipeline until, the SET instruction is executed and retired (resulting in a clearing of the Bit flag). Once the Bit flag has been cleared, the READ instruction is placed in the pipeline for execution. During the time that processing of one thread is paused, the execution of other threads may continue.

Abstract: Described are methods and systems that allow partial speculation (e.g., speculation within constraints). With partial speculation, after a fault is detected for example, speculation remains enabled for processor registers and other memories private to a microprocessor, while speculation normally permitted for certain other operations is suspended. Accordingly, while the fault is dispatched, some speculation is permitted as opposed to suspending all speculation. As such, microcode that makes use of speculation can be written.

Abstract: A system, method and article of manufacture return code management in autonomic systems and more particularly to managing execution of operations in data processing systems on the basis of return code tracking. One embodiment provides a method for managing execution of an operation in a data processing system. The method comprises tracking return codes received from previous executions of the operation in the data processing system, determining an execution behavior of the operation from the tracked return codes, and managing a subsequent execution of the operation on the basis of the determined execution behavior.

Abstract: Exception handling is simulated. An exception simulator is employed to simulate exceptions generated from routines simulating operations. The exception simulator provides an indication of the exception and invokes an interruption, when appropriate. The exception simulator includes an instruction invoked to handle the exception and any interruption.

Abstract: A method and system for executing 32-bit flat address programs during a System Management Interrupt. The system provides a 16-bit SMI routine that is given control when an SMI occurs. That routine initially saves the state of the processor and then executes an instruction to switch to protected mode. When in protected mode, the routine transfers control to 32-bit code. The 32-bit code uses a global descriptor table that is different from that used by the interrupted operating system. When the 32-bit code completes, it restores the saved processor state and returns from the interrupt by executing an RSM instruction.

Abstract: Described is method and apparatus for handling exception signals in combination particularly with the dynamic conversion of binary code executable by a one computing platform into binary code executed instead by another computing platform. An exception handling unit selectively handles some exception signals with respect to a target state and handles others with respect to a subject state derived from the target state. Signal handling sub-units are arranged to process the exception signal with respect to the target state and output a request either to return to execution or to pass on the exception signal. A delivery path selection unit is arranged to determine a delivery path of the exception signal to a selected group of the plurality of signal handling sub-units. A signal control unit is arranged to deliver the exception signal in turn to each of the selected group of signal handling sub-units.

Abstract: A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion that is executed on the h-flow pipeline. The non-essential portion includes hint calculus that is used to provide hints to the main pipeline. The conjugate processor also includes a conjugate mapping table that maps triggers to h-flow targets. Triggers can be instruction attributes, data attributes, state attributes or event attributes. When a trigger is satisfied, the h-flow code specified by the target is executed in the h-flow pipeline.

Abstract: Provided is a microcomputer having the improved flexibility in changing correspondences between exception causes and exception vectors. The microcomputer includes: a vector candidate output section capable of outputting a plurality of vector candidates; an address selecting section selecting, as an exception vector, one of the vector candidates according to an exception cause; an instruction execution section starting an exception processing routine by accessing a memory area specified by the exception vector; and a correspondence changing section changing the number of exception causes associated with at least one of address candidates included in the vector candidates.

Abstract: Microprocessor arrangement and a method for operating a microprocessor arrangement, where the microprocessor arrangement has an execution unit for controlling a program cycle and for processing arithmetic and logic operations, a working register which stores a result of an operation and which is coupled to a control element in the execution unit, a flag register which indicates information about the result of the operation using flag bits, and combinational logic elements which are connected to the working register, wherein the combinational logic elements are controlled such that the state of the flag bits in the flag register is updated after the executed operation only if execution of one of subsequent operations within the program cycle requires a status of the flag bits.

Abstract: An embodiment of the invention is a processor for detecting one or more groups of instructions and initiating a processor action upon detecting one or more groups of instructions. The processor includes an instruction unit for fetching and decoding a group of instructions. An instruction register receives the group of instruction having at least one instruction opcode. A control register includes a control word including a control opcode and an action field defining a processor action. An execution unit includes compare logic for comparing the instruction opcode and the control opcode. The execution unit initiates the processor action upon the compare logic detecting a hit between the instruction opcode and the control opcode.

Abstract: A technique for enabling a computer processor to be capable of responding with comparable efficiency to both: (i) events whose handling is independent on the state of the software machine that responds to the events, and (ii) events whose handling is dependent on the state of the software machine that responds to the events. Each time a software state machine enters a state, one or more event control registers are programmed to direct the illustrative embodiment where to resume execution when each possible event occurs. This enables the illustrative embodiment to automatically branch to the code that is appropriate for the combination of the event and the state of the software machine.

Abstract: A method of determining request transmission priority subject to request channel and transmitting request subject to such request transmission priority in application of Fieldbus communication framework in which the communication device determines whether the request channel from which the received requests came have the priority right and whether there is any logical operation condition established, and then the communication device transmits the received external requests to the connected slave device as an ordinary request or priority request, preventing the slave device from receiving an important external request sent by the main control end or manager at a late time.