Abstract: An asynchronous processor having pipelined instruction fetching and execution to implement concurrent execution of instructions by two or more execution units. A writeback unit is connected to execution units and memory units to control information updates and to handle precise exception. A pipelined completion mechanism can be implemented to improve the throughput.

Abstract: An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the number of inputs of an instruction; a waiting data storage region that stores N(N≧2) waiting data and respective data valid flags in one address; a constant storage that stores constants and a constant valid flag; a constant readout unit that reads out a constant and a constant valid flag from the constant storage with the node number of the packet as the address; a unit that calculates the address and selects a process for data waiting depending upon a combination of a data valid flag, a constant valid flag, and the number of instruction inputs; and a unit that performs the waiting process in response to the select signal.

Abstract: An arbitrator provided to a processor element requests the utilization of a bus sends a bus request signal and a bus request value according to a priority level of the processor element to the bus, determines the priority of utilizing the bus in accordance with utilizing situation of the bus and the priority level of the processor element. Since a common bus arbitrating circuit connected to the bus watches the bus and determines a processor element to utilize the bus according to the utilizing situation of the bus and the priority level of the processor elements requesting the utilization of the bus, the bus arbitration can be performed with high speed, and an increase of communication speed between the processor elements through a single bus can be realized.

Abstract: When a prescribed operation is performed on 1024-bit multiple-precision data in a data-driven processor, the multiple-precision data is treated as a plurality of single-precision data obtained by dividing the multiple-precision data by every 32 bits in accordance with the memory word length of an accumulation memory, and a group of 32 memory words each having 32 bits of the accumulation memory is treated as the multiple-precision data. Accordingly, in the data-driven processor, a usual memory region can serve as an accumulator for multiple-precision data without having to provide any accumulator dedicated to multiple-precision data in the data-driven processor. In addition, since the multiple-precision data is divided into independent single-precision data each having 32 bits, operations for all data can be performed concurrently. Thus, a parallel processing capability of the data-driven processor can be maximized.

Abstract: A router is formed by an M-input, 1-output junction unit and a 1-input, N-output branching unit. Where M and N satisfy the relation of (M>N), the transfer rate of a path between the junction unit and the branching unit is made the total sum of the transfer rates of inputs of IN1 to INM, whereby N times faster transfer becomes possible.

Abstract: A C element controls a pipeline register and successively transfers data packets. When a dead-lock state occurs, a data packet in the pipeline register is erased by a master reset signal, a host transfer flag operating circuit overwrites a data packet in the pipeline register so that it has a host transfer flag at the “H” level, and thereafter, when the host transfer flag is detected in the subsequent stage, the data packet is transferred to the host.

Abstract: The disclosure relates to microprocessors and, more particularly, to a system for organizing and a method for the sequencing of the circuits of a microprocessor. The instruction registers are connected in chains and an inhibiting device is associated with each instruction register. Each inhibiting device has its inputs connected to the inputs of the associated register and to the clock circuit a provides and signal for the loading of the associated instruction register when it detects a predetermined combination of digits in the associated register.

Abstract: A system and method of executing instructions within a counterflow pipeline processor. The counterflow pipeline processor includes an instruction pipeline, a data pipeline, a reorder buffer and a plurality of execution units. An instruction and one or more operands issue into the instruction pipeline and a determination is made at one of the execution units whether the instruction is ready for execution. If so, the operands are loaded into the execution unit and the instruction executes. The execution unit is monitored for a result and, when the result arrives, it is stored into the result pipeline. If the instruction reaches the end of the pipeline without executing it wraps around and is sent down the instruction pipeline again.

Abstract: The invention relates to computer science, in particular, to a computer system comprising a processor, an input-output switch, an instruction loading switch, instruction memory, and a data access unit which uses the dataflow principle of computation. Performance is increased by decreasing the volume of associative memory by means of the introduction of the use of a fragment routine processor to process segments of the program which are better processed by von Neumann principles of computation.

Abstract: A system and method for manipulating waveforms, including transaction cancellation, in parallel time-warp simulation of circuits, such as those modeled in VHDL. Events waveforms for each output of a processor are organized by the simulation time (ST) of the events which created them and by the simulation time (RT) at which they are to be effective. A phantom buffer provides a linked list of events and associated transactions cancelled as a result of insertion of a new event in said chain of events. Rollback of a cancelled event waveform is done by restoring to the linked lists selected events and transactions from the phantom buffer.

Abstract: A circuit and method is disclosed which reduces data dependencies between instructions within an application program thereby reducing time delays associated therewith. In one embodiment, a data dependent instruction is translated into at least first and second speculative data independent instructions wherein the data dependent instruction, if executed, produces results which are dependent on a data result provided by execution of a data independent instruction. The first and second speculative data independent instructions are executed to generate first and second speculative results. It is noted that these results are generated independent of the results produced by executing the data independent instruction. Once the data independent instruction is executed and its data result is generated, one of the first and second speculative results is invalidated depending on the value of the data results.

Abstract: Pre-designed and verified data-driven hardware cores (intellectual property, functional blocks) are assembled to generate large systems on a single chip. Token transfer between cores is achieved upon synchronous assertion, over dedicated connections, of a one-bit ready signal by the transmitter and a one-bit request signal by the receiver. The ready-request signal handshake is necessary and sufficient for token transfer. There are no combinational paths through the cores, and no latches or master controller are used. The architecture and interface allow a significant simplification in the design and verification of large systems integrated on a single chip.

Abstract: A parallel computer including a plurality of processing elements, each of processing elements comprising a flag address holding unit for temporarily holding an address of a send complete flag of a direct remote write message when the direct remote write message is sent to another processing element, and a flag update unit for exclusively updating a flag represented by the address held in the flag address holding unit when data indicated by the direct remote write message has been sent.

Abstract: Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shift count for each operand. Operands and shift counts are successively transferred to a vector shift functional unit, which shifts the operand by an amount equal to the value of the shift count. The shifted operands are stored in a third vector register. The vector shift functional unit also achieves word shifting of a predetermined number of vector register elements to different word locations of another vector register.

Abstract: A method and strobe circuit are provided for maintaining a strobe signal at a valid voltage level. The method includes driving the strobe signal at the valid voltage level using a first strobe driver, pre-driving the strobe signal at the valid voltage level using a second strobe driver while the first strobe driver is driving, and terminating the driving of the first strobe driver. The strobe circuit includes a strobe line, a first strobe driver having a first enable input for enabling the first strobe driver and adapted to drive the strobe line with a first strobe signal, and a second strobe driver having a second enable input for enabling the second strobe driver and adapted to drive the strobe line with a second strobe signal. A first strobe controller is coupled to the second enable input and adapted to enable the second strobe driver to pre-drive the second strobe signal while the first strobe driver is enabled, wherein the first and second strobe signals are at equal logic levels.

Abstract: In an apparatus having a network including successive stages of cross-point switches which collectively interconnect a plurality of nodes external to said network, wherein at least one message is carried between one of the nodes and one of the cross-point switches over a route through said network, a method for preventing routing deadlocks from occurring in the network which comprises the steps of: creating a graphical representation of the network; searching for the existence of cycles within the graphical representation; partitioning the graphical representation into at a first subgraph and a second subgraph if cycles exist in the graphical representation; searching for the existence of edges directed from the first subgraph to the second subgraph; and removing the edges directed from the first subgraph to the second subgraph.

Abstract: A counterflow pipeline is provided which includes an instruction pipeline having a plurality of stages for transmitting instruction packets in a first direction and a result pipeline having a plurality of stages for transmitting result packets in a second direction opposite the first direction. Each of the result pipeline stages corresponds to an instruction pipeline stage, the associated instruction and result pipeline stages being part of a counterflow pipeline stage. Arbitration logic coupled between the instruction and result pipelines facilitates the movement of instruction and result packets in the stages of the instruction pipeline and result pipeline, respectively, using a four-phase level signaling protocol. The arbitration logic prevents instruction and result packets from passing each other in their respective pipelines by inhibiting them from being simultaneously released from adjacent counterflow pipeline stages. Thus, any necessary interaction between the two data packets may take place.

Abstract: A floating point unit has a control unit, a data input register and a write stage register from which an instruction is transferred from the floating point unit to a storage unit. The floating point unit typically has multiple pipeline stages for arithmetic computation, a normalization stage, and a rounding stage, each of which pipeline stages may during processing of a stream of instructions contain a separate instruction. The stages are connected in an ordered manner such that the processing of instructions occurs in the pipeline. An active instruction is a "stalled" instruction within a pipeline when forward progress is not permitted to advance to a new stage in the pipeline because data needed is not available for a prior instruction creating a data dependency.

Abstract: An asynchronous circuit having a pipelined completion mechanism to achieve improved throughput.

Abstract: At least one peripheral processing apparatus and at least one information processing apparatus, interconnected through a network, include a storage means for storing control information by which the information processing apparatus controls the peripheral apparatus through the network. The control information stored in the storage means is transferred through the network to the information processing apparatus, which receives it, the control data being generated by the information processing apparatus based upon the control information transferred to the information processing apparatus control means executes control process according to the data control received.

Abstract: A processor that executes coded instructions using an instruction scheduling unit receiving the coded instructions and issuing an instruction for execution. A replay signaling device generates a signal indicating when the instruction failed to execute properly within a predetermined time. A replay device within the instruction scheduling unit responsive to the signaling device then reissues the instruction for execution.

Abstract: The invention relates to a processor having a data flow unit for processing data in a plurality of steps. In one version, the data flow unit includes a plurality of consecutive stages which include logic for performing steps of the data processing, the stages being coupled together by a data path, at least one stage being coupled to a transceiver which causes data to be provided to the stage for processing or to bypass the stage unprocessed in response to a stage enable signal; a synchronizer which receives processed data from the stages and causes the processed data to be provided to external logic in synchronization with a clock signal.

Abstract: A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instructions in-order.