Abstract: A method and system for messaging between processors and co-processors connected through a bus. The method permits a multi-thread system processor to request the services of a processor or co-processor located on the bus. Message control blocks are stored in a memory which identify the physical address of the target processor, as well as a memory location in the memory dedicated to the thread requesting the service. When the system processor requests service of a processor or co-processor, a DCR command is created pointing to the message control block. A message is built from information contained in the message control block or transferred to the processor or co-processor. The return address for the processor or co-processor message is concatenated with the thread number, so that the processor or co-processor can create a return message specifically identifying memory space dedicated to the requesting thread for storage of the response message.

Abstract: Systems and methods that allow for performing a single transaction that both instructs a device to perform an operation and return the resulting data to a processor without the processor having to send a separate request for the result. In accordance with the systems and methods, a bus controller generates a system bus operation that sends (to the device) a thread identifier and a data request formulated in one thread by a processor that context switches to a second thread.

Abstract: A method, apparatus, and computer instructions for broadcasting information. A change in data used by a number of processors in the data processing system is identified. A message is sent to the number of processors in the data processing system in which the message is sent with a priority level equal to a set of routines that use the data in response to identifying the change. This message is responded to only when the recipient is at an interrupt priority less favored than the priority of the message. A flag is set for each of the number of processors to form a plurality of set flags for the message in which the plurality of set flags are located in memory locations used by the number of processors in which the plurality of set flags remains set until a response is made to the message.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: In one embodiment, a method is provided. The method of this embodiment includes generating, by a processor that includes a plurality of processing engines capable of executing program instructions, a packet. The method of this embodiment also includes transmitting the packet to at least one of the processing engines. Additionally, the method of this embodiment also includes, in response, at least in part to receipt of the packet by the at least one of the processing engines, modifying at least in part, by the at least one of the processing engines, a set of program instructions that the at least one processing engine is capable of executing. Of course, many modifications, variations, and alternatives are possible without departing from this embodiment.

Abstract: A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor-based packet processing mechanism for use in efficiently assigning and processing packets to a plurality of processors. A plurality of descriptors associated with each packet transfer are written back to memory in order, divided into subset groups and assigned to processors, where each processor searches the assigned subset for EOP and associated SOP descriptors to process.

Abstract: The invention relates to an information processing device (1), including a user control unit (2) for the selection of units of primary information to be processed and functions to be invoked. The device also includes storage means (3) for storing the primary information. From the selections made by the user the device derives personalizing information concerning the use of the device and the primary information processed with the device. The personalizing information is stored separately and represents a history of the usage of the device, thus making the device more personalized to its owner.

Abstract: A computer system has a node and a service processor (SVP) connected together via a diagnosis section. An input/output (I/O) unit is connected to the SVP. The diagnosis section has a serial controller. The SVP writes data to be transmitted to the node from the I/O unit into the serial controller. The node reads data stored in the serial controller. The node also writes data to be transmitted to the I/O unit into the serial controller. The serial controller instructs the SVP to read the data written by the node. The SVP reads this data and sends it to the I/O unit.

Abstract: A system and method for verifying a memory consistency model for a shared memory multiprocessor computer systems generates random instructions to run on the processors, saves the results of the running of the instructions, and analyzes the results to detect a memory subsystem error if the results fall outside of the space of possible outcomes consistent with the memory consistency model. A precedence relationship of the results is determined by uniquely identifying results of a store location with each result distinct to allow association of a read result value to the instruction that created the read result value. A precedence graph with static, direct and derived edges identifies errors when a cycle is detected that indicates results that are inconsistent with memory consistency model rules.

Abstract: A system for collecting events relating to multiple distributed physical systems includes multiple event collection cards (100), each receiving events from one of the distributed physical systems. Each event collection card includes a time stamp clock (120) configured to provide a time stamp when each event is received, an event memory (110) configured to store the received events, a sync interface unit (130) configured to receive a sync signal, a sync control unit (125) configured to synchronize the time stamp clock (120) to the sync signal received by the sync interface (130), and a collection control unit (115) configured to time stamp the collected events according to the time stamp clock (120) synchronized to the sync signal, and to store the time stamped events in the event memory (110).

Abstract: A process for packing an instruction word including providing a word value representing an instruction word into which an operation is to be fit be equal to some initial value having a plurality of portions representing constraints, operating on the initial value of the value word with operation class values having a plurality of portions representing constraints of a new operation as the new operation is attempted to be fit into the instruction to affect the processor word value in a manner to indicate when the limit of any constraint for the instruction is reached, and determining a violation of any constraint to determine that the new operation does not fit the format.

Abstract: A processor communication register (PCR) contained in each processor within a multiprocessor cluster network provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR within the cluster network and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs via a private protocol or dedicated wireless network, instantly allowing all of the other processors within the cluster network to see the change within the PCR data, and bypassing the cache subsystem.

Abstract: A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction.

Abstract: A method, apparatus, and computer instructions for broadcasting information. A change in data used by a number of processors in the data processing system is identified. A message is sent to the number of processors in the data processing system in which the message is sent with a priority level equal to a set of routines that use the data in response to identifying the change. This message is responded to only when the recipient is at an interrupt priority less favored than the priority of the message. A flag is set for each of the number of processors to form a plurality of set flags for the message in which the plurality of set flags are located in memory locations used by the number of processors in which the plurality of set flags remains set until a response is made to the message.

Abstract: A method of operation within a processor that permits load instructions following barrier instructions in an instruction sequence to be issued speculatively. The barrier instruction is executed and while the barrier operation is pending, a load request associated with the load instruction is speculatively issued. A speculation flag is set to indicate the load instruction was speculatively issued. The flag is reset when an acknowledgment of the barrier operation is received. Data that is returned before the acknowledgment is received is temporarily held, and the data is forwarded to the register and/or execution unit of the processor only after the acknowledgment is received. If a snoop invalidate is detected for the speculatively issued load request before the barrier operation completes, the data is discarded and the load request is re-issued.

Abstract: A system and method for producing a fused instruction is described. In one embodiment, a first instruction and a second instruction that are both simple instructions (e.g., perform only one operation) and are dependent are fused together to create the fused instruction. The fused instruction has an opcode that represents the operation performed by the first instruction and the operation performed by the second instruction. The fused instruction has three source operands and one destination operand. Two of the three source operands are the two source operands of the first instruction, and the third source operand is the source operand of the second instruction that is not the destination operand of the first instruction. The destination operand of the fused instruction is the destination operand of the second instruction. An execution unit that can execute a fused instruction in one clock cycle is also disclosed.

Abstract: An electronic control apparatus for a control object makes a mode check before each program part is retrieved even at a predetermined start timing, and inhibits a retrieval of program parts unnecessary for operation modes including a normal mode, inspection mode or rewrite mode. As it is not necessary to check the mode in the processing of each program part, the control processing for the control object can be executed efficiently in each mode. As the program parts unnecessary for the specified operation mode is not retrieved either in the specified operation mode, the processing efficiency is increased.

Abstract: A multi-processor system (10) includes a plurality of processors (12). Each processor (12) has an integrated memory (16) operable to provide, receive, and store data. Each processor (12) also includes an integrated memory controller (30) in order to control read and write access to the integrated memory (16). Additionally, each processor (12) includes an integrated memory directory (18) operable to maintain a plurality of memory references to data within the integrated memory (16). The multi-processor system (10) also includes an external switch (14) coupled to each of the plurality of processors (12). The external switch (14) passes data to and from any of the plurality of processors (12). The external switch (14) has an external directory (22). The external directory (22) provides a memory reference for each of the plurality of processors (12) to remote data that is not provided within its own integrated memory directory (18).

Abstract: Disclosed is a multiprocessor data processing system that executes loads transactions out of order with respect to a barrier operation. The data processing system includes a memory and a plurality of processors coupled to an interconnect. At least one of the processors includes an instruction sequencing unit for fetching an instruction sequence in program order for execution. The instruction sequence includes a first and a second load instruction and a barrier instruction, which is between the first and second load instructions in the instruction sequence. Also included in the processor is a load/store unit (LSU), which has a load request queue (LRQ) that temporarily buffers load requests associated with the first and second load instructions. The LRQ is coupled to a load request arbitration unit, which selects an order of issuing the load requests from the LRQ.

Abstract: Disclosed is a method of operating a processor, by which a speculatively issued load request, which fetches incorrect data, is recycled. An instruction sequence, which includes a barrier instruction and a load instruction that follows the barrier instruction in program order, is received for execution. In response to the barrier instruction, a barrier operation is issued on an interconnect. Following, in response to the load instruction and while the barrier operation is pending, a load request is issued to memory. When a pre-determined type of invalidate, which is affiliated with the load request, is received before the receipt of an acknowledgment for the barrier operation, data that is returned by memory in response to the load request is discarded and the load request is re-issued. The pre-determined type of invalidate includes, for example, a snoop invalidate.

Abstract: The invention presents a unique computational paradigm that provides the tools to take advantage of the parallelism inherent in parallel algorithms to the full spectrum from algorithms through architecture to implementation. The invention provides a new processing architecture that extends the standard instruction set of the conventional uniprocessor architecture. The architecture used to implement this new computational paradigm includes a thread control unit (34), a spawn control unit (38), and an enabled instruction memory (50). The architecture initiates multiple threads and executes them in parallel. Control of the threads is provided such that the threads may be suspended or allowed to execute each at its own pace.

Abstract: A computer system is presented which implements a system and method for ordering input/output (I/O) memory operations. In one embodiment, the computer system includes a processing subsystem and an I/O subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor executing software instructions. The I/O subsystem includes one or more I/O nodes serially coupled via non-coherent communication links. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). One of the processing nodes includes a host bridge which translates packets moving between the processing subsystem and the I/O subsystem. One of the I/O nodes is coupled to the processing node including the host bridges. The I/O node coupled to the processing node produces and/or provides transactions having destinations or targets within the processing subsystem to the processing node including the host bridge.

Abstract: In response to a need to initiate a global operation, a bus master within a multiprocessor system issues a combined token and operation request on a bus coupled to the bus master. The combined token and operation request solicits a token required to complete the global operation and identifies the global operation to be processed with the token, if granted. Upon receiving a combined response acknowledging both the token and operation portions of the combined request, the bus master treats the global operation as complete. If a combined response acknowledging the token portion of the combined request but retrying the operation portion (i.e., at least one snooper is busy processing a previous global operation), the bus master issues an operation request (only) for the operation portion of the combined request.

Abstract: A data processing system, method, and computer program product are disclosed for reporting a loss of a service application to a particular system administrator. The data processing system includes a logically partitioned computer system and a hardware management console. The hardware management console is a stand-alone system separate from the computer system. A service application is executable by the hardware management console for managing service of and placing service calls for the logically partitioned computer system. The logically partitioned computer system includes a service partition. A service processor included in the logically partitioned computer system monitors a presence of the service application, and reports the absence of the service application to the service partition. In response to an absence of the service application, the service partition reports the absence of the service application to a system administrator of the service partition.

Abstract: Each processor in a distributed shared memory system has an associated memory and a coherence directory. The processor that controls a memory is the Home processor. Under certain conditions, another processor may obtain exclusive control of a data block by issuing a Load Lock instruction, and obtaining a writeable copy of the data block that is stored in the cache of the Owner processor. If the Owner processor does not complete operations on the writeable copy of the data prior to the time that the data block is displaced from the cache, it issues a Victim To Shared message, thereby indicating to the Home processor that it should remain a sharer of the data block. In the event that another processor seeks exclusive rights to the same data block, the Home processor issues an Invalidate message to the Owner processor.

Abstract: A method and apparatus for bus compression in an array processing system, involving providing a data bus making multiple data bus connections between two separate processing modules; compressing bus signals outputted by at least one of the processing modules with an associated bus modulator effective to permit concurrent transfer of a plurality of bits of information per connection; transferring the compressed signals via the data bus to a bus demodulator associated with the other processing module, wherein the demodulator reconstructs the bus signals before inputting the signals to the other processing module; wherein at least one of the processing modules is formed at least in part in CMOS in a unique semiconductor structure.

Abstract: An operating system for distributed industrial controllers ensures the completion of enrolled application programs within a predetermined time span as is required for robust industrial control by preallocating dynamic and static hardware resources on a per application basis and in a manner that ensures execution of the application within the necessary time constraints. Portions of the distributed operating system may be distributed at particular hardware resources to provide necessary modeling for those hardware resources in making the commitments to resource bandwidths.

Abstract: A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. The microcode within the lock requesting node transmits a write command to write corresponding node identification data into a lock register in the arbitrating node. The lock requesting node iteratively reads the lock register until it finds its node identification data stored therein with a valid bit set. The lock requesting node then informs all remaining processing nodes to release shared system resources. This is accomplished through a release request bit and a release response bit in each processing node. After completion of lock operations, the lock requesting node sends a message to the arbitrating node to reset the valid bit in the lock register, and a broadcast message to each remaining node to reset the release request bit.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A synchronized system and method for the coordinated reading and writing of data to and from the shared main memory by the processing units also are provided. A hardware sandbox structure is provided for security against the corruption of data among the programs being processed by the processing units. The uniform software cells contain both data and applications and are structured for processing by any of the processors of the network. Each software cell is uniquely identified on the network.

Abstract: A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

Abstract: The method operates a parallel computer system with distributed memory. Each processor element has a local program memory, data memory and communications memory. Each processor element contains a communications manager unit with an address comparator and an address computation unit with entailed functionality. All processors globally write the global data and locally read the global data. A global address is adjoined to data written globally. For each processor element, an address comparator determines from the address whether the specific processor element is interested in these data. If yes, a local address computer determines the physical address in the processor memory. The parameters of the address comparator are agreed upon with the operating system before or during computation. The invention creates scalable multi-processor systems offering high communications performance using standard operating systems.

Abstract: A buffer cache management structure, or metadata, for a computer system such as a NUMA (non-uniform memory access) machine, wherein physical main memory is distributed and shared among separate memories. The memories reside on separate nodes that are connected by a system interconnect. The buffer cache metadata is partitioned into portions that each include a set of one or more management data structures such as hash queues that keep track of disk blocks cached in the buffer cache. Each set of management data structures is stored entirely within one memory. A first process performs operations on the buffer cache metadata by determining, from an attribute of a data block requested by the process, in which memory a portion of the metadata associated with the data block is stored. The process then determines if the memory containing the metadata portion is local to the process. If so, the first process performs the operation.

Abstract: A circuit and method is provided for selectively stalling interrupt requests originating devices coupled to a multiprocessor system. The multiprocessor system includes a plurality of circuit nodes each one of which is coupled to an individual memory. An I/O bridge coupled to a first circuit node is configured to generate non-coherent memory access command packets and non-coherent interrupt command packets. The first circuit node also generates a coherent interrupt command packet in response to receiving the non-coherent interrupt command packet. The first circuit node transmits the coherent interrupt command packet to another circuit node, possibly the second circuit node. However, the transmission of the coherent interrupt command packet may be delayed. Any delay in transmission is based on a comparison of the pipe identifications of the non-coherent command packets.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. Each instance keeps track of the CPUs in the system and their respective operational statuses relative to the instance, such as compatibility with the instance, control by the instance, and availability to the instance for SMP processing.

Abstract: The present invention provides an address resolution method for use in a multiprocessor system with distributed shared memory. The method allows users to change a memory configuration and a system configuration to increase system operation flexibility and to isolate errors. A cell controller indexes into an address resolution table using the high-order part of a processor-specified address. A write protection flag specifies whether to permit write access from other cells. An attempt to write-access a cell inhibited for write access causes a logical circuit to output an access exception signal.

Abstract: A local area computer network provides distributed parallel processing. The network comprises a plurality of workstations or personal computers, each having preemptive multitasking for the interactive execution of a local task in the foreground concurrently with a remote network subtask in the background. A large compute-intensive task may be partitioned into a plurality of parallel subtasks executed simultaneously with each subtask executed in the background by a respective workstations without substantial interference with the local task being executed concurrently in the foreground. The computer time and processing power which would otherwise be wasted while waiting for slow input/output operations is instead utilized to provide a powerful parallel multiprocessor system for handling compute-intensive tasks too large for an individual workstations.

Abstract: An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analogue and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. External pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test data or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SER-CLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control.

Abstract: A system in which a single VLAN architecture spans multiple VLAN transport protocols and technologies, including a method and system in which multiple different VLANs may be combined in a single enterprise network. Each LAN-switch in the system identifies each frame with an identifier, and associates that identifier with particular VLAN identifiers for each type of VLAN technology. When a frame is bridged or routed from a first type of VLAN to a second type of VLAN, the first VLAN encapsulation is removed and the second VLAN encapsulation is added, with appropriate change in the VLAN identifier for the frame or packet. The identifier may also be implicit for the frame, such as when a particular set of sender's MAC addresses are identified with a particular VLAN. Individual VLANs, of whatever architecture, may be added, configured or reconfigured, modified, or deleted, using control tools associated with the multiple VLAN architecture system.

Abstract: The present invention provides a cross-bar switch which includes a plurality of master bus ports, the master bus ports adapted to receive a plurality of master buses; a plurality of slave bus ports, the slave bus ports adapted to receive a plurality of slave buses; a manner of switching for selectively coupling the plurality of master bus ports to the plurality of slave bus ports; and a manner of configuration for prioritizing access requests by the plurality of master buses to the plurality of slave buses via the switching means. The cross-bar switch of the present invention has the capability of prioritizing requests between multiple parallel high speed buses. In a preferred embodiment, this arbitration is accomplished through Configuration Registers on the cross-bar switch. The Configuration Registers are programmable through the Device Control Register bus, which allows the cross-bar switch to be dynamically programmed and changed by a processor in a larger system.

Abstract: A system and method for handling system management interrupts in a multi-processor computer is disclosed. When the computer enters system management mode, the method uses the registers of each processor to get currently executing opcode to determine what each processor was doing before the interrupt. The method may have to first translate address information to locate the actual physical location of the currently executing opcode. The registers are stored in memory and the contents of the registers can be used to determine if the current processor caused the system management interrupt. If so, then the method now knows which processor caused the interrupt and can handle the interrupt accordingly. If, however, the processor was not the one that caused the interrupt, or if another processor also caused an interrupt, the method then repeats the above steps for the next processor of the multiprocessor system.

Abstract: A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.

Abstract: A distributed memory computer architecture associates separate memory blocks with their own processors, each of which executes the same program. A processor fetching data or instructions from its local memory also broadcasts that fetched data or instruction to the other processors to cut the time required for them to request this data. Runs of instruction and data local to one processor providing improved performance that is captured by the system as a whole by the ability of the other processors not executing local data or instructions to execute instructions out of order and return to find the data ready in buffer for rapid use.

Abstract: A computerized method for load balancing in a geographically distributed or clustered system is disclosed. An arbiter assigns clients to nodes. The arbiter partitions clients into groups based on their request load. Each group is dynamically scheduled among nodes, thus avoiding high load groups from being allocated to the same node and overloading the system. If one of the nodes becomes overload, an alarm is generated, so that fewer or no new clients are allocated to the overloaded node.

Abstract: Embedded systems employed in critical applications demand high reliability and availability in addition to high performance. Hardware-software co-synthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, cost, reliability, and availability goals. The present invention addresses the problem of hardware-software co-synthesis of fault-tolerant real-time heterogeneous distributed embedded systems. Fault detection capability is imparted to the embedded system by adding assertion and duplicate-and-compare tasks to the task graph specification prior to co-synthesis. The reliability and availability of the architecture are evaluated during co-synthesis. On embodiment of the present invention, called COFTA, allows the user to specify multiple types of assertions for each task. It uses the assertion or combination of assertions that achieves the required fault coverage without incurring too much overhead.

Abstract: In some embodiments, a computer system includes nodes connected through conductors. At least some of the nodes each include memory and processing circuitry to receive snoop requests in a node reception order and to initiate snoops of the memory in the node before the snoop requests are in a global order. The at least some nodes also each include an ordering buffer to receive the snoop requests and provide them at an output of the ordering buffer in the global order.

Abstract: A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.

Abstract: In the system bus controller of a multi-processor system, apparatus is provided for selecting one of the processors to handle an interrupt. A mask is provided for each respective task being executed on each one of the processors. Each mask includes a speculation bit identifying whether the task is speculative. Each mask includes a plurality of class enable bits identifying whether the task can be interrupted by a respective class of interrupts associated with each of the plurality of class enable bits. Control lines in the system bus receive an interrupt having a received interrupt class. A subset of the processors is identified; processors in the subset can be interrupted by the received interrupt based on the received interrupt class and the respective speculation bit and class enable bits assigned to the task being executed on each respective processor. A Boolean AND operation is performed on the mask associated with the respective task executing on each processor.

Abstract: Modular, portable data collection terminals are disclosed for use in mixed wireless and hard-wired RF communication networks, wherein various radio transmitter modules and associated antennas may be selectively added to a base terminal unit to solve networking problems associated with specific types of business environments. Modularity exists in both the hardware (splitting data collection and processing control circuitry from radio transitive control circuitry) and software (splitting transceiver-specific, lower level communication protocol from generic, higher level communication protocol). The control circuitry, including associated microprocessors devices, interact to selectively activate communication circuits to perform necessary communication or data processing functions and enter and remain in a power-saving dormant state during other times. To support such dormant or "sleeping" states, a series of communication protocols provide for channel access to the communication network.

Abstract: Multiprocessor architecture having advantages of both synchronous and asynchronous architectures. The multiprocessor (FIG. 10) comprises processors (300) operating in parallel and synchronously. Each processor operates at a different rate (a), so that each processor processes a data unit (316) in a different amount of time. An input distribution function (317) receives an input stream of data and distributes it to individual processors for processing, in amounts directly proportional to the operating rates of the individual processors, so that each processor processes all of the data distributed to it in the same amount of time as the other processors. Input data buffers (301) connected to processors operate synchronously with the connected processors, receiving and storing the distributed data and inputting it to the connected processors at rates synchronized with the processors' operating rates.