Abstract: Disclosed are a method, a system and a computer program product for dynamically allocating and/or de-allocating resources and/or partitions that provide I/O and/or active storage access services in a supercomputing system. The supercomputing system can include multiple compute nodes, high performance computing (HPC) switches coupled to the compute nodes, and active non-volatile storage devices coupled to the compute nodes. Each of the compute nodes can be configured to communicate with another compute node through at least one of the HPC switches. In one or more embodiments, each of at least two compute nodes includes a storage controller and is configured to dynamically allocate and de-allocate a storage controller partition to provide storage services to the supercomputing system, and each of at least two compute nodes includes an I/O controller and is configured to dynamically allocate and de-allocate an I/O controller partition to provide I/O services to the supercomputing system.

Abstract: A multi-service processing method, including: configuring different cores of a multi-core processor to process different services; and sending received packets to the cores in the pre-defined service processing sequence. The multi-core processor apparatus, includes the configuration management unit, the packet distributing unit, and the multi-core processor. The method and apparatus can save investments in devices while implementing multiple service processing functions.

Abstract: The present invention relates generally to computer programming, and more particularly to, systems and methods for parallel distributed programming. Generally, a parallel distributed program is configured to operate across multiple processors and multiple memories. In one aspect of the invention, a parallel distributed program includes a distributed shared variable located across the multiple memories and distributed programs capable of operating across multiple processors.

Abstract: A distributed processing system includes a plurality of processing elements each having one or more inputs and one or more outputs, and a control unit to which the plurality of processing elements are connected, wherein based on a service execution request from a client, the control unit creates execution transition information in which the processing elements that are necessary to execute a specific service and an order of execution are specified.

Abstract: A general-purpose processing element has a program holding portion that can hold a program by which a specific function is implemented in the general-purpose processing element. A distributed processing system according to the invention includes a control unit, a plurality of processing elements connected to the control unit, and a client, wherein the plurality of processing elements include the above-described processing element.

Abstract: Systems and methods for decoding of compressed video enable the storing of compressed video data in a memory shared by a group of symmetric multiple processors. The video includes a plurality of frames and each of the plurality of frames has one or more slices. Such one or more slices are assigned, by a main processor, of the group of symmetric multiple processors to the group of multiple processors. The one or more assigned slices are partially decoded by the one or more of the group of multiple processors and the partially decoded one or more slices are stored in the memory. Subsequently, each of the plurality of frames having at least one partially decoded slice is assigned to one or more of the group of multiple processors. In a successive progression, the group of multiple processors in combination fully decodes each of the plurality of frames.

Abstract: This invention describes a baseband dual-core signal processing in mobile communication systems operating according to GSM, GPRS, or EDGE comprising a first digital signal processor adapted to perform tasks on a first time basis and a second digital signal processor adapted to perform tasks on a second time basis. The second time basis is an integer multiple of the first time basis.

Abstract: A hardware switch to which a plurality of processing elements are connected, wherein for sending side processing elements and receiving side processing elements different from the sending side processing elements selected from among the plurality of processing elements, the hardware switch interconnects one output selected from outputs that the sending side processing elements have and one input selected from inputs that the receiving side processing elements have, thereby selectively switching paths between the plurality of processing elements, and at least one of the number of outputs of the sending side processing element connected to the hardware switch and the number of inputs of the receiving side processing elements connected to the hardware switch is more than one.

Abstract: General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program that is written by a developer in a high-level language are automatically translated into a distributed execution plan. A set of extensions to a sequential high-level computing language are provided to support distributed parallel computations and to facilitate generation and optimization of distributed execution plans. The extensions are fully integrated with the programming language, thereby enabling developers to write sequential language programs using known constructs while providing the ability to invoke the extensions to enable better generation and optimization of the execution plan for a distributed computing environment.

Abstract: A data processing apparatus can reduce an occupancy rate of a ring bus by suppressing occurrence of a stall packet, and can change a processing sequence. In the data processing apparatus, a buffer is provided in each communication unit connecting the ring bus and the associated processing unit. Transfer of data from the communication unit to the processing unit is controlled by an enable signal. Consequently, occurrence of a stall packet is suppressed. Accordingly, frequency of occurrence of a deadlock state is reduced by decreasing the occupancy rate of the ring bus.

Abstract: General-purpose distributed data-parallel computing using high-level computing languages is described. Data parallel portions of a sequential program written in a high-level language are automatically translated into a distributed execution plan. Map and reduction computations are automatically added to the plan. Patterns in the sequential program can be automatically identified to trigger map and reduction processing. Direct invocation of map and reduction processing is also provided. One or more portions of the reduce computation are pushed to the map stage and dynamic aggregation is inserted when possible. The system automatically identifies opportunities for partial reductions and aggregation, but also provides a set of extensions in a high-level computing language for the generation and optimization of the distributed execution plan. The extensions include annotations to declare functions suitable for these optimizations.

Abstract: A multi-processor computer system is provided for managing physical memory domains. The system includes at least one processor having an address interface for sending a memory access message, which includes an address in physical memory and a domain identification (ID). The system also includes a physical memory portioned into a plurality of domains, where each domain includes a plurality of physical addresses. A domain mapping unit (DMU) has an interface to accept the memory access message from the processor. The DMU uses the domain ID to access a permission list, cross-reference the domain ID to a domain including addresses in physical memory, and grant the processor access to the address in response to the address being located in the domain.

Abstract: A processing apparatus includes: an operation detection unit that detects an operation; a request unit that requests other processing apparatuses to transmit functions when the operation is detected by the operation detection unit; a receiving unit that receives replies in response to the requests of the request unit from the at least one of the other processing apparatuses; a selection unit that selects at least one of the other processing apparatuses from which the receiving unit has received the replies; and a communication unit that performs communication with the at least one of the other processing apparatuses selected by the selection unit.

Abstract: A high performance sequencer/synchronizer controls multiple concurrent data processors and dedicated coprocessors and their interaction with multiple shared memories. This sequencer/synchronizer controls multi-threading access to shared memory.

Abstract: An information processing system includes a first system and a second system. The first system and the second system each includes: hardware; a compensation section configured to provide execution environments for execution of a process using the hardware of the system to which the compensation section belongs; and a processing section configured to execute a predetermined process in the execution environments provided by the compensation section. The hardware of the first system and the hardware of the second system are different in nature from each other. The compensation section of one of the first system and the second system compensates for the differences between the hardware of the first system and the hardware of the second system to provide the processing section of the other with the execution environments which are not affected by the differences between the hardware of the first system and the hardware of the second system.

Abstract: Systems and methods for parallelization of machine learning computing code are described herein. In one aspect, embodiments of the present disclosure include a method of generating a plurality of instruction sets from machine learning computing code for parallel execution in a multi-processor environment, which may be implemented on a system, of, partitioning training data into two or more training data sets for performing machine learning, identifying a set of concurrently-executable tasks from the machine learning computing code, assigning the set of tasks to two or more of the computing elements in the multi-processor environment, and/or generating the plurality of instruction sets to be executed in the multi-processor environment to perform a set of processes represented by the machine learning computing code.

Abstract: A packet processing device includes multiple processor cores and memory connected to the multiple processor cores, upon reception of a load request of a program, selects a processor core to which the program has not yet been loaded, loads the program to the selected processor core, retains first association information that associates attribute information specified by the load request with the processor core to which the program has been loaded, upon reception of the packet, specifies the attribute information corresponding to the received packet, and transfers the received packet to the processor core corresponding to the specified attribute information.

Abstract: A system for conveying critical and non-critical words of multiple cache lines includes a first node interface of a first processing node receiving, from a first processor, a first request identifying a critical word of a first cache line and a second request identifying a critical word of a second cache line. The first node interface conveys requests corresponding to the first and second requests to a second node interface of a second processing node. The second node interface receives the corresponding requests and conveys the critical words of the first and second cache lines to the first processing node before conveying non-critical words of the first and second cache lines.

Abstract: Distant parallelization of sequential programs is obtained by making parallelization decisions at the boundaries between program methods (e.g., functions and sub-routines). Experimentation suggests that such a partitioning allows for large-scale parallelization without data flow conflicts.

Abstract: A system and method for implementing a unified model for integration systems is presented. A user provides inputs to an integrated language engine for placing operator components and arc components onto a dataflow diagram. Operator components include data ports for expressing data flow, and also include meta-ports for expressing control flow. Arc components connect operator components together for data and control information to flow between the operator components. The dataflow diagram is a directed acyclic graph that expresses an application without including artificial boundaries during the application design process. Once the integrated language engine generates the dataflow diagram, the integrated language engine compiles the dataflow diagram to generated application code.

Abstract: A scheduler of a reconfigurable array, a method of scheduling commands, and a computing apparatus are provided. To perform a loop operation in a reconfigurable array, a recurrence node, a producer node, and a predecessor node are detected from a data flow graph of the loop operation such that resources are assigned to such nodes so as to increase the loop operating speed. Also, a dedicated path having a fixed delay may be added to the assigned resources.

Abstract: Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory. The information processing device comprises a basic side CPU 100 for executing basic processing and an addition side CPU 200 for executing additional processing, in which a transfer management unit 300 provided on the basic side CPU 100 transfers execution environment data 1000 including constitution information of an execution environment 30 of the additional processing to be executed on the addition side CPU and data in a memory corresponding to the execution environment to other information processing device and restores the execution environment to re-start the addition side CPU based on the received execution environment data 1000.

Abstract: Some embodiments comprise an apparatus for processing data, the apparatus having a second configurable processor configured to process data using second configuration data, and a configuration data re-manipulator configured to retrieve manipulated second configuration data and first data of a first processor, to re-manipulate the manipulated second configuration data depending on the first data, and to feed the re-manipulated second configuration data to the second configurable processor as the second configuration data.

Abstract: An arrangement of arithmetic logic units carries out an operation on at least one operand, wherein the operation is determined by operation codes received by the arithmetic logic units. The operation codes and at least one operand are received on a first clock cycle. The result of the operation is output from at least one arithmetic logic unit to at least one further arithmetic logic unit. A result of the plurality of arithmetic logic units is then output on a next clock cycle.

Abstract: The invention relates to a method for executing computer usable program code or a program made up of program parts on a multi-core processor (1) with a multiplicity of execution units (21, 22, 23, 24), each of which comprises a local memory (201) and at least one processing unit (202) communicatively linked to the local memory, wherein each of the execution units (21, 22, 23, 24) is connected to a communications network (30) for data exchange. One or more program parts are stored in at least some of the local memories (201) of the majority of execution units (21, 22, 23, 24). Execution of a program part is performed by the processing unit (202) of the particular execution unit (21, 22, 23, 24) that has the program part stored in its local memory (201).

Abstract: A multi-core system includes: a first core that writes first data by execution of a first program, wherein the first core gives write completion notice after completion of the writing; a second core that refers to the written first data by execution of a second program; and a scheduler that instructs the second core to start the execution of the second program before the execution of the first program is completed when the scheduler is given the write completion notice from the first core by the execution of the first program.

Abstract: A reconfigurable circuit design method includes an input step of inputting design data of a default configuration of a reconfigurable circuit including a plurality of processor elements which perform processing and a first generation step of generating design data obtained by modifying at least one of the processor elements in the reconfigurable circuit with the default configuration.

Abstract: The instant invention broadly contemplates an energy saving subsystem comprising a secondary CPU that utilizes less power than a main CPU, thereby allowing an electronic device (e.g. a laptop PC) having the secondary CPU to use less power and run for longer periods of time on a limited power supply. Thus, the invention permits the electronic device to be utilized for extended periods and extends the battery life.

Abstract: A technique for operating a high performance computing (HPC) cluster includes monitoring communication between threads assigned to multiple processors included in the HPC cluster. The HPC cluster includes multiple nodes that each include two or more of the multiple processors. One or more of the threads are moved to a different one of the multiple processors based on the communication between the threads.

Abstract: Provided are a data processing apparatus and a method of controlling the data processing apparatus. The data processing apparatus may select a single stream processor from a plurality of stream processors based on stream processor status information, and input data into the selected stream processor. The stream processor status information may include first status information of a processor core and second status information of at least one internal memory.

Abstract: Disclosed are methods and devices, among which is a system that includes one or more pattern-recognition processors, such as in a pattern-recognition cluster. The pattern-recognition processors may be activated to perform a search of a data stream individually using a chip select or in parallel using a universal select signal. In this manner, the plurality of pattern-recognition processors may be enabled concurrently for synchronized processing of the data stream.

Abstract: A Session Initiation Protocol (SIP) proxy server including a multi-core central processing unit (CPU) is presented. The multi-core CPU includes a receiving core dedicated to pre-SIP message processing. The pre-SIP message processing may include message retrieval, header and payload parsing, and Call-ID hashing. The Call-ID hashing is used to determine a post-SIP processing core designated to process messages between particular user pair. The pre-SIP and post-SIP configuration allows for the use of multiple processing cores to utilize a single control plane, thereby providing an accurate topology of the network for each processing core.

Abstract: The workload is heavy in the development of an application program that controls the task distribution in consideration of the variety of the execution environment. In a system where the processing is distributed to SPUs serving as plural processing entities so as to execute the computer program, the data processing is broken into plural units of processing by referring to the script code in which the content of the data processing is written, and the units of processing are assigned to the plural SPUs. Then, the whole computer program is executed when the SPUs execute the assigned process.

Abstract: In one aspect, a method of processing time-ordered multi-element data uses a set of computational nodes. In some examples, hundreds or thousands of nodes are used. A set of portions of the data are accepted, for example, from a MD simulation system. Each portion of the data is associated with a corresponding computational node in the plurality of computational nodes, and each portion representing a distinct range of time. Instructions for processing the data are accepted. These instructions include one or more instruction specifying a set of times, a set of elements, an analysis function, and an aggregation function. The accepted data is redistributed from within the portions at each computational node to multiple computational nodes in the plurality of computational nodes, such that data for any element of the specified set of elements is localized to a particular computational node.

Abstract: A gated-storage system including multiple control interfaces, each control interface operatively connected externally to respective multithreaded processors. The multithreaded processors each have a thread context running an active thread so that multiple thread contexts are running on the multithreaded processors. A memory is connected to a system-level inter-thread communications unit and shared between the multithreaded processors. The thread contexts request access to the memory by communicating multiple access requests over the control interfaces. The access requests are from any of the thread contexts within any of the multithreaded processors. A single request storage is shared by the multithreaded processors. A controller stores the access requests in the single request storage within a single clock cycle.

Abstract: A read-only memory (ROM) includes storage areas used as a processing setting data storage unit, a successful detection rate storage unit, and a processing time storage unit. A central processing unit (CPU) can function as a calculation unit by executing a calculation program stored on the ROM. The successful detection rate storage unit stores a predetermined successful detection rate (the probability of executing subsequent processing based on a result of a current processing). The processing time storage unit stores a predetermined processing time of each processing. The calculation unit calculates a module configuration for executing each processing according to the successful detection rate stored on the successful detection rate storage unit and the processing time stored on the processing time storage unit. The processing setting data storage unit stores setting data of a characteristic amount and a setting data of positional information about image data (the address of the image data).

Abstract: For flexibly setting up an execution environment according to contents of processing to be executed while taking stability or a security level into consideration, the multiple processor system includes the execution environment main control unit 10 which determines CPU assignment at the time of deciding CPU assignment, the execution environment sub control unit 20 which controls starting, stopping and switching of an execution environment according to an instruction from the execution environment main control unit 10 to synchronize with the execution environment main control unit 10, and the execution environment management unit 30 which receives input of management information or reference refusal information of shared resources for each CPU 4 or each execution environment 100 to separate the execution environment main control unit 10 from the execution environment sub control units 20a through 20n, or the execution environment sub control units 20aA through 20n from each other.

Abstract: A distributed processing system includes at least two processing elements (100 and 200) which are mutually connected, and each processing element having at least a processing section, a memory section, and a communication section. A first processing section (102) stores data in a predetermined area of a first memory section (101), or reads data stored in a predetermined area of the first memory section (101). A first communication section (103) of one processing element (100) transmits data read from the first memory section (101) to the other processing element (200), or stores data received from the other processing element (200) to the first memory section (101).

Abstract: A barrier synchronization device for realizing barrier synchronization of at least 2 processor cores belonging to a same synchronization group among a plurality of processor cores is included in a multi-core processor having a plurality of processor cores, and when two or more processor cores in that multi-core processor belong to the same synchronization group, the included barrier synchronization device is used for realizing barrier synchronization.

Abstract: A multiprocessor system includes first and second processors independently executing application functions associated with one or more applications using an open operating system (OS), a multiport memory, a first nonvolatile memory coupled to the first processor via a first bus, and a second nonvolatile memory coupled to the second processor via a second bus. The multiport memory includes a memory cell array divided into a plurality of memory banks including a shared memory bank commonly accessed by the first and second processors via respective first and second ports, and an internal register disposed outside the memory cell array and configured to control access authority to the shared memory bank by the first and second processors, wherein different application functions are independently executed in parallel by the first and second processors using the multiport memory as a data transfer mechanism.

Abstract: The disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The arrangement also enables MPEs delegate functionality to one or more groups of SPEs such that those group(s) of SPEs will act as pseudo MPEs. The pseudo MPEs will utilize pseudo virtualized control threads to control the behavior of other groups of SPEs. In a typical embodiment, the apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements.

Abstract: Among other things, the disclosure is applied to a generic microprocessor architecture with a set (e.g., one or more) of controlling/main processing elements (e.g., MPEs) and a set of groups of sub-processing elements (e.g., SPEs). Under this arrangement, MPEs and SPEs are organized in a way that a smaller number MPEs control the behavior of a group of SPEs using program code embodied as a set of virtualized control threads. The apparatus includes a MCP coupled to a power supply coupled with cores to provide a supply voltage to each core (or core group) and controlling-digital elements and multiple instances of sub-processing elements. In accordance with these features, virtualized control threads can traverse the physical boundaries of the MCP to control SPE(s) (e.g., logical partitions having one or more SPEs) in a different physical partition (e.g., different from the physical partition from which the virtualized control threads originated.

Abstract: A method and system for processing multimedia data is provided. The method for processing multimedia data in a multiprocessor system includes enabling communication between a plurality of processors in response to receipt of multimedia data. The method also includes providing portions of the multimedia data selectively to the plurality of processors. Further, the method includes processing the portions of the multimedia data by the plurality of processors. Moreover, the method includes synchronizing the portions of the multimedia data. The method also includes performing at least one of queuing the portions of the multimedia data to be played, playing the portions of the multimedia data and skipping the portions of the multimedia data based on the synchronizing. A system for processing multimedia data includes one or more sub-processors for processing portions of multimedia data selectively. The system also includes a master processor for synchronizing the portions of the multimedia data.

Abstract: A method and apparatus for enabling usage of an accelerator device in a processor socket is herein described. A set of inter-processor messages is utilized to initialize a configuration/memory space of the accelerator device. As an example, a first set of inter-processor interrupts (IPIs) is sent to indicate a base address of a memory space and a second set of IPIs is sent to indicate a size of the memory space. Furthermore, similar methods and apparatus' are herein described for dynamic reconfiguration of an accelerator device in a processor socket.

Abstract: A method of dynamic parallelization in a multi-processor identifies potentially independent computational operations, such as functions and methods, with a serializer that assigns a computational operation to a serialization set and a processor based on assessment of the data that the computational operation will be accessing upon execution.

Abstract: A mechanism is provided for invoking a multi-library application on a multiple processor system, wherein the multiple processor system comprises a Power Processing Element (PPE) and a plurality of Synergistic Processing Element (SPE). Applications including multi-libraries run in the memory of the PPE. The mechanism comprises maintaining the status of each SPE in the application running on the PPE, where there are SPE agents for capturing the instructions from the PPE in the SPEs that have been started. In response to a request for invoking a library, the PPE determines whether the number of available SPEs for invoking the library is adequate based on the current status of SPEs. If the number of available SPEs is adequate, the PPE sends a run instruction to selected SPEs. After finishing the invocation of all libraries, the PPE sends termination instructions to all started SPEs.

Abstract: Architectures for graphic engine chips with minimum impact on other resources are disclosed. According to one embodiment, a graphic engine architecture includes a scheduler that is configured to schedule an execution time for each of the drawing instructions sent in groups from a processor. Each drawing instruction includes a piece of time information. The scheduler is provided to fetch the drawing instructions from a FIFO buffer that buffers the drawing instructions. Subsequently, the drawing instructions are successively executed according to their scheduling.

Abstract: A system for processing a user application having a plurality of functions identified for parallel execution. The system includes a client coupled to a plurality of compute engines. The client executes both the user application and a compute engine management module. Each of the compute engines is configured to execute a requested function of the plurality of functions in response to a compute request. If, during execution of the user application by the client, the compute engine management module detects a function call to one of the functions identified for parallel execution, and the module selects a compute engine and sends a compute request to the selected compute engine requesting that it execute the function called. The selected compute engine calculates a result of the requested function and sends the result to the compute engine management module, which receives the result and provides it to the user application.

Abstract: A processor integrated circuit according to the present invention comprises low-speed and high-speed computing units (110), (120) as two or more kinds of computing units, a program memory (131) as a first storage unit in which programs for operation the computing units are stored, a data memory (second storage unit) (132) as a memory area to be used for computation by the computing units, and selectors (141), (142) as first and second connection switching units for connecting a computing unit that performs computation to the first and second storage units, wherein the program memory (131) and the data memory (132) are connected to the low-speed computing unit (110) or the high-speed computing unit (120). In this construction, it is possible to achieve both of securing in program compatibility and speeding-up without increasing the circuit scale and power consumption of the processor integrated circuit.

Abstract: A multiprocessor computer system comprises a dragonfly processor interconnect network that comprises a plurality of processor nodes, a plurality of routers, each router directly coupled to a plurality of terminal nodes, the routers coupled to one another and arranged into a group, and a plurality of groups of routers, such that each group is connected to each other group via at least one direct connection.