Abstract: A digital signal processor uses a number of independent sub-processors that may be controlled by a master programmable controller. For example, a specialized input processor may process input signals while a specialized output processor may process output signals. Each of these processors may also accomplish math functions when input and output processing is not necessary. The various processors may communicate with one another through general purpose registers which receive data and provide data to any of the processors in the system. Math processors may be added as needed to accomplish desired mathematical functions. In addition, a RAM processor may be utilized to hold the results of intermediate calculations in one embodiment of the present invention. In this way, an adaptable and scaleable design may be implemented that accommodates a variety of different operations without requiring redesign of all the components.

Abstract: A hardware accelerator is used to execute a floating-point byte-code in an information processing device. For a floating-point byte-code, a byte-code accelerator BCA feeds an instruction stream for using a FPU to a CPU. When the FPU is used, first the data is transferred to the FPU register from a general-purpose register, and then an FPU operation is performed. For data, such as a denormalized number, that cannot be processed by the FPU, in order to call a floating-point math library of software, the processing of the BCA is completed and the processing moves to processing by software. In order to realize this, data on a data transfer bus from the CPU to the FPU is snooped by the hardware accelerator, and a cancel request is signaled to the CPU to inhibit execution of the FPU operation when corresponding data is detected in a data checking part.

Abstract: Distant parallelization of sequential programs is obtained by making parallelization decisions at the boundaries between program methods (e.g., functions and sub-routines). Experimentation suggests that such a partitioning allows for large-scale parallelization without data flow conflicts.

Abstract: In an optical transmission device, firmware that operates within a CPU of a first LIU and firmware that operates within a CPU of a second LIU periodically measure a load status of a CPU via an OS, respectively. Switchover control of a master CPU is performed according to a load status of a CPU measured by the firmware of each LIU. For example, when a load status of the CPU of the second LIU is lower than that of the CPU of the first LIU, a master CPU that performs switchover control of a predetermined port is switched to a slave CPU in the first LIU, and a slave CPU related to the predetermined port is switched to a master CPU in the second LIU, thereby dynamically changing the setting.

Abstract: Disclosed are various embodiments for arbitration of memory transfers in a digital signal processing system. In one embodiment, a digital signal processing system includes a plurality of DSP's having an external memory. The DSP's are further configurable to act as a master processor and a slave processor relative to another DSP. The system also includes an arbiter configured to maintain DSP status data and arbitrate requests between master processors and slave processors in the system.

Abstract: Mechanisms for dynamically configuring the resources of a virtual multiprocessor are provided. An apparatus to configure resources for virtual processing elements in a virtual multiprocessor is provided. The apparatus includes a virtual multiprocessor context, virtual processing element contexts, and configuration logic. The virtual multiprocessor context, prescribes the resources, and controls a configuration state of the virtual multiprocessor. The virtual processing element contexts each exclusively correspond to a virtual processing element. The virtual processing element contexts each have first logic, for prescribing whether the virtual processing element is permitted to configure the resources; and second logic, for prescribing a subset of the resources that is allocated to the virtual processing element.

Abstract: A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables.

Abstract: A data processor and a method for processing data is disclosed. The processor has an input port for receiving packets of data to be processed. A master controller acts to analyse the packets and to provide a header including a list of processes to perform on the packet of data and an ordering thereof. The master controller is programmed with process related data relating to the overall processing function of the processor. The header is appended to the packet of data. The packet with the appended header information is stored within a buffer. A buffer controller acts to determine for each packet stored within the buffer based on the header within the packet a next processor to process the packet. The controller then provides the packet to the determined processor for processing. The processed packet is returned with some indication that the processing is done. For example, the process may be deleted from the list of processes.

Abstract: Methods, apparatus, and products are disclosed for configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks, the compute nodes in the operational group connected together for data communications through a global combining network, that include: partitioning the compute nodes in the operational group into a plurality of non-overlapping subgroups; designating one compute node from each of the non-overlapping subgroups as a master node; and assigning, to the compute nodes in each of the non-overlapping subgroups, class routing instructions that organize the compute nodes in that non-overlapping subgroup as a collective network such that the master node is a physical root.

Abstract: In a multiprocessor system (1), a processor (3) as a monitor monitors data read access performed by a processor (2) as a master to a memory (4) as a slave. The processor (3) acquires data outputted from the memory (4) when a data read-out command outputted from the processor (2) contains an address associated with the processor (3).

Abstract: Embodiments are disclosed for a system and method for parallel processing of video signals. A multi-core processor is used to establish a master-slave relationship between a first processing core and a plurality of individual processing cores. Shared memory is used to store data and control messages. A plurality of individual private memories are associated with each of the individual processing cores; and control logic is used to establish a master-slave protocol for using the plurality of individual cores to process video data. The master processing core is operable to balance the video data processing load among the individual slave processing cores.

Abstract: Dynamic cache architecture for a multi-processor array. The system includes a plurality of processors, with at least one of the processors configured as a parent processor, and at least one of the processors configured as a child processor. A data cache is coupled to the parent processor, and a dual port memory is respectively associated with each child processor part and parcel of a unified memory architecture. The parent processor may then dynamically distribute sub-cache components to dual-port memories based upon a scatter-gather work unit decomposition pattern. A parent cache controller reads, in response to a memory request from a child processor and an address translation pattern from the parent processor, a set of data from non-contiguous addresses of the data cache according to the address translation pattern, and writes the set of data to contiguous addresses of the dual port memory associated with the requesting child processor.

Abstract: A data processing apparatus comprises a plurality of processors and message processing logic operable for establishing one of the processors as a master processor and all other processors as slave processors; receiving an application message from a particular message source among a plurality of message sources coupled to one or more network interfaces and the processors, wherein the application message comprises one or more data frames, packets and segments; granting exclusive control of the particular message source to a selected one of the slave processors; assigning an ordered sequence number to the application message; granting exclusive control, for a particular message destination among a plurality of message destinations coupled to the network interfaces and the processors, to the selected one of the slave processors; and providing the application message to the particular message destination.

Abstract: Methods and systems are provided for partitioning data of a database or data store into several independent parts as part of a data mining process. The methods and systems use a mining application having content-based partitioning logic to partition the data. Once the data is partitioned, the partitioned data may be grouped and distributed to an associated processor for further processing. The mining application and content-based partitioning logic may be used in a computing system, including shared memory and distributed memory multi-processor computing systems. Other embodiments are described and claimed.

Abstract: A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.

Abstract: There is disclosed a processor array, which achieves an approximately constant latency. Communications to and from the farthest array elements are suitably pipelined for the distance, while communications to and from closer array elements are deliberately “over-pipelined” such that the latency to all end-point elements is the same number of clock cycles. The processor array has a plurality of primary buses, each connected to a primary bus driver, and each having a respective plurality of primary bus nodes thereon; respective pluralities of secondary buses, connected to said primary bus nodes; a plurality of processor elements, each connected to one of the secondary buses; and delay elements associated with the primary bus nodes, for delaying communications with processor elements connected to different ones of the secondary buses by different amounts, in order to achieve a degree of synchronization between operation of said processor elements.

Abstract: Plural CPUs are provided, and when a first CPU of the plural CPUs is a master, the other CPU operates as a slave. Also, plural memories are provided including a memory that operates and is used for first processing when the master CPU operates and a memory that operates and is used for second processing when the slave CPU operates. Every time an OS (Operating System) starts, the CPU to serve as a master is sequentially switched, then the remaining CPU is caused to serve as a slave, and the memories used for the first processing and the second processing are sequentially switched.

Abstract: A control system comprises a master processor, a main memory and multiple slave processors. The main memory stores programs, and a signal-program table for storing relationships between the programs and input signals. The multiple slave processors are configured for sending input signals in response to external stimuli to the master processor, and executing programs corresponding to the input signals sent back by the master processor. The master processor is configured for interrogating the signal-program table to determine the corresponding programs according to one of the input signals, searching the main memory for acquiring the corresponding programs, determining which one or more of the multiple slave processors should execute the corresponding programs, and transmitting each of the corresponding programs to the one or more of the multiple slave processors. A related control method is also provided.

Abstract: One embodiment of a video processor includes a first media processing device coupled to a first memory and a second media processing device coupled to a second memory. The second media processing device is coupled to the first media processing device via a scalable bus. A software driver configures the media processing devices to provide video processing functionality. The scalable bus carries video data processed by the second media processing device to the first media processing device where the data is combined with video data processed by the first media processing device to produce a processed video frame. The first media processing device transmits the combined video data to a display device. Each media processing device is configured to process separate portions of the video data, thereby enabling the video processor to process video data more quickly than a single-GPU video processor.

Abstract: According to at least one embodiment, a method comprises detecting loss of lockstep for a pair of processors. The method further comprises triggering, by firmware, an operating system to idle the processors, and recovering, by the firmware, lockstep between the pair of processors. After lockstep is recovered between the pair of processors, the method further comprises triggering, by the firmware, the operating system to recognize the processors as being available for receiving instructions.

Abstract: Methods, apparatus, and products are disclosed for configuring compute nodes of a parallel computer in an operational group into a plurality of independent non-overlapping collective networks, the compute nodes in the operational group connected together for data communications through a global combining network, that include: partitioning the compute nodes in the operational group into a plurality of non-overlapping subgroups; designating one compute node from each of the non-overlapping subgroups as a master node; and assigning, to the compute nodes in each of the non-overlapping subgroups, class routing instructions that organize the compute nodes in that non-overlapping subgroup as a collective network such that the master node is a physical root.

Abstract: A network system by which the processing speed of the entire system can be enhanced. The network system includes a number of information processing apparatus connected to each other through a network such that a process can be executed in a distributed fashion. One of the information processing apparatus is set as a master apparatus while the other information processing apparatus are set as slave apparatus. The master information processing apparatus manages information regarding available hardware resources of the individual information processing apparatus connected to the network as apparatus information and manages communication speeds of the individual information processing apparatus connected to the network. One or more of the information processing apparatus by which the process should be executed are specified based on the management information, and a request for execution of the process is issued to the specified information processing apparatus.

Abstract: Disclosed are various embodiments for arbitration of memory transfers in a digital signal processing system. In one embodiment, a digital signal processing system includes a plurality of DSP's having an external memory. The DSP's are further configurable to act as a master processor and a slave processor relative to another DSP. The system also includes an arbiter configured to maintain DSP status data and arbitrate requests between master processors and slave processors in the system.

Abstract: A system comprises a master processor and at least one slave processor. A state of the master processor comprises a first plurality of variables and a state of the slave processor comprises a second plurality of variables. The system comprises a parallel mode of operation wherein data are processed by the master processor and the slave processor and a serial mode of operation wherein data are processed by the master processor. In case of an interrupt or exception occurring in the parallel mode of operation, the system performs the steps of saving at least a portion of the first plurality of variables and the second plurality of variables to a buffer memory and switching the system to the serial mode of operation. If the interrupt or exception is occurring in the slave processor, at least one of the first plurality of variables is set to a value of at least one of the second plurality of variables.

Abstract: Resolving a Layer 3 address includes maintaining an address resolution table at each slave processor of a number of slave processors. The slave processors have a master processor, and the master processor and the slave processors are associated with a unified address. An address resolution table includes one or more Layer 2-Layer 3 address mappings. An address resolution request requesting a Layer 2 address corresponding to a Layer 3 address is sent from a slave processor. The address resolution request uses the unified address. An address resolution response comprising the Layer 2 address is received at the master processor. The master processor sends the response to the slaves.

Abstract: A computer architecture and programming model for high speed processing over broadband networks are provided. The architecture employs a consistent modular structure, a common computing module and uniform software cells. The common computing module includes a control processor, a plurality of processing units, a plurality of local memories from which the processing units process programs, a direct memory access controller and a shared main memory. A processing system is provided for processing programs and data. The processing system has a processing unit and multiple sub-processing units. Each sub-processing unit includes a dedicated local memory for storing programs and data. The dedicated local memory of each respective sub-processing unit is not a cache memory. In an alternative, multiple computing devices may connect to one another via a communications network, and each computing device may include at least one processing element having the processing unit and sub-processing units.

Abstract: A method, system, apparatus, and computer-readable medium for exchanging data between an application program and a firmware in a computer system having multiple CPUs are provided. According to the method, an application program stores an input parameter for the firmware program in a register of the CPU on which it is executing. Data is also stored in a register of the CPU that identifies the CPU as having generated a SMI. The application program then generates a software SMI. In response to the SMI, a SMM dispatcher executing within the SMM causes the current contents of all the registers of the CPUs to be saved. The SMM dispatcher then identifies the CPU that generated the SMI by searching the saved register contents to locate the data stored by the application program that identifies the CPU as having generated the software SMI. Once the CPU has been identified, the input parameter can be retrieved from the saved register contents for the identified CPU.

Abstract: A method for communicating instructions to slave processors in a multi-processor system having a master processor and pipelined slave processors controlled by the master processor is described. The method uses a pass-through command having (i) a header block coded using a computer language understood by the slave processors and (ii) a payload block including instructions coded in a computer language understood by a destined slave processor. The pass-through command is transmitted to an outermost slave processor and then forwarded, without recoding, by intermediate downstream slave processors until the command reaches the destined slave processor. In one application, the method is used in a system adapted for processing video data or rendering graphics.

Abstract: Configuration management information having circuit configuration information for altering a circuit configuration of an FPGA (12) is stored in a memory (13), the configuration management information according to information related to an instruction group, which is supplied by a configuration management unit (11) from the outside via a signal line group (14), is read from the memory (13), and the circuit configuration of the FPGA (12) is altered according to the read configuration management information to execute processing of the instruction group so that information processing by software is replaced by information processing by hardware in real time, which increases execution speed of information processing and shortens verification time of software, enabling software development in a shorter period and with higher efficiency.

Abstract: A method of processing a volume visualization dataset. Information is transmitted from a resource manager to a task scheduling module regarding the number of processor nodes and amount of storage available in associated storage devices, and sub-tasks instructions including algorithm modules are transmitted from the task scheduling module to a master processor and multiple slave processor nodes. Portions of the volume visualization dataset are transmitted from data storage devices to RAM accessed directly by the master and slave processor nodes. The sub-task instructions and algorithm modules are executed on the individual master and slave processor nodes by accessing directly the portions of the dataset on their respective RAM. Results are transmitted to the master processor node of the slave processor node execution of any sub-task and algorithm module assigned to the slave node. The results are combined at the master processor node and transmitted to the volume visualization application.

Abstract: A processor system includes a main processor having registers and an instruction decode control unit, and a coprocessor. When the main processor performs an operation in accordance with an instruction, the registers store data to be used for the operation and data obtained by the operation, and the control unit sequentially decodes an instruction, and performs a control based on the instruction. When decoding a coprocessor operation instruction to request the coprocessor to perform an operation, which includes operands designating a type of an operation to be performed by the coprocessor, a first register storing data to be used for the operation, and a second register to store data obtained by the operation, the control unit requests the coprocessor to perform the designated type of operation by using a content in the first register, and causes the second register to store a result of the operation.

Abstract: A computing system is provided that has a multiprocessor architecture. The processors are hierarchically organized so that one or more slave processors at a senior hierarchical level provide tasks to one or more slave processors at a junior hierarchical level. Further, the slave processors at the junior hierarchical level will have a different functional capability than the slave processors at the senior hierarchical level, such that the junior slave processors can perform some types of operations better than the senior slave processors. A master computing process distributes operation sets among one or more computing processes running on a processor at the senior hierarchical level, which will begin executing operations in the operation set.

Abstract: A method for dual-processor communication. In one example embodiment, a method includes indicating to a master processor that data is available to transfer to the master processor; receiving a request for the data from the master processor over a storage-based channel; and sending the data to the master processor over the storage-based channel. In another embodiment a method includes determining that data is available for transfer from a slave processor; sending a request for the data to the slave processor over a storage-based channel; and receiving the data from the slave processor over the storage-based channel. In another embodiment a method includes detecting an event on a master processor and writing data corresponding to the event to a slave processor over a storage-based channel.

Abstract: A digital processor in a network ingests encoded media programs and determines conformance with variable test criteria. A storage medium or a network provides the media data as files or as streamed data. Various coding and compression formats can be served at the input or output. A scalable hierarchy of control, media analyst, and user interactive test and display processors share the processing load of decoding, processing and re-encoding media programs or segments for storage and distribution. Processing can include chroma, luma, audio level and other controls, normalizing successive segments to standards, forcing legal variable values, and marking of segments and data changes for optional user review and control using a graphic interface. The interface can display the program image and audio, multiple user selected graphic displays, tabular information including processing criteria and includes the status and queuing of segments that are in process or ready for distribution.

Abstract: A data transmitter includes a bus master circuit. The bus master circuit obtains the right to use a CPU bus and directly performs data transmission to and from a working memory connected to the CPU bus through a CPU interface section and the CPU bus.

Abstract: According to one embodiment, a method comprises system firmware instructing a system's operating system to idle a processor, and responsive to the instructing, the operating system idling the processor and returning control over the processor to the system firmware. According to one embodiment, a method comprises detecting loss of lockstep (LOL) for a processor module in a system, and responsive to the detecting LOL for the processor module, system firmware instructing an operating system to idle the processor module.

Abstract: A stacked device is disclosed which is easily manufactured while identifying a plurality of devices that are stacked in the stacked device. The stacked device includes a stack of a plurality of slave devices and a master device having identical terminal arrangements. Here, the master device includes command transmission unit configured to input an identification command to a terminal of an adjacent slave device.

Abstract: The information processing device includes a plurality of integrated circuits that are interconnected via an external bus. Each of the integrated circuits is structured to be connectable via an internal bus to a CPU, a user logic, and a bridge. One integrated circuit is set as a master integrated circuit, which controls other integrated circuits, and the other integrated circuits are set as slave integrated circuits. CPUs of the slave integrated circuits are set in a reset state. Only the CPU of the master integrated circuit can be boot and it controls the user logic of the slave integrated circuit via the bridge of the slave integrated circuit and the external bus.

Abstract: A system and method for automatically and uniquely assigning identification codes to a plurality of slave processors. A master processor having communication port is linked to a first slave processor, which, itself, has first and second communication ports. The first communication port is used in support of the aforementioned link to the computer. A second slave processor, also having first and second serial ports, is linked by its first communication port to the second communication port of the first slave processor. The slave processors are programmed to read designated pins on their first communication ports. The read values determine the identification code of each processor. Thereafter, each slave processor outputs to its second port a value one greater than the value read from its first port. Therefore, each slave processor assigns itself a particular identification code and directs the next slave processor to assign itself an identification code one greater.

Abstract: In an advanced microcontroller bus architecture (AMBA) system with reduced power consumption, a signal transition is allowed to occur only in loads required for transferring bus signals by isolating loads on a bus signal transfer path requiring the signal transition from the other loads, so that the power consumption can be reduced in a bus architecture such as an advanced high-performance system bus (AHB).

Abstract: The present invention provides system and methods for executing a sequential in parallel. Parallel procedures, specified in the program, are executed as parallel slave processes. A process when actually accessing a ‘synchronous object’ that does not contain the data value same as in program's sequential run gets blocked till the right value is received. Object value transfer takes place through an ownership queue. Synchronization over referred objects along with run-time alterations in the linkage structure of the objects is also supported. In the event of a fault, aborted processes are rescheduled and redundancy in data storage is avoided.

Abstract: A computing system having expansion modules. One of the expansion modules is identified as a master module. The other modules act as slaves to the master module. The central processing unit routes a task to either the master module for portioning out or to all of the expansion modules. The master module then receives completion signals from all of the active slave modules and then provides only one interrupt to the central processing unit for that task.

Abstract: A data-processing circuit includes first and second cooperating processors where one of the processors context switches between applications without running an operating system. In one implementation, the first processor operates under the control of an operating system to switch back and forth between executing a first application or portion thereof and executing a second application or portion thereof. And the second processor operates in a stand-alone mode to switch back and forth between the first application or a portion thereof and the second application or a portion thereof. In another implementation, the first processor runs a single application or portion thereof but no operating system, and the second processor operates in a stand-alone mode to switch back and forth between different applications or different portions of the same or different applications.

Abstract: A multiprocessor system capable of responding to various types of processing to improve the processing efficiency of the entire system. Each of a plurality of processors holds information indicating the program control mode, a VLIW mode or a multithread mode, in a program synchronization flag of a program controller. A master processor, responsible for program control of the entire system, notifies an instruction memory section for storing instructions in a program of updated information when the program synchronization flag information is updated.

Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.

Abstract: The invention relates to a device for acquisition of measurements using a digital communication bus (10) and a computer system. The device includes a bus arbitrator, several items of slave equipment, and two line termination devices. The bus arbitrator (11) is connected to the bus (10), with the function of acting as the bus master. The bus arbitrator synchronizes measurements made using sensors (14). The several items of slave equipment (13) are connected on the bus (10), to which these sensors (14) are connected. The first of the two line termination devices is integrated in the bus arbitrator (11) and the second is integrated into slave equipment (13) at the other end of the bus (10) opposite the bus arbitrator (11).

Abstract: This invention generally relates to one or more computer networks having computers like personal computers or network servers with microprocessors linked by broadband transmission means and having hardware, software, firmware, and other means such that at least one parallel processing operation occurs that involve at least two computers in the network. More particularly, this invention relates to one or more large networks composed of smaller networks and large numbers of computers connected, like the Internet, wherein more than one separate parallel processing operation involving more than one different set of computers occurs simultaneously and wherein ongoing processing linkages can be established between virtually any microprocessors of separate computers connected to the network.

Abstract: Apparatus and methods for controlling a system that operates responsive to a plurality of input control signals are disclosed. During operation the system generates a plurality of output status/control signals. A master controller has at least first and second controllers. The first controller outputs and inputs signals over a first communication path, and the second controller outputs and inputs signals over a second communication path. The first and second controllers output signals based on input signals received over the first and second communication paths, respectively, and also based on stored control data. A plurality of input/output modules are provided. Each of the input/output modules has first and second slave controllers. The first slave controller of each of the input/output modules inputs and outputs signals over the first communication path to the first controller, and the second slave controller outputs and inputs signals over the second communication path.

Abstract: The invention relates to an information processing device (1), including a user control unit (2) for the selection of units of primary information to be processed and functions to be invoked. The device also includes storage means (3) for storing the primary information. From the selections made by the user the device derives personalizing information concerning the use of the device and the primary information processed with the device. The personalizing information is stored separately and represents a history of the usage of the device, thus making the device more personalized to its owner.

Abstract: A computer system has a node and a service processor (SVP) connected together via a diagnosis section. An input/output (I/O) unit is connected to the SVP. The diagnosis section has a serial controller. The SVP writes data to be transmitted to the node from the I/O unit into the serial controller. The node reads data stored in the serial controller. The node also writes data to be transmitted to the I/O unit into the serial controller. The serial controller instructs the SVP to read the data written by the node. The SVP reads this data and sends it to the I/O unit.