Abstract: A computer system has a node and a service processor (SVP) connected together via a diagnosis section. An input/output (I/O) unit is connected to the SVP. The diagnosis section has a serial controller. The SVP writes data to be transmitted to the node from the I/O unit into the serial controller. The node reads data stored in the serial controller. The node also writes data to be transmitted to the I/O unit into the serial controller. The serial controller instructs the SVP to read the data written by the node. The SVP reads this data and sends it to the I/O unit.

Abstract: A data processing system comprises a master processor (10), a slave processor (30), a memory (50), and a bus subsystem (20) interconnecting the master processor (10), the slave processor (30), and the memory (50). The master processor (10) is configured to generate, in response to a memory access instruction, a read request comprising a read command for execution by the slave processor (30) to read data stored in a location in the memory (50) specified by the memory access instruction, and to write the read request to the slave processor (30) via the bus subsystem (20). The slave processor (30) is configured to execute the read command received in the read request from the master processor (10) to obtain the data stored at the specified location in the memory (50) and to write the data thus obtained to the master processor (10) via the bus subsystem (20).

Abstract: A method of providing reset logic in high availability computer systems is disclosed. The illustrative embodiment of the present invention uses probability theory in combination with redundant processors and components to ensure system availability. Detected errors are verified, and malfunctioning processors or components are then changed to a reset state that functionally removes them from the system. Detected errors which can not be verified result in the processor or component that incorrectly detected the error being placed in a reset state. The use of redundant components and processors enable standby processors to be activated to take the place of reset processors quickly enough to maintain system availability.

Abstract: A design and method of using a group write slave and a sequence alignment logic module including an identification stage, the identification stage having a first ID input, a second ID input, an ID AND gate, and an ID comparator, a select stage, the select stage having a first select input port, a group write comparator, an individual select comparator, an OR gate and a select AND gate, a Slave Module, wherein the Slave Module includes a group wait signal and a group rearbitrate signal and a sequence alignment logic module which includes a gated logic portion having logic circuitry constructed so as to create a sequence alignment logic module output signal by sequencing and combining the plurality of sequence alignment logic module input signals so as to represent the slowest of the sequence alignment logic module input signals.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: A communication protocol processing unit by a multiprocessor is disclosed, and includes a first processor for performing a process demanding a real time property on a stream of communication data; and a second processor for performing a process not demanding the real time property, wherein the first processor transfers using parameters paired with the communication data to be processed to the second processor, and the second processor is structured so as to refer to the transferred communication data and parameters to process.

Abstract: A system and method for synchronizing image display and buffer swapping in a multiple processor-multiple display environment. In a master-slave dichotomy, one processor or system is deemed the master and the others act as slaves. The master generates signals used to control vertical retrace and buffer swapping for itself and the slaves. In addition, a synchronization signal generator is provided to synchronize a timing signal between the master and slave systems.

Abstract: A system for collecting events relating to multiple distributed physical systems includes multiple event collection cards (100), each receiving events from one of the distributed physical systems. Each event collection card includes a time stamp clock (120) configured to provide a time stamp when each event is received, an event memory (110) configured to store the received events, a sync interface unit (130) configured to receive a sync signal, a sync control unit (125) configured to synchronize the time stamp clock (120) to the sync signal received by the sync interface (130), and a collection control unit (115) configured to time stamp the collected events according to the time stamp clock (120) synchronized to the sync signal, and to store the time stamped events in the event memory (110).

Abstract: A shared memory type vector processing system in which CPUs are connected by a bus for transferring a vector processing instruction generated from any of the CPUs to each of the CPUs, and the respective CPUs are grouped into a master CPU which issues a vector processing instruction to other CPUs and slave CPUs operating as a multi-vector pipeline in synchronization with a vector processing unit in the master CPU, the master CPU including a memory access control unit for issuing said vector processing instruction with issuing source CPU information attached for identifying an issuing source CPU, and transferring said instruction to all the CPUs including its own CPU through a bus, and the master CPU and the slave CPU including a vector processing instruction control unit for comparing issuing source CPU information contained in a vector processing instruction and master CPU information set at its own CPU and conducting instruction issuance based on the vector processing instruction when the information accord

Abstract: A USB device centric agent is associated with an operating system. The agent software is only required to be loaded once and then it will function with multiple compatible USB devices. A standard interface is established between the device agent and any compatible USB device. This enables any compatible USB device to control the agent which in turn controls the host computer. This is opposite the standard practice where the host controls the USB device.

Abstract: A system and method for automatically and uniquely assigning identification codes to a plurality of slave processors. A master processor having communication port is linked to a first slave processor, which, itself, has first and second communication ports. The first communication port is used in support of the aforementioned link to the computer. A second slave processor, also having first and second serial ports, is linked by its first communication port to the second communication port of the first slave processor. The slave processors are programmed to read designated pins on their first communication ports. The read values determine the identification code of each processor. Thereafter, each slave processor outputs to its second port a value one greater than the value read from its first port. Therefore, each slave processor assigns itself a particular identification code and directs the next slave processor to assign itself an identification code one greater.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A telecommunications data conferencing platform has a secure zone and a partly secure zone connected by a secure firewall. The secure zone contains a master data server, a billing system a reservation system and an audio bridge connected to the firewall. The partly secure zone contains a pair of slave data servers. The first slave data server can be connected through a public firewall to the public Internet. The first slave data server can receive incoming calls from the public switched telecommunications network via a bank of modems. The secure firewall restricts the passage of messages from the partly secure zone to the secure zone to messages which originate directly in the partly secure zone but allows the passage of conference data. Thus, unauthorised parties are unable to gain access to the reservation system or the master data server. In order to establish a conference, the reservation system creates a conference on the master data server.

Abstract: An apparatus comprising one or more first processors and one or more second processors. The one or more first processors may each comprise a first random access memory (RAM) sections. The one or more second processors may each comprise a read only memory (ROM) section and a second RAM section. The one or more first processors may be configured to operate in either (i) a first mode that executes code stored in the one or more ROM sections or (ii) a second mode that processes code stored in the one or more first RAM sections. The one or more second processors may be configured to execute code from either (i) the one or more ROM sections or (ii) the one or more second RAM sections. The apparatus may provide interoperability that may increase system observability and decrease system debugging complexity.

Abstract: A Virtual Server Farm (VSF) is created out of a wide scale computing fabric (“Computing Grid”) which is physically constructed once and then logically divided up into VSFs for various organizations on demand. Allocation and control of the elements in the VSF is performed by a control plane connected to all computing, networking, and storage elements in the computing grid through special control ports. The control plane is comprised of a control mechanism hierarchy that includes one or more master control process mechanisms communicatively coupled to one or more slave control process mechanisms. The one or more master control process mechanisms instruct the slave control process mechanisms to establish VSFs by selecting subsets of processing and storage resources.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute multiple threads in parallel very efficiently. Generally, the operating system is responsible for scheduling various threads of execution among the available processors in a multiprocessor system. One problem with parallel multithreading is that the overhead involved in scheduling the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreading. Consequently, potential performance gains from parallel multithreading are not attainable. Additional circuitry is included in a form of symmetrical multiprocessing system which enables the scheduling and speculative execution of multiple threads on multiple processors without the involvement and inherent overhead of the operating system.

Abstract: The present invention provides a processor device and technique having the capability of providing a two-processor solution with only one processor. In accordance with the principles of the present invention, a host processor is programmed in its native source and machine code language, and an emulated second processor is programmed in a different native source or machine code language particular to that emulated processor, to allow programming specialists in the different processors to develop common code for use on the same host processor. A multitasking operating system is included to allow time sharing operation between instructions from program code relating to the host processor (e.g., a DSP in the disclosed embodiment), and different program code relating to the emulated processor. The program code relating to the host processor (e.g., DSP) is written in program code which is native to the DSP, while the program code relating to the emulated processor (e.g.

Abstract: The present invention relates to a method for providing a master-slave hot-swapping apparatus and mechanism for use with an ATA bus. A bus controller and a bus separator are employed for isolating the hot-swapping apparatus and the host system, and a power supply switch is used.

Abstract: A multiprocessor system of a distributed shared memory structure has a hot plug function for main memories. Each of nodes of the multiprocessor system has a processor, an IO unit, a main memory, a mover, and a routing control unit. If a memory read access request is issued from the processor, the IO unit, or the mover to the main memory of a master node, the routing control unit instructs the master node to transfer the memory read access request. If a memory write access request is issued from the processor, the IO unit, or the mover to the main memory of the master node, the routing control unit instructs both the master node and a slave node to transfer the memory write access request when in a multicasting mode, and instructs only the master node to transfer the memory write access request when not in the multicasting mode.

Abstract: According to one embodiment, a graphics/video processor includes a memory controller. The memory controller includes a first arbiter that receives memory client requests to access a memory device, and a first memory buffer coupled to the first arbiter. The first arbiter stores client requests that are selected by the first arbiter. The memory controller also includes a second arbiter coupled to the first memory buffer and a second memory buffer coupled to the second arbiter. The second arbiter receives requests from the memory client requests stored in the first memory buffer. The second memory buffer stores the client requests selected by the second arbiter. Further, the memory controller includes a third arbiter coupled to the second memory buffer. The third arbiter provides access of the memory device to the client requests stored in the second memory buffer.

Abstract: A system, such as an AMBA based system, wherein an interrupt controller is coupled directly to a processor, thereby providing that the processor can access the interrupt controller without having to access a system bus. Specifically, the interrupt controller may be coupled to a port of the processor, such as a tightly coupled memory (TCM) port or a coprocessor port of the processor. The interrupt controller may be coupled to the TCM port along with SRAM.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus. In response to the active signal on the address increment disable line, the bus master inhibits changing the address for the duration of the data transfer. The module also drives an active signal on an expansion address off boundary line in the control bus when an internal expansion address of the module is not aligned with a natural boundary of a data bus of the internal communication bus to allow the bus master to adjust the width of the data transfer.

Abstract: The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.

Abstract: A pipeline operation method and a pipeline operation device in which an operation result of an operation unit can be effectively written to a register. In the pipeline operation method and the pipeline operation device, a pipeline operation unit that can perform a pipeline operation, a non-pipeline operation unit that cannot perform a pipeline operation, and a register that is shared by the pipeline operation unit and the non-pipeline operation unit are arranged. To perform an operation while an operation result of each of the pipeline units is being written into the register, translating an instruction to the pipeline operation unit is interlocked when the writing of the operation result of the pipeline operation unit overlaps with the writing of the operation result of the non-pipeline operation unit.

Abstract: A single integrated circuit chip interfaces device control circuitry of a device to a client machine via a computer network. The chip comprises an internal data bus; a central processing unit connected to the internal data bus; an internal memory connected to the internal data bus; a device interface connected to the internal data bus, wherein the device interface comprises circuit blocks for communicating digital information between the integrated circuit and the device control circuitry; and a network interface connected to the internal data bus, wherein the network interface comprises circuit blocks for communicating digital information between the integrated circuit and the computer network.

Abstract: A buffer cache management structure, or metadata, for a computer system such as a NUMA (non-uniform memory access) machine, wherein physical main memory is distributed and shared among separate memories. The memories reside on separate nodes that are connected by a system interconnect. The buffer cache metadata is partitioned into portions that each include a set of one or more management data structures such as hash queues that keep track of disk blocks cached in the buffer cache. Each set of management data structures is stored entirely within one memory. A first process performs operations on the buffer cache metadata by determining, from an attribute of a data block requested by the process, in which memory a portion of the metadata associated with the data block is stored. The process then determines if the memory containing the metadata portion is local to the process. If so, the first process performs the operation.

Abstract: A distributed computer system having centrally available processing units. A plurality of computer workstations are connected to a plurality of processing units by computer transmission cables. In one embodiment each of the workstations may be connected to any of the plurality of processing units. These connections are accomplished by a switching unit controlled by a management computer where the management computer automatically connects and disconnects individual computer workstations to individual processing units. In a typical embodiment, there are more computer workstations then processing units and the management computer disconnects idle computer workstations from processing units and connects previously idle computer workstations that become active to processing units not then connected to another computer workstation. A portion of a video display adapter is included in computer workstations while a second portion of a video display adapter is included in the processing units.

Abstract: General purpose parallel computer, latency reduction MIMD, with multiple processors, and multiple memory address spaces, wherein processors (SPU) are redundantly replicated on each memory (M) bus (C-BUS) and, formed/connected as either master-active or slave-active of the bus and to interface a suitable communication structure (A-S) for transferring among themselves the process context and the bus control, in such a way to execute in turn a unique migrant sequential process per bus (C-BUS), and wherein each processor is also directly and tightly coupled with devoted private buses (P-P) to one corresponding processor of another one bus (C-BUS) in a way to form, between distinct buses (C-BUS), biprocessor pairs (DPU) capable of allowing communication and synchronization of the parallel migrant processes.

Abstract: Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subdivided by software into multiple partitions, each with the ability to run a distinct copy, or instance, of an operating system. At different times, different operating system instances may be loaded on a given partition. Resources, such as CPUs and memory, can be dynamically assigned to different partitions and used by instances of operating systems running within the machine by modifying the configuration. The partitions themselves can also be changed without rebooting the system by modifying the configuration tree. Each instance keeps track of the CPUs in the system and their respective operational statuses relative to the instance, such as compatibility with the instance, control by the instance, and availability to the instance for SMP processing.

Abstract: A DSP coprocessor 2 is connected to a host sub-system (3). The host sub-system (3) has a host processor (4), a host RAM (5), and shared RAM banks (6, 7). Multiplexers (11) provide access for either the DSP or the host to a shared RAM bank. Macro commands for functions of the DSP coprocessor are retrieved from the shared RAM banks. This allows comprehensive interaction of the host and the DSP coprocessor.

Abstract: A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.

Abstract: Shadow arrays are configured in a distributed memory multiprocessor architecture to localize memory referencing. As each additional processor becomes active a variable array having dimensions 1×N, including N single instance variables which must be monitored on a “per processor” basis, is configured in a memory local to the additional processor and made locally referenceable. A patchwork of shadow arrays is thereby established in which each additional processor may reference local memory to access its own value set for the N single instance variables. The single instance formatting of the arrays also advantageously facilitates migration from an single processor operating system to a multiprocessor operating system without substantial recoding.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A system and method for handling system management interrupts in a multi-processor computer is disclosed. When the computer enters system management mode, the method uses the registers of each processor to get currently executing opcode to determine what each processor was doing before the interrupt. The method may have to first translate address information to locate the actual physical location of the currently executing opcode. The registers are stored in memory and the contents of the registers can be used to determine if the current processor caused the system management interrupt. If so, then the method now knows which processor caused the interrupt and can handle the interrupt accordingly. If, however, the processor was not the one that caused the interrupt, or if another processor also caused an interrupt, the method then repeats the above steps for the next processor of the multiprocessor system.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: The communications system operates at two distinct operating modes. Each of the slave stations, which are controlled by a master station, has a first output circuit and a second output circuit. The two output circuits are connected to one another on the output side. In a first operating mode, the slave stations are identified by the master station, all the first output circuits can be activated and the system operates at a low clock rate. In a second operating mode, a transfer of data takes place, one of the second output circuits can be activated, and the system operates at a higher clock rate.

Abstract: In a distributed network of processors, a method for completing update transactions using update transaction timers after failure of one processor. Failed slave processors are updated with other slave processors using a record of the last completed database update transaction at each processor prior to failure and using a journal in the master processor that records steps of database update transactions generated by the master database processor.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: A source module, a destination module, or both modules, that are used in a data transfer, signal over an internal communication bus to a bus master when additional time is needed to participate in the data transfer. If either the source module, destination module or both modules require more time, the bus master, in response to an active stretch bus access signal or signals for the module or modules, automatically extends the bus access cycle until all modules requiring additional time signal over the internal communication bus that they are ready to proceed with the data transfer. Consequently, the source module, destination module, or both modules can re-time a bus access cycle to accommodate the characteristics of that particular module. When the addressed storage location in the data transfer comprises a single point address type memory, the addressed module drives an active signal on an address increment disable line in the control bus.

Abstract: A system of the present invention uses small swing differential source synchronous voltage and timing reference (SSVTR and /SSVTR) signals to compare single-ended signals of the same slew rate generated at the same time from the same integrated circuit for high frequency signaling. The SSVTR and /SSVTR signals toggle every time the valid signals are driven by the transmitting integrated circuit. Each signal receiver includes two comparators, one for comparing the signal against SSVTR and the other for comparing the signal against /SSVTR. A present signal binary value determines which comparator is coupled to the receiver output, optionally by using XOR logic with SSVTR and /SSVTR. The coupled comparator in the receiver detects whether change in signal binary value occurred or not until SSVTR and /SSVTR have changed their binary value. The same comparator is coupled if the signal transitions. The comparator is de-coupled if no transition occurs.

Abstract: A protocol and internal link system of a micro-controller in which components, interconnected by a parallel BUS link, exchange during a transaction successive messages on a plurality of clock cycles. A master transmitting component transmits, on a current clock cycle, to an addressee slave receiver component, an instruction message, encoded on N+p bits, and comprising a main field, N bits, and an auxiliary field, p bits, comprising an operation code, a signature identifying master and slave component and their transaction. A proof of transmission message and an acknowledgement message are transmitted from the master component to the slave component and vice versa on the following clock cycle. These steps are repeated on at least one subsequent clock cycle.

Abstract: A direct access storage device (DASD) controller system for serves computer elements such as processors and disk arrays through a serial interconnect scheme. The system includes a plurality of adapters belonging to either a first set or a second set. Cache memory is divided into master memory cards and slave memory cards, each slave memory card in communication with a corresponding master memory card. A plurality of bidirectional multichannel serial data links connects one adapter with one memory card such that every adapter in the first set of adapters is connected to every master memory card and such that every adapter in the second set of adapters is connected to every slave memory card.

Abstract: A multiple processor circuit arrangement utilizes a master processor which controls the operational state of a slave processor by programming internal control registers on the slave processor. In addition, a stack-based processor utilizes a stack cache for accelerating stack access operations and thereby accelerating the overall performance of the processor. When the stack-based processor is utilized as a slave processor in the aforementioned master/slave multi-processor computer system the slave processor is optimized to process platform-independent program code such as Java bytecodes, thereby permitting fast and efficient execution of both program code native to the master processor as well as platform-independent program code that is in effect native to the slave processor.

Abstract: A process and system for transferring data including at least one slave device connected to at least one master device through an arbiter device. The master and slave devices are connected by a single address bus, a write data bus and a read data bus. The arbiter device receives requests for data transfers from the master devices and selectively transmits the requests to the slave devices. The master devices and the slave devices are further connected by a plurality of transfer qualifier signals which may specify predetermined characteristics of the requested data transfers. Control signals are also communicated between the arbiter device and the slave devices to allow appropriate slave devices to latch addresses of requested second transfers during the pendency of current or primary data transfers so as to obviate an address transfer latency typically required for the second transfer.

Abstract: To improve the efficiency of delayed transactions in bus-to-bus bridge systems which include at least one interface to a PCI bus, a bridge system is disclosed including at least a primary interface and an interface to a secondary subsystem for interconnecting a primary PCI bus system and the secondary subsystem. The system comprises a delayed transaction mechanism for enabling a transaction source attached to the primary PCI bus system to effect delayed transactions with a target in the secondary subsystem. This system has a programmable delay transaction timer which provides a degree of flexibility in the configuration of PCI systems. This flexibility can be exploited to provide considerable efficiency gains, albeit at the expense of some deviation of the strict requirements of the PCI Specification.

Abstract: For the obtainment of a unique number identifier called a ticket indentifying a task or an event in a multi-node data processing system (SYS), a master node (Ny) for distributing the ticket in the system is designated, and it includes a ticket generator (TICKy:VALy, SESSy, COUNTy) whose address (TICK.sub.-- ID) is stored in a reference register (REF) of each node. When a node (Nx) requests a ticket, it reads the address (TICK.sub.-- ID) in this register and thus accesses the ticket generator of the master node (Ny). A backup or substitute node (Ns) can replace the master node (Ny) in case of a failure (TICK-MISS).

Abstract: The mapping of playing objects from one game to another. In one embodiment, generic attributes of an object may be mapped to game-specific attributes. The mapping may either change or maintain the look and feel of an object. For example, a fast but lightly-armed starship in one game may be mapped to a quick but weak warrior in another game.

Abstract: A multiprocessor architectural definition provides that a program executing on a first processor interrupts a second processor by executing a software interrupt instruction. The software interrupt instruction includes an argument field for passing information from a program requesting the software interrupt. The argument, along with the opcode, is saved in a register designated for holding the argument. The information communicated via the argument is used in one embodiment to indicate a cause of the interrupt. In an embodiment, the information communicated via the argument designates an interrupt service routine to be activated in the interrupted processor.