Abstract: A device for processing digital data receives digital data with a number of original digital data being reduced in a predetermined manner, discriminates whether a predetermined reference part of the received digital data meets a predetermined condition, sets a value corresponding to a remaining part of the received digital data, and modifies the value in a predetermined way if the reference part meets the predetermined condition.

Abstract: A scalable computer system has an interconnect bus providing communication links among a host processor and one or more function-specific processors, including a network processor (NP) and a file storage processor (FSP). The host processor provides a single interface to network administrators for maintaining the system. A bi-endian conversion system is provided to minimize a need for translating between big and little endian data types generated by diverse processors. The NP shares a single memory image with other processors and has a buffer memory for buffering requests from the network interfaces. The buffer memory has one or more segments which are dynamically allocatable to different processors. The FSP has a metadata cache for maintaining information on data being cached in the NP buffer memory. The FSP also has a write cache for buffering file write operations directed at disks.

Abstract: A microcomputer includes an analog-to-digital (AD) converter which converts analog data into digital data and then stores a plurality of data bits which represent the digital data, a read signal output unit for producing a read signal for identifying the value of the digital data stored in the AD converter, a gate circuit which, in response to the read signal from the read signal output unit, obtains a plurality of data bits at the uppermost or lowermost end of the digital data from the digital data stored in the AD converter, a skip circuit which, in response to the read signal, obtains remaining data bits, other than the plurality of data bits obtained by the gate unit, from the digital data stored in the AD converter and produces a control signal having a second value which differs according to the value of the remaining data bits and a data identifying unit which identifies the value of the digital data on the basis of the plurality of data bits supplied by the gate unit and by the control signal.

Abstract: An information processing apparatus including a Global Positioning System (GPS) receiver for receiving a radio wave from a GPS satellite and a Reduced Instruction Set Computer (RISC) type microprocessor for processing signals corresponding to the radio wave received by the GPS receiver. The GPS receiver and RISC type microprocessor are incorporated into a single integrated circuit chip, and the RISC type microprocessor is provided with a bypass circuit which facilitates the execution of conditional branch instructions.

Abstract: An audio information processing subsystem 200 is disclosed which includes a stream processor 100 for simultaneously processing multiple streams of audio data. Processing subsystem 200 also includes a program memory 202 coupled to stream processor 100 for storing instructions for controlling processing system 200 and a data memory 203/204 also coupled to stream processor 100. Additionally, a direct memory access circuitry 208 is provided for controlling direct memory accesses to a selected one of program memory 202 and data memory 203/204.

Abstract: A system for compiling a computer program to implement parallel image processing on a computer having a plurality of arithmetic processors. The program is analyzed to determine whether it contains a parallel image processing identifier, and if so, a plurality of parallel image processing execution codes are generated for use by the arithmetic processors. Thereby, allowing image processing to be conducted at an increased speed.

Abstract: A virtual network consists of many distributed virtual computers interconnected over a communication network of individual links, such as optical fibers or electrical conductors, for example. Each distributed virtual computer has at least two ports connected over respective links to other respective distributed virtual computers on the network. Each distributed virtual computer is connected to or resident within its own host, each host typically being a conventional computer such as a personal computer or a work station, for example, although at least one of the hosts may itself be another virtual computer. Each distributed virtual computer has reconfigurable logic elements such as an FPGA or an array of FPGAs.

Abstract: A special purpose reduced instruction set central processing unit (RISC CPU) for controlling digital audio/video decoding. The instruction set includes flow control instructions which incorporate immediate values, used to jump over a small number of instructions, and other instructions used for larger jumps. Also, instructions obtain data from the video decoder of the ASIC in a streamlined fashion, using video decoder addresses hard-coded into the RISC CPU. Further instructions perform manipulations of individual bits of registers used as state/status flags. The RISC CPU includes watchdog functions for monitoring the delivery of data to the RISC CPU from other functional units or from memory, so that the RISC CPU can execute instructions while delivery of data from memory or other functional units is pending, unless that data is necessary for program execution, in which case, program execution stalls until the data arrives.

Abstract: A processor that includes hardware resources for the operating system that are separate and independent from resources dedicated to user programs. The OS resources preferably include a separate OS arithmetic logic unit (OS/ALU) along with a dedicated instruction buffer, instruction cache and data cache. The OS/ALU is preferably able to control the registers and program address of user processes, and can read a program request register from the user program.

Abstract: An arithmetic logic unit capable of executing an instruction belonging to a user-defined instruction area at the same clock frequency as a hard-wired logic includes a memory storing data at an arbitrary address and outputting the data stored in the address when an instruction code and an operand data are applied as an address. When an instruction decoder decoding part of the instruction code for setting the memory to read mode or write mode is provided, contents of the memory can be re-written, and therefore the content of the memory can be readily changed even after delivery. The arithmetic logic unit may include, in place of the memory, a programmable logic device adapted to receive an instruction code and the operand data and capable of organizing a desired logic.

Abstract: Protocol processor intended to be associated with at least one main processor of a system with a view to the execution of tasks to which the main processor is not suited. The protocol processor comprises a program part (30) including an incrementation register (31), a program memory (33) connected to the incrementation register (31) in order to receive addresses thereof, a decoding part (35) intended to receive instructions from the program memory (33) of the program part (30) with a view to executing an instruction in two cycles, and a data part (36) for executing the instruction.

Abstract: An improved PC system that includes a main CPU microprocessor, a file-based operating system, and a DSP microprocessor arranged so that the DSP can execute main CPU operations during time intervals in which the main CPU is otherwise occupied, thereby increasing the bandwidth of the system is provided. This PC system may include multiple CPUs and/or multiple DSPs.

Abstract: A processor having a modified Harvard architecture having first and second memories, an address register file divided into first and second sets of registers, first and second stream registers, and a general purpose register file for performing data streaming. The first and second sets of registers respectively address the first and second memories which, in turn, load data into the first and second stream registers. An arithmetic logic unit (ALU) accepts the stream registers and general purpose registers as inputs. Stream instructions are encoded such that a single instruction specifies an ALU operation performed on selected ALU inputs and where to store the results of the ALU operation, loads new values into the stream registers, and updates the address registers. A stream instruction has three operand fields respectively specifying two operands for the next ALU operation and a location to store the result of the current ALU operation.

Abstract: A digital signal processing device (e.g., DSP), employed by electronic musical instruments and the like, is designed to perform a variety of digital signal processings. The digital signal processing device contains an arithmetic unit which is configured by at least an adder and a multiplier. There are provided first and second microprograms, each of which consists of microinstructions and each of which is designed to perform a specific kind of digital signal processing. The first and second microprograms are alternatively selected in accordance with a preset sequence of processing; and consequently, data supplied to the arithmetic unit are changed in response to the microprogram selected. Thus, the arithmetic unit performs arithmetical operations, using the data selectively supplied thereto, in accordance with the microprogram selected. By changing the sequence of processing, it is possible to easily change a manner of digital computing performed by the digital signal processing device.

Abstract: In accordance with the present invention, an FPGA input/output buffer including at least two registers is provided. A first register provides the FPGA output through a tristate buffer to the pad or pin. A second register controls the state of the tristate buffer. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the second register and for loading data into the first register.

Abstract: A device for incorporation into a variety of consumer appliances for use in a home automation environment. The invention comprises an electronic hardware module having software resident on the module, providing an interface between an appliance and other elements on a communications system employing the "Consumer Electronics Bus" protocol. The present invention interprets data messages sent to the appliance and signals the appliance in a preprogrammed manner. Also, the invention can be programmed to generate a specific data message for transmission to another appliance. The invention accommodates the various communication media, levels of electrical noise, and operating speeds allowed by the "Consumer Electronics Bus" protocol.

Abstract: The present invention relates to a system and a method for data processing and a communications system controlled by such a system. The system comprises at least one central processor, a number of different function blocks and a common data memory (DS), At least one function is table executed in parallel with program execution by an execution processor (IPU) wherein the data memory (DS) either is used for program execution or for table execution wherein one or the other type of the execution has precedence and is able to interrupt an on-going execution of the other type.