Abstract: The present invention generally relates to a method, system and program product for distributing portal content processing. Specifically, a request for portal content is received on a surrogate system and then passed to a portal system. The portal system will obtain and aggregate a first type of the requested content, and then package the aggregated content into a response. The response will also include place holders that correspond to the remaining type of the requested content. The response will then be transmitted to the surrogate system, which will, based upon the place holders, obtain the remaining type of portal content. Once obtained, the remaining type of portal content will replace the place holders in the response, and the response will be rendered for the requesting portal user.

Abstract: A digital signal processing unit includes a control unit and a data computing unit. An R/L register for distinguishing independent data is disposed in the control unit. An R/L select signal for indicating independent data is supplied to the data computing unit. A data processing instruction signal for distinguishing a data processing instruction from other instructions is issued from an instruction decoder. The R/L register for distinguishing independent data is controlled by the data processing instruction signal. In the data computing unit, the portion related to storing independent data is multiplexed according to the number of independent data to be processed, and this multiplexed portion is controlled by the R/L select signal supplied from the control unit.

Abstract: A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of circuit parameters to execute one or more iterations of a computation specified by a streaming data flow graph. The candidate streaming processor circuit is evaluated with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output if the candidate streaming processor circuit satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate streaming processor circuits.

Abstract: A method for prototyping an integrated circuit may include selecting at least one daughter card for connection to a motherboard. The daughter card is selected having an ability to provide functionality corresponding to a specific integrated circuit device. The at least one daughter card is connected to the motherboard so that the daughter card is communicatively connected to common memory provided on the motherboard. The at least one daughter card and motherboard emulate an integrated circuit design. At least one of software and system integration of the integrated circuit emulated by the motherboard and the at least one daughter card is tested.

Abstract: Provides methods, systems and apparatus for coupling a general purpose processor (GPP) to an application specific instruction set processor (ASIP) in such a manner that the GPP can include execute instructions that do not normally comprise part of its instruction set architecture (ISA). The GPP is coupled to the ASIP via a coprocessor port such that instructions issued by the GPP to the port are conveyed to a novel pre-decoder module of the ASIP. The pre-decoder module translates the GPP instruction into operation codes for ASIP instructions to be executed in the ASIP or to an address in the ASIP instruction memory that identifies a start address for a plurality of ASIP instructions defining a complex application specific function. Once the ASIP has executed the instructions it shares the result of the execution with the GPP. In this way, the GPP takes advantage of the ASIP in its ability to more quickly execute an application specific program/procedure.

Abstract: A video processing system with reconfigurable instructions includes a processor, a first register file in the processor, an extension adapter, programmable logic, a second register file coupled to the programmable logic, and a load/store module. The processor executes a video application that contains an instruction extension not native to the instruction set of the processor. The extension adapter detects the instruction extension in the video application. The programmable logic device is configured to execute the instruction extension. The programmable logic device then executes the instruction extension. The load/store module transfers data between the first register file and the second register file, and transfers data directly between the second register file and a system memory for use by the processor in processing the video application.

Abstract: An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.

Abstract: A microprocessor circuit includes a control unit, a memory for free programming with at least one program having functions, a stack for buffer-storing data, a register bank having at least one register, and an auxiliary register that stores a number of bits, each of the bits being assigned to one of the registers of the register bank and indicating whether or not a respective register of the register bank contains information items.

Abstract: A reconfigurable processor calculates execution times of configuration for executing pipeline processing from hardware configuration information, and fixes a clock cycle until processing ends. A counter compares the fixed clock cycle with the actual number of elapsed clocks, and, when the number of elapsed clocks equals the clock cycle, it is determined that pipeline processing has ended, and a configuration controller is notified of this.

Abstract: An integrated circuit device with a data processing block is provided, the data processing block including a plurality of operation units that are arranged in a matrix, a plurality of first wire sets that extend in a first direction in the matrix and transfer input data of each operation unit, a plurality of second wire sets that extend in a second direction in the matrix and transfer output data of each operation unit, and a plurality of switching units that are arranged at each intersection between the first and second wire sets and can select and connect any wire in the first wire sets and any wire in the second wire sets. The plurality of operation units include a plurality of types of operation units with different data paths that are suited to special-purpose, processing, with an arrangement of operation units of the same type in the first direction or the second direction being formed in at least part of the data processing block.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network.

Abstract: The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a computer system containing standard instruction processors, as well as reconfigurable processors. The interface includes a command processor, a command list memory, various registers, a direct memory access engine, a translation look-aside buffer, a dedicated section of common memory, and a dedicated memory. The interface is controlled via commands from a command list that is created during compilation of a user application, or various direct commands.

Abstract: The present invention describes a method and system for an interface for integrating reconfigurable processors into a general purpose computing system. In particular, the system resides in a computer system containing standard instruction processors, as well as reconfigurable processors. The interface includes a command processor, a command list memory, various registers, a direct memory access engine, a translation look-aside buffer, a dedicated section of common memory, and a dedicated memory. The interface is controlled via commands from a command list that is created during compilation of a user application, or various direct commands.

Abstract: Electronic devices, and methods, for transmitting, transferring and/or conveying a multi-bit digital signal as a voltage signal via a single pin. Devices and methods according to the invention substantially reduce the pin count of a device because inputting of a multi-bit digital signal preferably does not use more than one input pin. In addition, the speed of transmission is improved because the multi-bit digital signal is transmitted as a voltage signal substantially at one time as opposed to serially.

Abstract: A data-processing system includes a data device for selectively storing data and an engine having access to the memory device, the engine supporting a plurality of machine executable programs. A controller is utilized which selectively outputs one of a plurality of instructions to the engine for driving the execution of the programs enabled by the engine, while a clock device is utilized for outputting a synchronizing clock signal comprised of a predetermined number of clock cycles per second. The clock device outputs the synchronizing clock signal to the data device, the engine and the controller. The controller outputs one of the instructions to the engine for execution of one of the programs, while also executing an operation within itself, all within a single clock cycle.

Abstract: A host system is provided with one or more host-fabric adapters installed therein for connecting to a switched fabric of a data network.

Abstract: An integrated circuit (203) for use in processing streams of data generally and streams of packets in particular. The integrated circuit (203) includes a number of packet processors (307, 313, 303), a table look up engine (301), a queue management engine (305) and a buffer management engine (315). The packet processors (307, 313, 303) include a receive processor (421), a transmit processor (427) and a risc core processor (401), all of which are programmable. The receive processor (421) and the core processor (401) cooperate to receive and route packets being received and the core processor (401) and the transmit processor (427) cooperate to transmit packets. Routing is done by using information from the table look up engine (301) to determine a queue (215) in the queue management engine (305) which is to receive a descriptor (217) describing the received packet's payload.

Abstract: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

Abstract: Method and apparatus for switching between multiple implementations of a routine. A plurality of implementations of a routine are compiled into respective object code modules. In one embodiment, each implementation of the routine is adapted for a particular hardware configuration. The different object code modules are associated with respective sets of hardware characteristics and with the name of the routine. When the application program and library are loaded into memory of the computer system, a references to the routine are resolved using the sets of hardware characteristics and the hardware configuration of the system.

Abstract: Programmable on-chip identification circuitry and associated method are disclosed that provide integrated circuits with the ability to select and report from multiple different vendor and system identification configurations. The integrated circuit device includes programmable circuitry that utilizes vendor identification, system identification, configuration or other device information provided or selected at least in part based upon selection information from a source external to the integrated circuit. The selection information may be provided through one or more externally generated digital and/or analog control signals that are then processed within the integrated circuit device to select, access and utilize desired identification information stored in an on-chip database.

Abstract: The present invention provides for a method and system for verifying hardware operation of an Application Specific Integrated Circuit (“ASIC”) chip. The ASIC includes microcode logic for enabling Transmission Control Protocol/Internet Protocol (“TCP/IP”) processing. The method is performed in a system that includes a first computing device having a processor and computer code for simulating a computing device that includes the ASIC. Wherein the ASIC is tested against a conventional TCP/IP stack included in a second computing device coupled to the first computing device.

Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Abstract: Herein disclosed is a function-variable type DSP apparatus comprising: a storage section for storing a plurality of DSP microprogram parts; and a plurality of DSP executing sections each for executing the DSP microprogram parts to implement a DSP function, each of the DSP microprogram parts being executable by each of the DSP executing sections to perform a set of steps necessary to implement a DSP base function forming part of a DSP function, whereby the DSP executing sections are operative to receive the DSP microprogram parts simultaneously from the storage section, and selectively execute the DSP microprogram parts in a sequence to respectively implement desired DSP functions.

Abstract: A cellular automaton cache memory architecture. On a micro-processor that is also capable of executing general-purpose instructions, a cache memory is provided to store instructions and data for use by the processor. The cache memory is further capable of storing data representing a first state of a cellular automaton at a first time step, where the data is organized in cells. A cellular automaton prefetch unit prefetches data associated with a cell to be updated and a neighborhood buffer stores the prefetched data. A cellular automaton update unit provides data from the neighborhood buffer to an update engine. The update engine includes a microprocessor execution unit capable of executing at least some general purpose microprocessor instructions and updates at least some of the selected cells according to an update rule and a state of any associated neighborhood cells to provide a state of the cellular automaton at a second time step.

Abstract: A web browser section provided in a scanner comprises a management table for relating URLs and setup values to each other and managing them and a URL interpretation section. A URL entered from a web browser installed in an information terminal is converted into a setup value by the URL interpretation section. The setup value is set in a drive control section through a setting section, whereby an image is read under a desired read condition.

Abstract: A method and apparatus for accelerating an object-oriented programming language are provided at a hardware gate level. In a Java-compliant embodiment, a Java Application framework is implemented in hardware. The Java.AWT, Java.NET. and Java.IO application frameworks are supported in the preferred embodiment of the invention. Instances and methods of supported application framework classes that are executed by a Java program are offloaded to a hardware object management system. A software stub is provided as an interface between the hardware object management system and the central processing unit.

Abstract: A method and configuration system are used for producing an application-specific functional module from a predefined functional module for a programmable controller. In this context, a marking device is useable to mask out subfunctions of the predefined functional module, so that just the software code for those subfunctions which is required in order to satisfy the functionality of the application-specific functional module are readable into the programmable controller. In this case, it is simultaneously necessary to ensure that only that software code which is not imperatively required for calculating a result for at least one of the unmarked subfunctions is masked out and is therefore not read in.

Abstract: A logical pipeline or logical hybrid pipeline is used for an xDSL communication system, and particularly for processing DMT symbols. This flexible arrangement permits easy and efficient sequencing of DMT symbols for transmit/receive tasks, and for multiple ports, since the pipeline resources can be shared or allocated as needed to support a particular data transmission. Each stage in the pipelines works on input data objects, and creates output data objects in the same format for use by other stages. The data objects are based on DMT symbols, so this facilitates intelligent control and sequencing of a DMT data transmission. The combination of the pipeline and the tailored data objects permits an implementation of a customized xDSL symbol processor.

Abstract: A Time Division Multiple Access (TDMA) mobile station architecture consuming less power and random access memory (RAM) is presented herein. The mobile station includes a system timer coprocessor which includes a microsequencer and a microwire for controlling radio components. Responsive execution of a single instruction by the microsequencer, the microwire transmits multiple bytes to the radio components. While the microwire transmits multiple bytes, execution of additional instructions for the microwire to transmit bytes is prevented by dynamically stalling the microsequencer pipeline.

Abstract: A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the computer. The computer program is then detected for containing the instruction extension. The programmable logic device is then configured to execute the instruction extension. The programmable logic device then executes the instruction extension for use by the processor core in processing the computer program.

Abstract: An integrated circuit having statistical processing capability. The integrated circuit has an input for receiving input data in a first data domain. A data converter is provided for converting received input data from the first domain to a second domain different from the first domain. A statistical processor is provided for obtaining statistical information from the output of the data converter and processing the obtained statistical information in accordance with a predetermined processing algorithm. An output on the integrated circuit allow access of the processed statistical information by the statistical processor external to the integrated circuit.

Abstract: A networking system consists of multiple computing devices connected to multiple networking processing engines each containing a memory system including a random access device (RAM). The RAM device contains a memory controller which performs memory read and write request handling by buffering incoming memory read and write requests and distributing the requests across multiple memory banks of the RAM in connection with client processes that support network services of the networking system. The read and write requests are intelligently reordered or prioritized utilizing grouping of memory reads and memory writes in such a way as to minimize the processing time of the requests while maintaining data coherency.

Abstract: A data processing device is used with peripheral devices having addressees and differing communication response periods. The data processing device includes a digital processor adapted for selecting different ones of the peripheral devices by asserting addresses of each selected peripheral device. Addressable programmable registers hold wait state values representative of distinct numbers of wait states corresponding to different address ranges. Circuitry responsive to an asserted address to the peripheral devices asserted by the digital processor generates the number of wait states represented by the value held in one of the addressable programmable registers corresponding to the one of the address ranges in which the asserted address occurs, thereby accommodating the differing communication response periods of the peripheral devices.

Abstract: An integrated circuit contains a microprocessor core, program memory and separate data storage, together with analog and digital signal processing circuitry. The ALU is 16 bits wide, but a 32-bit shift unit is provided, using a pair of 16-bit registers. The processor has a fixed length instruction format, with an instruction set including multiply and divide operations which use the shift unit over several cycles. No interrupts are provided. external pins of the integrated circuit allow for single stepping and other debug operations, and a serial interface (SIF) which allows external communication of test dat or working data as necessary. The serial interface has four wires (SERIN, SEROUT, SERCLK, SERLOADB), allowing handshaking with a master apparatus, and allowing direct access to the memory space of the processor core, without specific program control.

Abstract: The invention relates to a multi-standard digital receiver, in a digital video transmission system. It comprises a channel decoder for protecting a transmitted signal against channel transmission errors, the channel decoder comprising: a set of co-processors including at least 3 clusters of programmable co-processors for executing the functions of a digital front-end block (DFE), a channel correction block (CHN) and a forward error correction block (FEC), respectively, a general purpose processor (DSP) for managing control, synchronization and configuration of the channel decoder, and a memory (SM) shared between the clusters and the general purpose processor.

Abstract: An application specific signal processor (ASSP) performs vectorized and nonvectorized operations. Nonvectorized operations may be performed using a saturated multiplication and accumulation operation. The ASSP includes a serial interface, a buffer memory, a core processor for performing digital signal processing which includes a reduced instruction set computer (RISC) processor and four signal processing units. The four signal processing units execute the digital signal processing algorithms in parallel including the execution of the saturated multiplication and accumulation operation. The ASSP is utilized in telecommunication interface devices such as a gateway. The ASSP is well suited to handling voice and data compression/decompression in telecommunication systems where a packetized network is used to transceive packetized data and voice.

Abstract: The present invention provides a hardware accelerator of a DSP with a parameter RAM memory for storing the parameters required for the various operating conditions of the accelerator. The hardware accelerator can easily and without modification accommodate design changes such as the need to support additional ADSL lines.

Abstract: Disclosed is a method and apparatus for a unified RISC/DSP pipeline controller to control the execution of both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions for a signal processor. The unified RISC/DSP pipeline controller is coupled to a program memory, a RISC control unit, and at least one signal processing unit. The program memory stores both DSP and RISC control instructions and the RISC control-unit controls the flow of operands and results between the signal processing unit and a data memory that stores data. The signal processing unit executes the DSP instruction. The unified RISC/DSP pipeline controller generates DSP control signals to control the execution of the DSP instruction by the signal processing unit and RISC control signals to control the execution of the RISC control instruction by the RISC control unit.

Abstract: A relational processor having multiple inputs for receiving and processing parallel words. The relational processor comprises one or more input subsections for converting parallel input data to serial output data. Each of the one or more subsections has a parallel input for receiving the parallel input data and a respective subsection output for outputting the serial output data. A plurality of Boolean processors process the serial output data into processed output data, which plurality of Boolean processors are each operatively connected to the subsection outputs of the one or more input subsections to receive the serial output data. The processed output data is routed with a data routing system which is connected to a processor output of each of the plurality of Boolean processors to route data therefrom to one or more destination Circuits. The relational processor processes the input data in a single pass.

Abstract: A method and apparatus is disclosed for implementing an integrated video card and smart card reader. A single processor is used to perform both video and smart card reader functions. The processor simulates a PCI-to-PCMCIA detection logic scheme. An operating system, such as Windows, detects both a video card and a PCI-to-PCMCIA bridge. A smart card reader is attached to the integrated video card and smart card reader.

Abstract: An interrupt processing apparatus, system, and article including a machine-accessible medium, along with a method of processing interrupts, optimize interrupt-handling by combining the activities of acknowledging and disabling the interrupt. In one embodiment, the apparatus may include an interrupt cause register coupled to an interrupt disabling register and an interrupt mask register. The system may include a processor coupled to an interrupt cause register using a bus, along with an interrupt disabling register coupled to an interrupt mask register and the interrupt disabling register. The method may include reading an interrupt cause register in response to receiving an interrupt, and transferring a mask value stored in an interrupt disabling register directly to an interrupt mask register so as to disable receiving further interrupts from the interrupt source.

Abstract: Embodiments useful for a network of computers are presented. In an embodiment, an apparatus includes a microchip and a Faraday Cage. The microchip includes a personal computer with a general purpose microprocessor on the microchip. The Faraday Cage surrounds at least a portion of the microchip. In another embodiment, an apparatus includes a microchip. The microchip includes a general purpose microprocessor and one or more photovoltaic cells.

Abstract: The template data transfer coprocessor (TDTP) offloads block data transfer operations from a mediaprocessor. A uni-block template, program-guided template, an indirect template and queue-based template are described. The TDTP includes a template interpreter that employs an event-driven control mechanism to set up a template and compute block information and block information for each template. The programming involved in defining block data transfers for video and image processing algorithms is substantially reduced by the use of these templates.

Abstract: A method, apparatus, and system are described for processing an operation code (op-code) to be transmitted over a data path of a graphics pipeline. If the op-code comprises context state information for a first graphics context, then the context state information is transmitted to registers in the graphics pipeline over the graphics pipeline data path. If the op-code comprises a save state command, then context state information in the registers is retrieved and transmitted from the registers to a preallocated region of a frame buffer over the same graphics pipeline data path. If the op-code comprises a restore/load state command, then new context state information is loaded. Context state information for a second context can then be loaded on the graphics pipeline data path to restore or process a new context.

Abstract: A data processor formed on a LSI chip has an instruction address generator, an instruction cache memory having entries each storing an instruction address and an instruction corresponding to the instruction address, an instruction decoder decoding an instruction from said cache memory corresponding to an instruction address from said instruction address generator, an operand address generator generating an operand address in response to an output signal of said instruction decoder, and an operand cache memory having entries each storing an operand address and operand data corresponding to the operand address in its entry. The data processor executes an instruction that makes entries in both of said instruction cache memory and said operand cache memory ineffective.

Abstract: In an integrated circuit, an FPGA (2) has functions of a CPU core (5), and includes a user's circuit and so forth. This configuration allows the number of implemented components such as peripheral circuit chips to be decreased, and cost to be reduced. The integrated circuit is configured such that the CPU core (5), peripheral circuits thereof, and a system bus (8) are stored as logic data in a PROM (3), and the FPGA (2) performs functions as the CPU core (5), peripheral circuits (6) (7), and system bus (8) based on the logic data. Therefore, the CPU core (5), peripheral circuits (6) (7), and system bus (8) which have desired functions can be obtained according to contents of the logic data stored in the PROM (3). Further, a user can readily extend and change functions of the CPU core (5) by retrofitting a separate circuit to the system bus (8).

Abstract: A network processor useful in network switch apparatus and methods of operating such a processor in which data flow handling and flexibility is enhanced by the cooperation of an embedded processor complex with a suite of peripherals, all formed on a common semiconductor substrate. The interface processors provide data paths for inbound and outbound data flow and operate under the control of instructions stored in an instruction store formed on the semiconductor substrate, while storage of transiting data flow portions is provided by memory peripherals and interfaces to external memory elements.

Abstract: A microcontroller including a memory 10 and further electronic components configured capable of functioning as parts of a state machine 14, and an addressing circuit 20, a state register 25 and a data transfer circuit 22. The input of the addressing circuit 20 forms the input of the state machine 14, the output of the state register 25 forms the output of the state machine 14. The data transfer circuit 22 is connected to the addressing circuit 20, memory 10 and state register 25 in thus enabling the memory 10 of the microcontroller to be made use of for efficiently memorizing the changing state of the state machine.

Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Abstract: An audio/video processing engine that is programmable for processing digital video and digital audio simultaneously, either in parallel or concurrently, has an audio/video I/O processor that communicates with a single programmable hardware processor having reconfigurable logic blocks. The single programmable hardware processor communicates with both a general purpose processor and an optional digital signal processor for adjunct processing. The general purpose processor has a flash memory for initializing the programmable elements of the audio/video processing engine and has data links for remote accessing for programming, control and monitoring. The flash memory is accessible by the single programmable hardware processor, and may be reloaded remotely via the general purpose processor.