Abstract: An apparatus and method for implementing a hash algorithm word buffer. In one embodiment, a cryptographic unit may include hash logic configured to compute a hash value of a data block according to a hash algorithm, where the hash algorithm includes a plurality of iterations, and where the data block includes a plurality of data words. The cryptographic unit may further include a word buffer comprising a plurality of data word positions and configured to store the data block during computing by the hash logic, where subsequent to the hash logic computing one of the iterations of the hash algorithm, the word buffer is further configured to linearly shift the data block by one or more data word positions according to the hash algorithm. The hash algorithm may be dynamically selectable from a plurality of hash algorithms.

Abstract: One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type sub-processor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.

Abstract: A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities.

Abstract: An information-processing device that executes a specific process more frequently than other processes among a variety of processes is provided. The information-processing device includes a first processor capable of executing an instruction set corresponding to the variety of processes, and a second processor capable of executing a portion of or the entire instruction set, the second processor being capable of executing a part of the instruction set corresponding to the specific process more efficiently than the first processor, wherein the second processor executes the specific process whereas the first processor executes the other processes. Accordingly, the information-processing device can execute a variety of instructions efficiently.

Abstract: A design apparatus for designing a processor re-configurable for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extended instruction definition unit that searches the program for a part allowing use of an extended instruction in accordance with the analysis results by the analysis unit and generates definition of an extended instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extended instruction generated by the extended instruction definition unit.

Abstract: An arithmetic unit capable of reconfiguring circuitry in accordance with configuration data supplied includes a data processing unit performing a processing using input data; an output data maintenance unit maintaining the result of the processing to output it as an output data; and an output valid signal control unit outputting an output valid signal indicating whether or not the output data is valid, in which an output timing of a valid data to outside the arithmetic unit can be controlled optionally by controlling the output timing of the output valid signal.

Abstract: A microprocessor having model specific registers (MSRs) includes, for each of the MSRs, an associated default value that indicates whether the MSR is protected or non-protected and an associated fuse that, if blown, toggles the associated default value from protected to non-protected or non-protected to protected. In one embodiment, microcode that does the following in response to the microprocessor encountering an instruction that accesses a specified MSR: determines whether the fuse associated with the specified MSR is blown or unblown, uses the default value associated with the MSR as an indicator of whether the MSR is protected if the associated fuse is unblown; toggles the associated default value to generate the indicator if the associated fuse is blown; protects access to the MSR if the indicator indicates the MSR is protected; and refrains from protecting access to the MSR if the indicator indicates the MSR is non-protected.

Abstract: An arithmetic-logic unit for performing an operation of a prescribed bit length in an execution stage of a processor includes a plurality of sub-arithmetic-logic units which perform in respectively different pipeline stages sub-operations created by decomposing the operation of the prescribed bit length in a bit length direction, and a plurality of pipeline registers provided so as to separate the pipeline stages from each other, wherein each of the pipeline registers operates in such a manner as to be switchable between two operation modes, a flip-flop mode in which an output value is updated in synchronism with an input trigger and a transparent mode in which an input value is directly output.

Abstract: A crypto-engine for cryptographic processing has an arithmetic unit and an interface controller for managing communications between the arithmetic unit and a host processor. The arithmetic unit has a memory unit for storing and loading data and arithmetic units for performing arithmetic operations on the data. The memory and arithmetic units are controlled by an arithmetic controller.

Abstract: A method and apparatus for dynamic allocation of processing resources and tasks, including multimedia tasks. Tasks are queued, available processing resources are identified, and the available processing resources are allocated among the tasks. The available processing resources are provided with functional programs corresponding to the tasks. The tasks are performed using the available processing resources to produce resulting data, and the resulting data is passed to an input/output device.

Abstract: Systems and methods that optimize GPU processing by front loading activities from a set time/binding time to creation time via enhancements to an API that configures the GPU. Such enhancements to the API include: implementing layering arrangements, employing state objects and view components for data objects; incorporating a pipeline stage linkage/signature, employing a detection mechanism to mitigate error conditions. Such an arrangement enables front loading of the work and reduction of associated API calls.

Abstract: To reduce the size of a basic block composed of a plurality of arithmetic & logical processing unit blocks, and achieve high-speed operation. Unit blocks are arranged in a matrix and adjacent unit blocks are coupled. For the unit blocks arranged in a matrix, serial block numbers are assigned so as to form a closed loop curve. In a boundary region of minimum dividable unit blocks, selectors are arranged at input ports of the unit blocks, and the output wiring of the unit block in the boundary region is coupled to the input selectors of the adjacent unit block and an opposing unit block. A block size of a basic block is changed by switching a coupling path of the selector.

Abstract: A control system is provided for controlling a load powered by an auxiliary power source during an interruption in the utility power source and/or during a power failure. The control system of the present invention provides power to essential loads in a dwelling as predetermined by a user and/or per the user's real-time instructions as the needs of the user may change. Additionally, the control system of the present invention automatically controls non-essential loads in order to maintain the auxiliary power load below the maximum threshold. Furthermore, the control system of the present invention allows the user to manually override all the controlled loads in an emergency or when the needs of the user change. Additionally, the control system of the present invention allows outside triggers to change the priority of the loads in real-time and can automatically change the priority due to predetermined tasks already running.

Abstract: Methods and apparatus are provided for efficiently implementing signal processing cores as application specific processors. A signal processing core, such as a Fast Fourier Transform (FFT) core or a Finite Impulse Response (FIR) core includes a data path and a control path. A control path is implemented using processor components to increase resource efficiency. Both the data path and the control path can be implemented using function units that are selected, parameterized, and interconnected. A variety of signal processing algorithms can be implemented on the same application specific processor.

Abstract: A data processor that allows a CPU to access an external memory in an interval between data accesses from a DSP having a variable data length. In a case where a 24-bit mode is set, when a determination section determines that the DSP is accessing the external memory, a control section commands to place an access from the CPU to the external memory in a wait state. In a case where a 16-bit mode is set, the control section commands an address-data switching section, allowing the CPU to access the external memory by utilizing a third bus cycle, which is free.

Abstract: A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent instructions.

Abstract: A method and apparatus for clustering a plurality of data elements. The method comprises receiving a plurality of cluster elements, each cluster element containing at least a data element; generating a clustering score for each cluster element of the plurality of cluster elements versus all other cluster elements of the plurality of cluster elements using a computing device; determining a size of a diagonal matrix having a size corresponding to the number of the plurality of cluster elements; placing the clustering score in a diagonal matrix in storage one clustering score for each pair of cluster elements; creating a new cluster element for each two cluster elements in the diagonal matrix having a clustering score that exceeds a threshold; and storing generated new cluster elements in the storage.

Abstract: A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.

Abstract: Methods and apparatus, including computer program products, are provided for selecting a processor, such as a hardware provider, for executing a virtual appliance. In one aspect, there is provided a computer-implemented method. The method may include receiving information representative of whether one or more processors are capable of executing at least one of a plurality of virtual appliances. The received information may further including one or more costs to execute the at least one virtual appliance at one of the processors. One of the processors may be selected based on the received information. The selection enables the processor to execute the at least one virtual appliance. Related apparatus, systems, methods, and articles are also described.

Abstract: A digital system and method of operating the same. The system comprises a processor chip including a first elastic interface domain, wherein the first elastic interface domain comprises a first processor X logic and a first processor Y logic, wherein the first processor X and Y logic comprise first X and Y latches, respectively; and a first ASIC chip electrically coupled to the processor chip, wherein the first processor X and Y logics are configured to be simultaneously in a functional mode, wherein the first processor X logic is configured to switch from the functional mode to a scanning mode while the first processor Y logic remains in the functional mode, and wherein in response to the first processor Y logic being in the functional mode, the first processor Y logic is configured to generate a first reference ASIC clock signal to the first ASIC chip.

Abstract: A computing arrangement for identification of a current temporal input against one or more learned signals. The arrangement comprising a number of computational cores, each core comprises properties having at least some statistical independency from other of the computational, the properties being set independently of each other core, each core being able to independently produce an output indicating recognition of a previously learned signal, and at least one decision unit for receiving the produced outputs from the number of computational cores and making an identification of the current temporal input based the produced outputs.

Abstract: A disclosed image processing apparatus includes a SIMD microprocessor in which multiple processor elements are arranged in one dimension, each of the processor elements including multiple access registers arranged in stages for storing image data; and multiple data processing devices corresponding one-to-one with the stages of the access registers, arranged in one dimension in the same direction as the processor elements, and configured to read and write image data from/to the access registers. The access registers of each of the stages, each of which access registers is included in a different one of the processor elements, are connected with a common line. Wiring outlets, each of which connects the common line of a different one of the stages to a corresponding data processing device, are individually disposed within the SIMD microprocessor in such a manner that each wiring outlet has a shortest possible distance to the corresponding data processing device.

Abstract: The invention describes a method to convert geological response data to graphical raw data by using at least one stream processor for this purpose. The geological response data is pre-processed by a CPU and the preprocessed geological response data is fed into one or more stream processors. The stream processor then does the calculation intensive work on the preprocessed geological response data and returns the processing results back to the CPU which does some post-processing on the results coming from the stream processor Stream processors comprise single or multiple programmable GPUs, clusters/networks of nodes with one or several GPU's; cell processors (or processors derived from it) or a cluster of cell processor nodes, game computers (in the spirit of Sony's PlayStation, Nintendo's GameCube, etc.) or clusters of game computers.

Abstract: A system is disclosed comprising a logic circuit in an integrated circuit device, wherein the logic circuit comprises a logic fabric that includes a plurality of configurable logic blocks, switching blocks, and input/output blocks, wherein the logic fabric is configured according to configuration data provided to the integrated circuit device from an external memory and at least a portion of the logic fabric is configured as a configured processor to perform a first fixed logic function according to the configuration data. A fixed logic processor, a first auxiliary processing interface, a second fixed logic processor, a second auxiliary processing interface enable communication with the configured processor, wherein the configured processor remains configured to enable both the fixed logic processor and the second fixed logic processor to access the configured processor to perform the fixed logic function.

Abstract: An application-specific integrated circuit (ASIC) comprising a plurality of channels, each channel having circuitry for time and energy discrimination, a plurality of programmable registers, each programmable register configured to output at least one configuration parameter for the circuitry, and a channel-select register configured to identify a channel of the plurality of channels to be configured. The ASIC further includes a configuration-select register configured to identify the programmable register to be used for channel configuration, and a communications interface configured to transmit instructions received from a controller to one of the channel-select register, the configuration-select register, and the plurality of programmable registers.

Abstract: A method is disclosed for generating a sequential pattern of motor control instructions under control of a microcontroller for the purpose of controlling a motor. A pattern of motor control instructions is stored in a memory. A timing circuit is operable to generate a periodic output sync signal. The microcontroller is operable to initiate a sequential Read operation of the memory so as to cause sequential reading and output of motor control instructions from the memory in a predetermined order. Each of the read motor control instructions is then stored in a pre-load buffer after output from the memory. The contents of the pre-load buffer is then transferred to an output buffer in synchronization with the output sync signal, wherein the output of motor control instructions from the memory is not required to be periodic.

Abstract: A method for automatically configuring a microprocessor architecture so that it is able to efficiently exploit instruction level parallelism in a particular application. Executable code for another microprocessor type is translated into the specialized instruction set of the configured microprocessor. The configured microprocessor may then be used as a coprocessor in a system containing another microprocessor running the original executable code.

Abstract: Systems, methods, and computer program products for preemption in asynchronous systems using anti-tokens are disclosed. According to one aspect, configurable system for constructing asynchronous application specific integrated data pipeline circuits with preemption includes a plurality of modular circuit stages that are connectable with each other and with other circuit elements to form multi-stage asynchronous application specific integrated data pipeline circuits for asynchronously sending data and tokens in a forward direction through the pipeline and for asynchronously sending anti-tokens in a backward direction through the pipeline. Each stage is configured to perform a handshaking protocol with other pipeline stages, the protocol including receiving either a token from the previous stage or an anti-token from the next stage, and in response, sending both a token forward to the next stage and an anti-token backward to the previous stage.

Abstract: A system, method and tangible medium for unified exception handling with distributed exception identification includes a packet processing pipeline with at least two processing stages for processing data packets, each of the data packets being processed having an associated exception map in a memory of the apparatus. An exception detector at each processing stage detects whether any exception conditions apply to the data packet at the processing stage, and if so, a bit setter sets, modifies, or resets one or more bits in the exception map associated with exception conditions detected at the processing stage. An exception handler processes the exception map in response to the state of in the exception map after all the processing stages are complete.

Abstract: In one embodiment, a processor architecture for concurrently fetching data and patched instructions includes a microprocessor, an instruction patch, a dedicated instruction memory, a patch memory, and a dedicated data memory. The instruction patch is coupled to the microprocessor by an instruction bus, and is also coupled to the dedicated instruction memory and the patch memory. The patch memory and the dedicated data memory are coupled to the microprocessor by a data bus separate from the instruction bus. In one embodiment, the instruction patch has a number of comparators that can be individually enabled by respective enable signals. Each comparator that is enabled compares every bit on an instruction address with a corresponding bit of a patched instruction address to detect a patch condition. When a patch condition is detected, patched instructions are fetched from the patch memory, while the microprocessor can concurrently fetch data from the dedicated data memory.

Abstract: Methods and apparatus suitable for rapid creation and configuration of microcontroller products, which include a microcontroller or similar computational resource, and configurable logic devices are described. Various embodiments of the present invention allow development of new microcontroller-based products and product families in a rapid and cost-effective manner, thereby enabling early entry of such products into the marketplace. An existing microcontroller block and existing configurable logic devices are combined to form a unique product, wherein the microcontroller block is operable to configure the configurable logic devices to form the desired unique hardware characteristics of the microcontroller-based product. The microcontroller block configures the configurable logic devices when the product is reset, and/or when a power-up condition is recognized.

Abstract: In a calculation processing device for calculating inputted data to output the result of the calculation, a number-of-calculation generator generates the numbers of parallel and serial calculations based on the data length of the received data. When a calculation enable generator applies a parallel enabling signal or a serial enabling signal to an input controller in order to control the numbers of these calculations, the received data is inputted to a calculation processor in parallel during an input period of the parallel enabling signal, and is inputted to the calculation processor in serial during an input period of the serial enabling signal. The calculation processor performs parallel and serial processes for the inputted data to output the results of the processes on an output.

Abstract: A method for data storage includes programming a first group of analog memory cells at a first time at a known first temperature, so as to cause the analog memory cells in the first group to assume respective first analog storage values. Respective second analog storage values are read from the analog memory cells in the first group at a second time at which the analog memory cells are at a second temperature. A shift is estimated between the first analog storage values and the second analog storage values, and a memory access parameter is adjusted responsively to the estimated shift. A second group of the analog memory cells is accessed at the second temperature using the adjusted memory access parameter.

Abstract: A system-on-a-chip integrated circuit has a field programmable gate array core having logic clusters, static random access memory modules, and routing resources, a field programmable gate array virtual component interface translator having inputs and outputs, wherein the inputs are connected to the field programmable gate array core, a microcontroller, a microcontroller virtual component interface translator having input and outputs, wherein the inputs are connected to the microcontroller, a system bus connected to the outputs of the field programmable gate array virtual component interface translator and also to the outputs of said microcontroller virtual component interface translator, and direct connections between the microcontroller and the routing resources of the field programmable gate array core.

Abstract: A multiport semiconductor memory device having a processor wake-up function and multiprocessor system employing the same is provided. The multiprocessor system includes: a first processor configured to perform a first predetermined task; a second processor configured to perform a second predetermined task; and a multiport semiconductor memory device coupled to the first processor and the second processor, the multiport semiconductor memory device including: a memory cell array having at least one shared memory area; a first port coupled to the at least one shared memory area; a second port coupled to the at least one shared memory area; and a wake-up signal generator, the first processor being coupled to the at least one shared memory area via the first port, the second processor being coupled to the at least one shared memory area via the second port, the wake-up signal generator being coupled to the first processor and the second processor.

Abstract: Techniques, systems and apparatus are described for providing a processing element (PE) structure forming a floating point unit (FPU)-processing element. Each processing element includes each of two multiplexers (MUXes) to receive data from one or more sources including another PE, and select one value from the received data. The processing element includes an arithmetic logic unit (ALU) in communication with the two multiplexers to receive the selected value from each multiplexer as two input values, and process the received two input values to generate results of the ALU.

Abstract: An accelerated processing system includes one or more conventional processors, one or more coprocessors, and high speed data links between the processors, coprocessors and memory. In an embodiment, an application program is compiled and linked to a library of macros, the macros are invoked at run time by the application program, the application program marks data to be processed by the one or more coprocessors. A service and control coprocessor streams the marked data to the one or more coprocessors for processing. In an embodiment, a coprocessor is configured to analyze software code and data, to schedule processing of the software code and data in another coprocessor, and to manipulate the data based on the type of data that the other coprocessor is configured to process.

Abstract: Apparatus for processing audio signal streams including a plurality of audio signal inputs, an audio signal output, and a plurality of audio signal processing units, wherein the audio signal input, the audio signal output, and the plurality of audio signal processing units are connected to and controlled by a Micro Controller Unit (MCU), and wherein the audio signal processing units are configured to process more than one audio signal stream at the same time. Related apparatus and methods are also described.

Abstract: Apparatus and methods for real-time control using a data processor. In one aspect, the invention comprises an improved processor having one or more extension instructions (and associated supporting pipeline hardware) which are specially adapted for use in a real-time control algorithm running on the processor. In one exemplary embodiment, the processor is a 32-bit pipelined RISC device having custom multiply (CMUL) and multiply-accumulate (CMAC) instructions added to the extension instruction set to optimize algorithm performance in real-time linear time-invariant (LTI) applications. Specialized extension hardware, and methods for generating a processor design adapted for real-time control applications are also disclosed.

Abstract: An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.

Abstract: Method and system for performing hardware tasks using a hardware state machine and a processor is provided. The method includes, setting a breakpoint for a state machine state; running the processor in a parallel mode with the state machine; passing control to the processor after a breakpoint condition is encountered; performing a task, wherein the processor performs the task which was meant to be performed by the state machine; and transferring control back to the state machine after the processor performs the task. The system includes an Application Specific Integrated Circuit (ASIC) with the state machine, and the processor.

Abstract: An on-chip debug emulator is capable of connecting to the target device and the host device for remotely debugging the program in the target device. The on-chip debug emulator contains a debug communication control unit. This debug communication control unit contains a plurality of serial communication circuits, the plurality of serial communication circuits are commonly provided with a clock signal. The debug communication control unit controls communications with the target device based on commands output from the host device. Each of The plurality of serial communication circuits contains a data buffer and serially transmits data stored in the data buffer to and from the target device while synchronized with the clock signal. Namely, the plurality of serial communication circuits communicate in parallel while operating synchronized with the same clock. The on-chip debug emulator can in this way be made utilizing a low-cost microcomputer not containing any parallel communication circuits.

Abstract: This processing is distributed among number of simple hexagonal units distributed in a honeycomb layer, consisting of a central hexagram surrounded by six receiving cells, each representing an invariable binary place fed into central hexagram's CPU controlled by a simple program. The activated receiving cells indicate the presence of a stimulus. The interconnected layers overlap so that the higher-level receiving cells get input from the lower-level central hexagrams and higher-level output modifies lower-level programs as well as sends input to other levels or Memory Units. Integration of layer output is achieved in 3D Memory Unit Complex consisting of truncated octagons, where each hexagonal side represents a binary number linked to 6 others through one binary place that makes adjacent numbers different. The input into each Memory Unit comes from the output of a Patch of central hexagrams a clocked input, other-layer output or a Memory Unit feedback.

Abstract: A method and system are disclosed, in a simulation of a design of a digital integrated circuit chip, to limit a number of scan test clocks and chip ports used for testing the chip. Clock domains are identified within the design of the chip that are independent of each other. The independent clock domains are grouped together, within said chip design, to form clock domain groups. A timing analysis is performed on the design of the chip by clocking the clock domain groups each with an independent scan test clock. The scan test clocks originate externally to the design and by-pass, within the chip design, the corresponding internal clocks. Capture mode violations are recorded from the timing analysis and are used to go back and form new clock domain groups, thereby repeating the method until no capture mode violations are generated.

Abstract: The present invention provides an array of parallel programmable processing engines interconnected by a switching network. At least some of the processing engines execute a thread, and at least some threads communicate with each other through communication objects either internally within one processing engine or through the network. A scheduling step of the parallel programmable processing engines is initiated by one or more events, an event being defined by a change of a state variable of a communication object. The array comprises: means for scheduling a scheduling step of the processing engines, the scheduling means comprising means for executing at least a first set of threads in parallel, means for updating state values of communications objects in response to the parallel executing step, and means for repeatedly and sequentially scheduling the executing means and the updating means until no more events occur. The present invention also provides a deterministic method of operating such an array.

Abstract: A Distributed-Structure-based parallel module structure and parallel processing method. One object is to provide a novel sequence-net computer architecture. A parallel operating structure with N+1 independent flow-sequences is created, and the N+1 flow-sequences control independently the distributed token via the sequence-net instructions to realize the parallel operating of module. Wherein N flow-sequences is regular type, a new consistency flow-sequence Sc running independently is composed by consistency tokens. The distributed token connecting among multi-machines support the co-operation running among N+1 flow-sequences.

Abstract: A fast linked multiprocessor network (22) including a plurality of processing modules (24, 26, 28, 30, 32, and 34) implemented on a field programmable gate array (10) and a plurality of configurable uni-directional links (21, 23, 25, 27, 29, 31) coupled among at least two of the plurality processing modules providing a streaming communication channel between at least two of the plurality of processing modules.

Abstract: A design apparatus for designing a configurable processor for an application, includes an analysis unit that analyzes the content of a program to be executed by the processor; a hardware extension unit that searches the program for a part of the program allowing hardware extension in accordance with the analysis results by the analysis unit and generates hardware extension information for the searched part; an extension instruction definition unit that searches the program for a part allowing use of an extension instruction in accordance with the analysis results by the analysis unit and generates definition of an extension instruction for the searched part; and a performance estimation unit that estimates whether or not the performance of the processor satisfies a target performance using at least one of the hardware extension information generated by the hardware extension unit and the definition of the extension instruction generated by the extension instruction definition unit.

Abstract: An encoder and an encoding method capable of improving the transfer efficiency in an encoding process is provided. The encoder determines the number of removed bit planes in order that the quantity of generated codes per frame is kept constant when performing the encoding process. A predetermined number of bit planes corresponding to those parts of information that seem relatively small to users are removed. Accordingly, the encoder can prevent variation of processing time in a stage before the encoder performs an encoding process.