Mode Switching Patents (Class 712/43)
  • Patent number: 10666631
    Abstract: Systems, methods, and computer program products for distributed validation of credentials are described. Upon receiving a request to perform an action by a user, a system performs a multi-part authentication where in each part, only a portion of authentication information is passed. In a first stage, an application manager of the system receives a first token than specifies partial access rights. In a second stage, a cloud controller of the system requests and receives privileges of the user separately from the first token. An API is presented with a token that only contains the authorities that the API needs, while still allowing validation of cloud controller permissions without having to escalate the user's privileges.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: May 26, 2020
    Assignee: Pivotal Software, Inc.
    Inventors: Joseph Benjamin Hale, Sree Lekha Tummidi
  • Patent number: 10649678
    Abstract: An apparatus comprises partition identifier storage storing an instruction partition identifier and a data partition identifier. When issuing a memory transaction for accessing data, the transaction is issued specifying a partition identifier depending on the data partition identifier, while when the memory transaction is for accessing an instruction, the transaction specifies a partition identifier depending on the instruction partition identifier. A memory system component selects one of a number of sets of memory system component parameters in dependence on the partition identifier specified by a memory transaction to be handled. The memory system component controls allocation of resources for handling the memory transaction or manages contention for the resources in dependence on the selected set of parameters, or updates performance monitoring data specified by the selected set of parameters in response to handling of said memory transaction.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: May 12, 2020
    Assignee: ARM Limited
    Inventor: Steven Douglas Krueger
  • Patent number: 10558489
    Abstract: Systems, apparatuses, and methods for suspending and restoring operations on a processor are disclosed. In one embodiment, a processor includes at least a control unit, multiple execution units, and multiple work creation units. In response to detecting a request to suspend a software application executing on the processor, the control unit sends requests to the plurality of work creation units to stop creating new work. The control unit waits until receiving acknowledgements from the work creation units prior to initiating a suspend operation. Once all work creation units have acknowledged that they have stopped creating new work, the control unit initiates the suspend operation. Also, when a restore operation is initiated, the control unit prevents any work creation units from launching new work-items until all previously in-flight work-items have been restored to the same work creation units and execution units to which they were previously allocated.
    Type: Grant
    Filed: February 21, 2017
    Date of Patent: February 11, 2020
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander Fuad Ashkar, Michael J. Mantor, Randy Wayne Ramsey, Rex Eldon McCrary, Harry J. Wise
  • Patent number: 10339333
    Abstract: A method for controlling an application to access a memory includes: receiving a first access request provided by the application and having a first access key; verifying the first access key; generating a second access key for the application if the verification of the first access key is successful; storing the second access key and providing the second access key to the application; receiving a second access request provided by the application and having a target address and a second access key; identifying whether the target address is within a reference address space indicative of a preset storage location of the memory, and verifying the second access key; generating an access control command according to an identification result of whether the target address is within the reference address space and a verification result of the second access key received from the application so as to restrict or permit the application to access the memory.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: July 2, 2019
    Assignee: MONTAGE TECHNOLOGY CO., LTD.
    Inventors: Gang Shan, Yi Li, Dongjie Tang
  • Patent number: 10042406
    Abstract: According to one embodiment, a semiconductor device includes a bus, a control circuit connected to the bus, a first circuit connected to the bus and configured to operate under control of the control circuit, a power source, a switch element connected between the first circuit and the power source, and a second circuit connected between the bus and the first circuit, the second circuit configured to cause the switch element to enter an on-state in response to a first signal transmitted from the control circuit to the first circuit through the bus.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: August 7, 2018
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Yasuhiro Katayama
  • Patent number: 9898071
    Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: February 20, 2018
    Assignee: Apple Inc.
    Inventors: David J. Williamson, Gerard R. Williams, III
  • Patent number: 9753776
    Abstract: A computer system may determine a mode for a processor. The processor may support SMT, and it may have a first hardware thread with a first architected resource and a second hardware thread with a second architected resource. The computer system may determine that the processor is in a reduced-thread mode. The computer system may determine that the first hardware thread is a primary hardware thread that is active in the reduced-thread mode, and that the second hardware thread is a secondary hardware thread that is inactive in the reduced-thread mode. The computer system may disable the second hardware thread. The computer system may enable the first hardware thread to access the second architected resources.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: September 5, 2017
    Assignee: International Business Machines Corporation
    Inventors: Sangram Alapati, Puneeth A. Bhat, Satish K. Sadasivam
  • Patent number: 9529750
    Abstract: Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing interrupts. In certain embodiments, the system includes a SP, which includes a processor, a non-volatile memory and a communication interface. The SP generates a first system management interface (SMI) message, and sends the first SMI message to the host computer to initiate a data transaction. The OS, in response to the first SMI message, execute a SMI handler in a system management random access memory (SMRAM) area at the CPU to enter a system management mode (SMM). The SMI handler then sends the notification to the SP via the communication interface. In response to receiving the notification from the SMI handler, the SP starts performing the data transaction with the host computer.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: December 27, 2016
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Sanjoy Maity, Purandhar Nallagatla, Harikrishna Doppalapudi, Ramakoti Reddy Bhimanadhuni, Satheesh Thomas, Joseprabu Inbaraj
  • Patent number: 9529410
    Abstract: Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing power off commands. In certain embodiments, the system includes a SP, which includes a processor, a non-volatile memory and a communication interface. The SP generates a first power off command for a data transaction purpose, and sends the first power off command to the host computer to initiate a data transaction. The OS, in response to the first power off command, calls an Advanced Configuration and Power Interface (ACPI) Machine Language (AML) code, which execute a system management interface (SMI) handler at the CPU to enter a system management mode (SMM). The SMI handler then sends a notification to the SP via the communication interface. In response to receiving the notification from the SMI handler, the SP starts performing the data transaction with the host computer.
    Type: Grant
    Filed: July 14, 2014
    Date of Patent: December 27, 2016
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Sanjoy Maity, Purandhar Nallagatla, Harikrishna Doppalapudi, Ramakoti Reddy Bhimanadhuni, Satheesh Thomas, Joseprabu Inbaraj
  • Patent number: 9436267
    Abstract: A data storage device includes a nonvolatile memory device; and a controller suitable for controlling an operation of the nonvolatile memory device based on a request from a host device, wherein the controller includes a first core activated in a normal mode and a second core activated in a standby mode.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: September 6, 2016
    Assignee: SK Hynix Inc.
    Inventors: Dong Jae Shin, Soo Nyun Kim
  • Patent number: 9229728
    Abstract: A processing system capable of connecting to a computer device comprising a second processing unit is provided. The processing system comprises a first processing unit and a first storage unit. The first storage unit is coupled to the first processing unit for storing at least a first programming code and a second programming code. At a first time point, the first processing unit accesses the first programming code from the first storage unit to set the processing system. At a second time point after the first time point, the first processing unit receives an instruction from the second processing unit and transfers the second programming code to the second processing unit in response to the instruction. The second processing unit controls the processing system with the second programming code.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: January 5, 2016
    Assignee: LITE-ON TECHNOLOGY CORPORATION
    Inventor: Chien-Ping Chung
  • Patent number: 9210487
    Abstract: Embodiments provide a methodology for designing a large-scale non-blocking OCS using a multi-stage folded CLOS switch architecture for use in datacenter networks and fiber-rich backbone network POPs. One aspect employs a folded CLOS architecture because of its ease of implementation, enabling the topology to scale arbitrarily with increasing number of stages. The fraction of ports allocated for internal switch wiring (overhead) also increases with the number of stages. Design decisions are made to carefully optimize the insertion loss per module, number of ports per module, number of stages and the total scale required. Other embodiments include folded CLOS switch architectures having at least two stages. In one example, power monitoring may be included only on the leaf switches.
    Type: Grant
    Filed: March 11, 2015
    Date of Patent: December 8, 2015
    Assignee: Google Inc.
    Inventors: Xiaoxue Zhao, Amin Vahdat, Hong Liu
  • Patent number: 9189234
    Abstract: An overhead reduction system creates a plurality of candidates of constants to be stored in one or more constant registers based on constants used in the program code of the current compilation scope, estimates, for each of the candidates of constants, an effect of overhead reduction by generation of the constant used in the program code by using the candidate of constant, determines a base constant to be loaded on the constant registers based on the estimation result, loads the base constant on the constant registers at an entry point of the program code, and generates a code for generating the constants used in the program code by using values of the constant registers.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: November 17, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventor: Hiroshi Inoue
  • Patent number: 9170753
    Abstract: A method of providing memory accesses for a multi-core processor includes reserving a group of pins of a multi-core processor to transmit either data or address information in communication with one or more memory chips, receiving memory access requests from the plurality of processor cores, determining granularity of the memory access requests by a memory controller, and dynamically adjusting the number of pins in the group of pins to be used to transmit address information based with the granularity of the memory access requests.
    Type: Grant
    Filed: December 30, 2013
    Date of Patent: October 27, 2015
    Assignee: Peking University
    Inventors: Yifeng Chen, Weilong Cui, Xiang Cui
  • Patent number: 9141567
    Abstract: A configurable device interface enhances the ability of a processor to communicate with other devices. A configurable serial interface promotes efficient data transmission and reception. The configurable serial interface includes a source of transmit data that the configurable serial interface may access even while data reception is simultaneously completing.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: September 22, 2015
    Assignee: HARMAN INTERNATIONAL INDUSTRIES, INCORPORATED
    Inventors: James D. Pennock, Ronald Baker, Brian R. Parker, Christopher Belcher
  • Patent number: 9098302
    Abstract: Methods and apparatus are disclosed to improve system boot speed. A disclosed example method includes associating a first serial peripheral interface (SPI) with a baseboard management controller (BMC), copying an image from the first SPI to a volatile memory in response to receiving power at the BMC, and in response to receiving an access request associated with the first SPI, providing access to the image stored in the volatile memory.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Robert Swanson, Mallik Bulusu, Palsamy Sakthikumar, Ramamurthy Krithivas, James Steven Burns
  • Patent number: 9053292
    Abstract: A processor has a register file configurable for different execution modes. In one mode the multiple register segments form a single register file where each register segment stores a Multiple Instructions Multiple Data (MIMD) super instruction matrix issuing four simultaneous instruction matrices where each individual instruction within each of the four simultaneous instruction matrices is a scalar or Single Instruction Multiple Data (SIMD). Another execution mode has the multiple register segments forming individual independent register tiles with individual register state to support simultaneous processing of separate threads, where each instruction matrix is associated with a separate thread and a separate register file segment.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: June 9, 2015
    Assignee: Soft Machines, Inc.
    Inventor: Mohammad A. Abdallah
  • Patent number: 8966226
    Abstract: A method and system of verifying proper execution of a secure mode entry sequence. At least some of the exemplary embodiments may be a method comprising delivering an instruction from a memory to a processor across an instruction bus (the instruction at least partially configures the processor for secure mode of operation different that privilege modes of the processor), verifying delivery of the instruction across the instruction bus, and checking for proper execution of the instruction using a trace port of the processor.
    Type: Grant
    Filed: October 8, 2004
    Date of Patent: February 24, 2015
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory Remy Philippe Conti, Jerome Laurent Azema
  • Patent number: 8891757
    Abstract: A cryptographic integrated circuit including a programmable main processor for executing cryptographic functions, an internal memory, and a data transmission bus to which the main processor and the internal memory are electrically connected. The cryptographic integrated circuit also includes a programmable arithmetic coprocessor that has specific hardware arithmetic units each being designed to carry out a predetermined arithmetical operation. The programmable arithmetic coprocessor is separate from the main processor and is also electrically connected to the data transmission bus.
    Type: Grant
    Filed: February 17, 2012
    Date of Patent: November 18, 2014
    Assignee: Bull SAS
    Inventor: Patrick Le Quéré
  • Patent number: 8850170
    Abstract: An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: September 30, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bernhard Egger, Dong-Hoon Yoo, Tai-Song Jin, Won-Sub Kim, Min-Wook Ahn, Jin-Seok Lee, Hee-Jin Ahn
  • Publication number: 20140281385
    Abstract: A network processor includes a plurality of processing cores configured to process data packets, and a processing mode mechanism configurable to configure the processing cores between a pipeline processing mode and a parallel processing mode. The processing mode mechanism may include switch elements, or a fabric logic and a bus, configurable to interconnect the processing cores to operate in either the pipeline processing mode or the parallel processing mode.
    Type: Application
    Filed: March 12, 2013
    Publication date: September 18, 2014
    Applicant: QUALCOMM INCORPORATED
    Inventor: Yifeng TU
  • Publication number: 20140164736
    Abstract: Embodiments related to managing lazy runahead operations at a microprocessor are disclosed. For example, an embodiment of a method for operating a microprocessor described herein includes identifying a primary condition that triggers an unresolved state of the microprocessor. The example method also includes identifying a forcing condition that compels resolution of the unresolved state. The example method also includes, in response to identification of the forcing condition, causing the microprocessor to enter a runahead mode.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 12, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Guillermo J. Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell D. Boggs, Magnus Ekman
  • Patent number: 8745424
    Abstract: An information processing system has a power supply section which detects a predetermined potential applied to a USB terminal and supplying the potential as a source potential, an information detection section which detects the predetermined information supplied to the USB terminal, and a processing section which executes, subsequent to the detection of the predetermined potential, the encoding process or the decoding process in accordance with at least the operating information supplied from the operation key arranged on the body and in accordance with the predetermined information supplied to the USB terminal after detection of the predetermined information. The recording and reproducing operation can be performed with the operating key on the body with power supplied only from the USB terminal.
    Type: Grant
    Filed: April 9, 2013
    Date of Patent: June 3, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hirofumi Kanai
  • Patent number: 8694689
    Abstract: In a storage system which includes a plurality of microprocessors, it is desired to prevent delay in I/O responses due to synchronous processing waiting for asynchronous processing, while still ensuring the throughput of asynchronous processing. In a plurality of microprocessors possessed by a controller, synchronous processors and asynchronous processors are mixed together. The synchronous processors are microprocessors whose duty is to perform synchronous processing and not to perform asynchronous processing. And the asynchronous processors are microprocessors whose duty is to perform asynchronous processing and not to perform synchronous processing.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: April 8, 2014
    Assignee: Hitachi, Ltd.
    Inventors: Tomohiro Yoshihara, Sadahiro Sugimoto, Norio Shimozono, Noboru Morishita, Masayuki Yamamoto
  • Patent number: 8694973
    Abstract: Methods and systems for executing a code stream of non-native binary code on a computing system are disclosed. One method includes parsing the code stream to detect a plurality of elements including one or more branch destinations, and traversing the code stream to detect a plurality of non-native operators. The method also includes executing a pattern matching algorithm against the plurality of non-native operators to find combinations of two or more non-native operators that do not span across a detected branch destination and that correspond to one or more target operators executable by the computing system. The method further includes generating a second code stream executable on the computing system including the one or more target operators.
    Type: Grant
    Filed: September 27, 2011
    Date of Patent: April 8, 2014
    Assignee: Unisys Corporation
    Inventor: Andrew Ward Beale
  • Patent number: 8683474
    Abstract: In an accounting apparatus, a conflict determination unit determines whether or not the accounting mode is in a conflict state where a process is executing in another logical CPU and stores the determination result in an accounting information storage unit, when a process of the user starts to be executed in a logical CPU of an SMT processor. And a CPU use time acquisition unit collects the CPU use time of the process in the conflict state or the non-conflict state distinctively and stores it in an accounting information storage unit. Thereafter, a CPU use time conversion unit converts the CPU use time in the conflict state, with a predetermined weighting, based on the CPU use time in the conflict state and the non-conflict state, after the end of executing the process, and an accounting calculation unit calculates the accounting amount for the process from an effective use time.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: March 25, 2014
    Assignee: Fujitsu Limited
    Inventors: Shuji Yamamura, Kouichi Kumon
  • Patent number: 8677100
    Abstract: An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: March 18, 2014
    Assignee: Macronix International Co., Ltd.
    Inventors: Yulan Kuo, Kuen-Long Chang, Chun-Hsiung Hung
  • Patent number: 8654932
    Abstract: A network tap port aggregator for use in monitoring a network is provided. The network tap port aggregator includes a first device interface terminal for receiving a first network feed. The network tap port aggregator also includes a second device interface terminal for receiving a second network feed. The network tap port aggregator further includes a circuitry coupled with the first device interface terminal and with the second device interface terminal, the circuitry configured to monitor the first network feed and the second network feed and to aggregate the first network feed and the second network feed into an aggregated network feed. The network tap port aggregator yet also includes a first monitor interface terminal coupled to the circuitry for providing the aggregated network feed to a first network monitor that is external to the network tap port aggregator.
    Type: Grant
    Filed: July 19, 2010
    Date of Patent: February 18, 2014
    Assignee: Net Optics, Inc.
    Inventors: Eldad Matityahu, Bob Shaw, Xiaochun Liu, Stephen Strong
  • Patent number: 8650440
    Abstract: A system comprises a first master element; and at least one shared communication element arranged to operably couple the first master element to at least one slave element. The system further comprises at least one validation element located on at least one further validation path located between the first master element and the at least one slave element, wherein the at least one validation element is arranged to validate at least one of: at least one access request by the first master element; and a response to an access request from the at least one slave element.
    Type: Grant
    Filed: January 16, 2008
    Date of Patent: February 11, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Michael Rohleder, Gary Hay, Stephan Mueller, Manfred Thanner
  • Patent number: 8615799
    Abstract: An apparatus providing for a secure execution environment. The apparatus includes a microprocessor and a secure non-volatile memory. The microprocessor is configured to execute non-secure application programs and a secure application program, where the non-secure application programs are accessed from a system memory via a system bus. The secure non-volatile memory is coupled to the microprocessor via a private bus. The secure non-volatile memory is configured to store the secure application program, where transactions over the private bus between the microprocessor and the secure non-volatile memory are isolated from the system bus and corresponding system bus resources within the microprocessor.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: December 24, 2013
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Terry Parks
  • Patent number: 8566565
    Abstract: A computing system includes a microprocessor that receives values for configuring operating modes thereof. A device driver monitors which software applications currently running on the microprocessor are in a predetermined list and responsively dynamically writes the values to the microprocessor to configure its operating modes. Examples of the operating modes the device driver may configure relate to the following: data prefetching; branch prediction; instruction cache eviction; instruction execution suspension; sizes of cache memories, reorder buffer, store/load/fill queues; hashing algorithms related to data forwarding and branch target address cache indexing; number of instruction translation, formatting, and issuing per clock cycle; load delay mechanism; speculative page tablewalks; instruction merging; out-of-order execution extent; caching of non-temporal hinted data; and serial or parallel access of an L2 cache and processor bus in response to an instruction cache miss.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: October 22, 2013
    Assignee: VIA Technologies, Inc.
    Inventors: Rodney E. Hooker, Colin Eddy, G. Glenn Henry
  • Patent number: 8489862
    Abstract: An object of the invention is to reduce the electric power consumption resulting from temporarily activating a processor requiring a large electric power consumption, out of a plurality of processors. A multiprocessor system (1) includes: a first processor (141) which executes a first instruction code; a second processor (151) which executes a second instruction code, a hypervisor (130) which converts the second instruction code into an instruction code executable by the first processor (141); and a power control circuit (170) which controls the operation of at least one of the first processor (141) and the second processor (151). When the operation of the second processor (151) is suppressed by the power control circuit (170), the hypervisor (130) converts the second instruction code into the instruction code executable by the first processor (141), and the first processor (141) executes the converted instruction code.
    Type: Grant
    Filed: June 5, 2008
    Date of Patent: July 16, 2013
    Assignee: Panasonic Corporation
    Inventors: Masahiko Saito, Masashige Mizuyama
  • Patent number: 8478972
    Abstract: A system, apparatus and method for handling switching among threads within a multithread processor are described herein. Embodiments of the present invention provide a method for multithread handling that includes fetching and issuing one or more instructions, corresponding to a first instruction execution thread, to an execution block for execution during a cycle count associated with the first instruction execution thread and when the instruction execution thread is in an active mode. The method further includes switching a second instruction execution thread to the active mode when the cycle count corresponding to the first instruction execution thread is complete, and fetching and issuing one or more instructions, corresponding to the second instruction execution thread, to the execution block for execution during a cycle count associated with the second instruction execution thread.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: July 2, 2013
    Assignee: Marvell World Trade Ltd.
    Inventors: Jack Kang, Hsi-Cheng Chu
  • Publication number: 20130091380
    Abstract: Methods, apparatuses, and computer program products for dynamically reconfiguring a primary processor identity within a multi-processor socket server are provided. Embodiments include detecting, by the service processor, a processor socket reconfiguration event corresponding to a first processor socket; disabling, by the service processor, the first processor socket of the server in response to detecting the processor socket reconfiguration event; and reassigning, by the service processor, the primary processor identity to a second processor socket of the server.
    Type: Application
    Filed: October 7, 2011
    Publication date: April 11, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael Decesaris, Ralph M. Begun, Randolph S. Kolvick, Steven L. Vanderlinden
  • Patent number: 8407714
    Abstract: An arithmetic device simultaneously processes a plurality of threads and may continue the process by minimizing the degradation of the entire performance although a hardware error occurs. An arithmetic device 100 includes: an instruction execution circuit 101 capable of selectively executing a mode in which the instruction sequences of a plurality of threads are executed and a mode in which the instruction sequence of a single thread is executed; and a switch indication circuit 102 instructing the instruction execution circuit 101 to switch a thread mode.
    Type: Grant
    Filed: December 15, 2009
    Date of Patent: March 26, 2013
    Assignee: Fujitsu Limited
    Inventors: Norihito Gomyo, Toshio Yoshida, Ryuichi Sunayama
  • Patent number: 8327122
    Abstract: A context switch method capable of promptly switching a context for a dynamically generated task and a dynamic link by converting a state of multiple register files, switching the context, and separately restoring and storing the context. That is, the context switch method includes: maintaining a multiple register files; establishing the multiple register to be in any one of a prefetch state, a current state, and a store state; converting a state of the multiple register files to be in any one of the prefetch state, the current state, and the store state when a context switch occurs; wherein, in the prefetch state, determining a memory address to read a next task context to be subsequently performed by the register file, in the current state, performing a task with the task context of the register file and in the store state, storing the register file in a memory.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: December 4, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae Don Lee, Keun Soo Yim, Woon Gee Kim, Jeong Joon Yoo, Jung Keun Park, Chang-Woo Baek, Chae Seok Im
  • Patent number: 8255723
    Abstract: A multiple instruction execution modules device that comprises a first instruction execution module and a second instruction execution module and a context switch controller; wherein the first instruction execution module is logically identical to the second instruction execution module but substantially differs from the second instruction execution module by at least one power consumption characteristic; wherein the context switch controller controls a context switch between the first instruction execution module and the second instruction execution module; wherein an instruction execution module that its context has been transferred is shut down.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: August 28, 2012
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Anton Rozen, Michael Priel, Leonid Smolyansky
  • Publication number: 20120179894
    Abstract: A data processing circuit is described that includes an instruction decoder operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of multiple functional units, and in the second instruction mode instructions controlling only one functional unit. A mode control circuit controls selecting the instruction modes. The instruction decoder uses time-stationary decoding of operations and destination registers. When instructions are scheduled, constraints are imposed on operations for which operation selection and destination register selection are included on different sides of an instruction mode change. When an instruction containing a jump is encountered, the mode control circuit sets the instruction mode for subsequent instructions in conformity with information provided by executing the jump command.
    Type: Application
    Filed: March 13, 2012
    Publication date: July 12, 2012
    Applicant: Silicon Hive B. V.
    Inventors: Jeroen Anton Johan Leijten, Hendrik Tjeerd Joannes Zwartenkot
  • Publication number: 20120166764
    Abstract: Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire.
    Type: Application
    Filed: November 17, 2011
    Publication date: June 28, 2012
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: G. Glenn Henry, Stephan Gaskins
  • Patent number: 8183881
    Abstract: Method and apparatus for using configuration memory for buffer memory is described. Drivers associated with a portion of the configuration memory are rendered incapable of creating a contentious state irrespective of information stored the portion of configuration memory. Configuration data is received in a non-configuration data format and buffered in the portion of the configuration memory.
    Type: Grant
    Filed: March 29, 2004
    Date of Patent: May 22, 2012
    Assignee: Xilinx, Inc.
    Inventors: Benjamin J. Stassart, Stephen M. Trimberger
  • Patent number: 8171267
    Abstract: A method and apparatus for migrating a task in a multi-processor system. The method includes examining whether a second process has been allocated to a second processor, the second process having a same instruction to execute as a first process and having different data to process in response to the instruction from the first process, the instruction being to execute the task; selecting a method of migrating the first process or a method of migrating a thread included in the first process based on the examining and migrating the task from a first processor to the second processor using the selected method. Therefore, cost and power required for task migration can be minimized. Consequently, power consumption can be maintained in a low-power environment, such as an embedded system, which, in turn, optimizes the performance of the multi-processor system and prevents physical damage to the circuit of the multi-processor system.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: May 1, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Seung-won Lee
  • Patent number: 8145883
    Abstract: A preload instruction in a first instruction set is executed at a processor. The preload instruction causes the processor to preload one or more instructions into an instruction cache. The pre-loaded instructions are pre-decoded according to a second instruction set that is different from the first instruction set. The preloaded instructions are pre-decoded according to the second instruction set in response to an instruction set preload indicator (ISPI).
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: March 27, 2012
    Assignee: QUALCOMM Incorporation
    Inventors: Thomas Andrew Sartorius, Brian Michael Stempel, Rodney Wayne Smith
  • Patent number: 8145888
    Abstract: A data processing circuit has an execution circuit (18) with a plurality of functional units (20). An instruction decoder (17) is operable in a first and a second instruction mode. In the first instruction mode instructions have respective fields for controlling each of the functional units (20), and in the second instruction mode instructions control one functional unit. A mode control circuit (12) controls the selection of the instruction modes. In an embodiment, the instruction decoder uses time-stationary decoding of the selection of operations to be executed by the execution circuit (18) and the selection of destination registers from the set of registers (19). Mode switching is a more efficient way of reducing instruction time for time stationary processors than indicating functional units for which the instruction contains commands.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: March 27, 2012
    Assignee: Silicon Hive B.V.
    Inventors: Jeroen Anton Johan Leijten, Hendrik Tjeerd Joannes Zwartenkot
  • Patent number: 8146093
    Abstract: A computer multi-OS switching method, in which a data exchange region for storing OS running environment information is provided, wherein the method includes: A. saving running information of computer hardware devices in a random access memory (RAM) by the computer after receiving a command for switching OS; B. obtaining OS running environment information of OS to be switched to from the data exchange region and storing the obtained OS running environment information in the RAM by the computer; C. restoring running state of the computer hardware devices based on its running information stored in the RAM, obtaining a preset OS to be switched to, starting the OS and subsequently executing the OS running environment information in the RAM by the computer. The method reduces the time for switching between multi-OSs in a computer.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: March 27, 2012
    Assignee: Lenovo (Beijing) Limited
    Inventors: Zhongqing Li, Liang Tang
  • Patent number: 8135941
    Abstract: One embodiment of the invention provides a processor. The processor generally includes a first and second processor core, each having a plurality of pipelined execution units for executing an issue group of multiple instructions and scheduling logic configured to issue a first issue group of instructions to the first processor core for execution and a second issue group of instructions to the second processor core for execution when the processor is in a first mode of operation and configured to issue one or more vector instructions for concurrent execution on the first and second processor cores when the processor is in a second mode of operation.
    Type: Grant
    Filed: September 19, 2008
    Date of Patent: March 13, 2012
    Assignee: International Business Machines Corporation
    Inventor: David A. Luick
  • Patent number: 8127296
    Abstract: A system and method for performing a VM migration which manages a cluster of machines in a pool for live migration to the same feature set or behavior. In certain embodiments, machines within the pool can be configured to emulate a certain feature set to enable a VM migration amongst the similar pools. The emulation can be by either masking reporting of a feature set or enabling/disabling a feature set. The handling of emulation registers within the hardware occurs at a firmware level rather than an operating system or hypervisor level.
    Type: Grant
    Filed: September 6, 2007
    Date of Patent: February 28, 2012
    Assignee: Dell Products L.P.
    Inventors: Mukund Khatri, Robert Hormuth
  • Patent number: 8122229
    Abstract: A dispatch mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. According to certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable that are to be processed by the co-processor. For instance, in certain embodiments, a designated portion of memory (e.g., “UCB”) is utilized, wherein a host processor may place information in such UCB and the co-processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executable for processing by the co-processor. In certain embodiments, the co-processor may comprise dynamically reconfigurable logic which enables the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to be loaded onto the co-processor.
    Type: Grant
    Filed: September 12, 2007
    Date of Patent: February 21, 2012
    Assignee: Convey Computer
    Inventors: Steven J. Wallach, Tony Brewer
  • Publication number: 20120042151
    Abstract: A processor including a first execution core section clocked to perform execution operations at a first clock frequency, and a second execution core section clocked to perform execution operations at a second clock frequency which is different than the first clock frequency. The second execution core section runs faster and includes a data cache and critical ALU functions, while the first execution core section includes latency-tolerant functions such as instruction fetch and decode units and non-critical ALU functions. The processor may further include an I/O ring which may be still slower than the first execution core section. Optionally, the first execution core section may include a third execution core section whose clock rate is between that of the first and second execution core sections. Clock multipliers/dividers may be used between the various sections to derive their clocks from a single source, such as the I/O clock.
    Type: Application
    Filed: September 10, 2010
    Publication date: February 16, 2012
    Inventors: David J. Sager, Thomas D. Fletcher, Glenn J. Hinton, Michael D. Upton
  • Patent number: 8108879
    Abstract: A processor having multiple independent engines can concurrently support a number of independent processes or operation contexts. The processor can independently schedule instructions for execution by the engines. The processor can independently switch the operation context that an engine supports. The processor can maintain the integrity of the operations performed and data processed by each engine during a context switch by controlling the manner in which the engine transitions from one operation context to the next. The processor can wait for the engine to complete processing of pipelined instructions of a first context before switching to another context, or the processor can halt the operation of the engine in the midst of one or more instructions to allow the engine to execute instructions corresponding to another context. The processor can affirmatively verify completion of tasks for a specific operation context.
    Type: Grant
    Filed: October 27, 2006
    Date of Patent: January 31, 2012
    Assignee: NVIDIA Corporation
    Inventors: Lincoln G. Garlick, Dennis K. Ma, Paolo E. Sabella, David W. Nuechterlein
  • Patent number: 8086763
    Abstract: A class changing apparatus includes a link unit configured to be linked with a client device to transmit and receive data. The class change apparatus also includes a storage unit configured to store apparatus information including class information of the client device. The class changing apparatus further includes a control unit coupled to the link unit and the storage unit and controlling operations of the class changing apparatus including a class changing operation, wherein the class change operation includes transmitting at least one command including a command for rebranching into the selected class to the client device through the link unit and registering class information as changed class information in the storage unit in response to detecting a class change request.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: December 27, 2011
    Assignee: LG Electronics Inc.
    Inventors: Moo-Rak Choi, Kwang-Wook Lee, You-Sun Kim, Sung-Jea Ko