Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: A microprocessor includes multiple register files. In a single thread mode, the microprocessor allows a single thread to have access to multiple ones of the register files. In a multi-thread mode, each thread has access to respective ones of the register files. In the multi-thread mode, multiple threads are simultaneously executing. Circuitry and hardware are provided to facilitate the respective modes and to facilitate transitions between the modes.

Abstract: A interrupt controller includes specialized interfaces and controls for ARM7TDMI-type microcontroller cores. Such sends interrupt vectors and IRQ or FIQ interrupt requests to the processor depending on particular interrupts received. Wherein, THUMB program execution is more economical with program code space, and an interrupt service routine preamble is coded in ARM program code to cause a switch to THUMB program execution. The interrupt service routine preamble is shared amongst all the interrupt service routines to further economize on program code space.

Abstract: A decode unit comprises first and second decoders respectively connected to receive bit sequences of first and second predetermined lengths. The first and second decoders operate in parallel to generate respective outputs. A switch selects one of the outputs in dependence on an instruction mode of the processor which governs the length of the bit sequence which is actually required to be decoded.

Abstract: A central processing unit (CPU) is described including a register file and an execution core coupled to the register file. The register file includes a standard register set and an extended register set. The standard register set includes multiple standard registers, and the extended register set include multiple extended registers. The execution core fetches and executes instructions, and receives a signal indicating an operating mode of the CPU. The execution core responds to an instruction by accessing at least one extended register if the signal indicates the CPU is operating in an extended register mode and the instruction includes a prefix portion including information needed to access the at least one extended register. The standard registers may be general purpose registers of a CPU architecture associated with the instruction. The number of extended registers may be greater than the number of general purpose registers defined by the CPU architecture.

Abstract: An input/output controller that allows independent and configurable reduction of clock speeds to its embedded processors when they are not in use to save average power consumption. The processor clock speeds are restored when new input/output requests are received.

Abstract: A programmable pipeline depth controller is provided to control the number of instructions that begins execution within an instruction pipeline of an instruction processor within a predetermined period of time. The pipeline depth controller of the present invention includes a logic sequencer responsive to a programmable count value. Upon being enabled, the logic sequencer generates a pipeline control signal to selectively delay the entry of some instructions into the instruction pipeline so that the number of instructions that begins execution within the instruction pipeline during the predetermined period of time following the enabling of the logic sequencer is equal to the count value.

Abstract: The present invention is generally directed to an apparatus and method for accessing registers within a processor. In accordance with one embodiment, an apparatus and method are provided for a processor in which at least two separate indicia (such as register select lines, register bank identifiers, processor mode identifiers, etc.) are utilized to uniquely identify and access a processor register. In accordance with this embodiment, bit lines of the separate indicia are encoded into a single, mapped set of signal lines, and these encoded signal lines are used to access the register.

Abstract: There is provided a method of controlling a monitoring function of a processor, the processor being operable in at least two domains, comprising a first domain and a second domain, the first and second domains each comprising at least one mode, the method comprising the steps of: setting at least one control value, the at least one control value relating to a condition and being indicative of whether the monitoring function is allowable in the first domain; and only allowing initiation of the monitoring function in the first domain when the condition is present if its related control value indicates that the monitoring function is allowable. In some embodiments the first domain is a secure domain and the monitoring function is a debug or trace function.

Abstract: Disclosed is a method and apparatus for a unified RISC/DSP pipeline controller to control the execution of both reduced instruction set computer (RISC) control instructions and digital signal processing (DSP) instructions for a signal processor. The unified RISC/DSP pipeline controller is coupled to a program memory, a RISC control unit, and at least one signal processing unit. The program memory stores both DSP and RISC control instructions and the RISC control-unit controls the flow of operands and results between the signal processing unit and a data memory that stores data. The signal processing unit executes the DSP instruction. The unified RISC/DSP pipeline controller generates DSP control signals to control the execution of the DSP instruction by the signal processing unit and RISC control signals to control the execution of the RISC control instruction by the RISC control unit.

Abstract: A method and logical apparatus for managing thread execution within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process.

Abstract: An access transaction generated by a processor is configured using a configuration storage containing a configuration setting. The processor has a normal execution mode and an isolated execution mode. The access transaction has access information. Access to the configuration storage is controlled. An access grant signal is generated using the configuration setting and the access information. The access grant signal indicates if the access transaction is valid.

Abstract: A microprocessor chip and methods for execution by the microprocessor chip. Instruction pipeline circuitry has first and second correct modes for processing at least some instructions. A plurality of flags each correspond to a class of instruction occurring in the instruction pipeline circuitry. Pipeline control circuitry cooperates with the instruction pipeline circuitry, as part of the basic execution cycle of the computer, to maintain the value of the flags to record failures of an attempt to execute in the first mode two mode instructions of the corresponding respective instruction classes, to be triggered by a timer expiry to switch the value of the flags, thereby to switch the instruction pipeline circuitry from one of the processing modes to the other for the corresponding instruction class.

Abstract: Program instructions permit software management of a processor cache. The program instructions may permit a software designer to provide software deallocation hints identifying data that is not likely to be used during further program execution. The program instructions may permit a processor to evict the identified data from a cache ahead of other eviction candidates that are likely to be used during further program execution. Thus, these software hints provide for better use of cache memory.

Abstract: Instruction and data registers of processors of a multiprocessing computing system are joined and forked to allow processing in multiple modes of operation. When joined, the registers of the processors each contain a same piece of information, hence generating single instruction and data streams. In contrast, when forked, the registers of the processors contain different pieces of information, thereby generating multiple instruction and data streams. Additionally, information may be stored into partitions of memory and fetched and broadcast by processors local to the particular memory sections thereby resulting in a faster cycle time.

Abstract: An interface switching device is connected to a keyboard unit and a computer. Two data lines, a power-supply line, and a ground line, which are provided at the interface switching device, are respectively connected to a data line, a clock line, a power-supply line, and a ground line, which are provided at the keyboard unit. An unused line is connected to an identification line. At the computer, the unused line, and the power-supply line or the ground line, are short-circuited. When the interface switching device is connected, a keyboard is notified of a voltage as identification information which is fixed at a power-supply voltage or zero volts.

Abstract: An apparatus and a system may include a modal property indicator and an access module to receive the modal property indicator and to access a selected location based on a condition of the modal property indicator. An article may include data, which, when accessed, results in a machine performing a method including indicating a processor mode to a memory including a plurality of instructions and predecoding an instruction selected from the plurality of instructions according to the processor mode.

Abstract: In a processor executing plural instructions simultaneously, writin-destination-register numbers of the plural instructions to be executed simultaneously are compared, and kinds of operations to be executed by the plural instructions are changed in response to a comparison result. When the writing-destination-register numbers of the plural instructions are identical, a constant operation is applied to plural operation results obtained from the plural instructions to obtain an operation result and the operation result is written into the writing-destination-register instructed by the plural instructions. Results outputted from plural processing units are put together into one result and the result is stored in one register. Thus, register use efficiency and process efficiency are improved.

Abstract: Chip cards comprising a microprocessor and a memory are used for various applications. It is also desirable that such chip cards can be used for different applications. This requires a strict and reliable separation of the various user programs so that mutual accessing is not possible. This is achieved notably by subdivision into a system mode, in which all access rights are free, and a user mode which is adjusted by way of a given bit in the program status word. This mode bit controls inter alia a separation in the bus for the special function registers so that given registers are not accessible in the user mode. These registers may contain information enabling the access to given memory sections only, so that this access cannot be modified in the user mode.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: In one embodiment, techniques are disclosed for causing a programmable processor to process one instruction at a time. Single-step debugging may be performed by taking an exception after each instruction or by invoking emulation mode after each instruction. The particular single-step debugging technique may be based upon state of control bits, or may be based upon the processor's current mode of operation, or both.

Abstract: An apparatus and method are disclosed for runtime modification of called functions within a write-protected operating system. The access state of a processor is altered to allow modification of the function code, and a redirection to a hook function is inserted at a target entry point within the called function. The access state of the processor may then be restored, and the hook function is executed in place of or in conjunction with the called function.

Abstract: A storage array is described which is specifically adapted to support a specific set of instruction modes of a processor. A first set of storage cells have a write input and a single read output. Second and third sets of storage cells each have a write input and only two read outputs. A fourth set of storage cells each have a write input and only three outputs. All the write inputs are addressable in common by a single write address and the read outputs are individually selectable responsive to a read pointer.

Abstract: A multiprocessor digital amplifier system is disclosed. A first processor is configured to decode a digital signal from a digital signal source. A second processor configured to provide control signals to the first processor. An expansion unit for communicating instructions and data between the processors and a memory device has a first port coupled to the first processor and a second port coupled to the second processor. The expansion unit includes a state generator with circuitry for selecting one of the first and second ports for receiving a memory device access grant. The first and second ports may be granted access in accordance with a selected arbitration protocol. A duration of the memory device access grant selectably constitutes one of a preselected number of accesses and a preselected timeslice. An amplifier amplifies the decoded digital signal from the first processor.

Abstract: A processor supports a first processing mode in which the address size is greater than 32 bits. The address size may be nominally indicated as 64 bits, although various embodiments of the processor may implement any address size which exceeds 32 bits, up to and including 64 bits, in the first processing mode. The first processing mode may be established by placing an enable indication in a control register into an enabled state and by setting a first operating mode indication and a second operating mode indication in a segment descriptor to predefined states. Other combinations of the first operating mode indication and the second operating mode indication may be used to provide compatibility modes for 32 bit and 16 bit processing compatible with the x86 processor architecture (with the enable indication remaining in the enabled state). To call code operating in the first processing mode from the 32 bit or 16 bit code, a call gate descriptor is defined which occupies two entries in a segment descriptor table.

Abstract: In a computer system having a plurality of modules connected by a bus, wherein the plurality of modules includes a first module and wherein the system has a word width of two or more bytes, a system and method of byte swapping bytes within a word stored in a location on the first module. An address is constructed, wherein constructing an address includes inserting address bits pointing to the location and activating an attribute bit in the address indicating whether bytes within the word should be swapped. The address is driven on the bus and received at the first module. If the attribute bit is active, byte swapping the word.

Abstract: The present invention prevents, at high speed, a malfunction from occurring at the time of changing a mode in a processor, in which information to be decoded varies with modes. The processor is provided with a circuit for referring to a result of decoding information or issuing an instruction when a write operation is performed on a register for storing data containing a bit that indicates a current mode, and for outputting a purge signal if the result of decoding information or issuing an instruction is information represented by a mode switching signal. Thus, when a mode switching signal is written to the register, a purge signal is outputted to a cache memory. Consequently, the valid bit of prefetched cache data is turned off. This prevents prefetched data from being decoded in a different mode. As a result, operations are normally performed after the switching of the mode. Alternatively, the purge signal is outputted by detecting a change in the value of the bit indicating the current mode.

Abstract: A method of selecting registers is proposed, which is used to gain access to a register in a primitive register set which is used to provide a plurality of physical registers, virtual registers, physical program counters, and virtual program counters arranged into six modes. The primitive register set is first mapped to a converted register set which contains only two modes of registers that are mapped to the six modes of registers in the primitive register set. The access to the primitive register set is carried out by a bit sequence. If Converted Mode 0 in the converted register set is selected, the selection is mapped to one of the physical registers and physical program counter in the Converted Mode 0; and if Converted Mode 1 is selected, the selection is mapped to one of the virtual registers and virtual program counter in the Converted Mode 1.

Abstract: An example embodiment of a method and apparatus for dynamically changing computer system configuration to improve software application performance includes a system logic device that implements at least two different configurations. The system logic device may change configuration depending on what software application is running. The system logic device can change configurations while the computer system is running and may change configurations in order to optimize performance for whatever application is currently running.

Abstract: A decode unit (20) decodes instructions in a processor. These, instructions include instructions of a first length in a first instruction mode and instructions of a second, shorter length in a second instruction mode. The decode unit has decoding circuitry (50-60) which decode the instructions. A register holds the instruction mode and generates an instruction mode signal. Switching circuitry (MUX6,MUX7) is responsive to the instruction mode signal to output decoded instructions from the decode unit depending on the instruction mode. A detector (70) is provided for detecting a length change instruction of the second, shorter length while in the second instruction mode which indicates that the subsequent instruction is of the first length. The detector also temporarily alters the state of the instruction mode signal to allow the first length instructions to be decoded without changing the instruction mode held in the register.

Abstract: An electronic control apparatus for a control object makes a mode check before each program part is retrieved even at a predetermined start timing, and inhibits a retrieval of program parts unnecessary for operation modes including a normal mode, inspection mode or rewrite mode. As it is not necessary to check the mode in the processing of each program part, the control processing for the control object can be executed efficiently in each mode. As the program parts unnecessary for the specified operation mode is not retrieved either in the specified operation mode, the processing efficiency is increased.

Abstract: A floating point register stack for a processor combines a plurality of two general purpose registers to form a register stack for x86 instructions and leaves the remaining general purpose registers for native instructions of the processor. By mapping x86 sources into the stack of two general purpose registers and operating x86 instructions on the x86 stack, the register stack for the processor is able to support both the processor's native instruction set and the x86 instruction set without increasing the size of the register stack.

Abstract: The present invention provides a processor capable of operating in high reliability and high performance modes in response to mode switch events. Execution resources of the processor are organized into multiple execution clusters. An issue unit provides different instructions to the execution clusters in high performance mode. The issue unit provides the same instructions to the execution clusters in high reliability mode and results generated by the different execution clusters are compared to detect soft errors. The processor may be switched between the high reliability and high performance mode under software control or in response to the detection of certain conditions, such as the execution of certain types of process threads. These include process threads from the operating system kernel, process threads comprising uncacheable instructions, and machine check process threads.

Abstract: A data storage system having a plurality of disk drives. Each one has a pair of bi-directional ports. A pair of directors controls the flow of data to and from the disk drives. A first fiber channel port by-pass selector section is provided. The first fiber channel by-pass selector section includes: an input/output port coupled to a first one of the directors; and, a plurality of output/input ports connected between a first one of the ports of the plurality of disk drives through a first plurality of fiber channel links. The first fiber channel port by-pass selector section is adapted to couple the first one of the directors serially to one, or ones, of the first ports of the plurality of disk drives through a first fiber channel selectively in accordance with a control signal fed to the first fiber channel by-pass selector section. The first fiber channel includes one, or more, of the first plurality of fiber channel links.

Abstract: A microcomputer system and method of utilizing a repeated reset operation to enter the microcomputer system into different operating modes, particularly a microcomputer system without a keyboard, in which only a reset key is needed to set the required operating mode. The microcomputer system of the present invention comprises: a microcomputer; a memory connected to the microcomputer; a reset key to reset the microcomputer system; and a reset circuit to provide a power on reset pulse required in the microcomputer system or to receive the reset pulse produced by reset key. The microcomputer system checks both a specific memory area content for only a first specific value and a dedicated address content in the memory for a second specific value. If both only the first specific value in specific memory area and the second specific value in dedicated address are present, the microcomputer system is set to an abnormal operating mode. Otherwise, the specific value is written into the dedicated address in the memory.

Abstract: A processor is provided having dual execution cores that may be switched between high reliability and high performance execution modes dynamically, according to the type of code segment to be executed. When the processor is in high performance mode, the dual execution cores operate in lock step on identical instructions, and the execution results generated by each execution core are compared to detect any errors. In high performance monde, the dual execution cores operate independently.

Abstract: In a computer system the instruction decoding unit for translating program instructions to microcode instructions operates dynamically. Thus the unit receives state signals indicating the state of the computer, such as a trace enabling signal, influencing the translation process in the instruction decoding unit. These state signals are added to the operation code of the program instruction to be decoded, the operation code of the program instruction thus being extended and used as input to a translating table, the extended operation code of the program instruction being taken as an address of a field in the table. The addresses and thus the contents of the fields addressed for the same operation code of a program instruction can then be different for different values of the state signals. Thus generally, the state signals cause the instruction decoder to change its translating algorithm so that the decoder can decode an operation code differently depending on the state which the signals adopt.

Abstract: A processing architecture enables execution of one first set of instructions and one second set of instructions compiled for being executed by two different CPUs, the first set of instructions not being executable by the second CPU, and the second set of instructions not being executable by the first CPU. The architecture comprises a single CPU configured for executing both the instructions of the first set and the instructions of the second set. The single CPU in question being selectively switchable between a first operating mode, in which the single CPU executes the first set instructions, and a second operating mode, in which the single CPU executes the second set of instructions. The single processor is configured for recognizing a switching instruction between the first operating mode and the second operating mode and for switching between the first operating mode and the second operating mode according to the switching instruction.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: Chip cards comprising a microprocessor and a memory are used for various applications. It is also desirable that such chip cards can be used for different applications. This requires a strict and reliable separation of the various user programs so that mutual accessing is not possible. This is achieved notably by subdivision into a system mode, in which all access rights are free, and a user mode which is adjusted by way of a given bit in the program status word. This mode bit controls inter alia a separation in the bus for the special function registers so that given registers are not accessible in the user mode. These registers may contain information enabling the access to given memory sections only, so that this access cannot be modified in the user mode.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: In a digital signal processing unit, addressing apparatus implements a multiplicity of addressing modes. The addressing modes include a circular buffer memory mode, a frame mode, and a sorting mode. To increase the speed of the address modification, the index, the index in the presence of a positive wrap-around, and the index in the presence of negative wrap-around are determined together. Other apparatus determines the addressing mode and provides control signals for the selection of the correct index. The correct index is combined with the base address to provide the next new address.

Abstract: In accordance with methods and systems consistent with the present invention, an improved processor performance instrumentation system is provided that allows a software tester to measure more performance indicators than there are hardware counters during a single execution of a tested program. The improved processor performance instrumentation system accomplishes this by “multiplexing” performance indicators while executing the tested program. In effect, methods and systems consistent with the present invention extend the abilities of the limited number of hardware counters to allow them to measure a number of performance indicators otherwise not allowed during one execution of the tested program.

Abstract: An electronic switch is has a receiver for receiving external switch signal and to producing corresponding switch control signal. A decoder us provided to receive switch control signal from the receiver and to produce corresponding decoding signal containing a switch identification code. A memory stores at least one switch identification code, each switch PIN code corresponding to a respective switch element. A processor is provided to compare switch identification code from the decoder with switch PIN code in the memory and to turn on the corresponding switch element when the switch identification codes are matched. The processor has a learning mode for writing every received switch identification code from the decoder into the memory and corresponding every written switch PIN code to the at least one switch element respectively.

Abstract: An improved processor implementation is described in which scalar and vector processing components are merged to reduce complexity. In particular, the implementation includes a scalar-vector register file for storing scalar and vector instructions, as well as a parallel vector unit comprising functional units that can process vector or scalar instructions as required. A further aspect of the invention provides the ability to disable unused functional units in the parallel vector unit, such as during a scalar operation, to achieve significant power savings.

Abstract: A system for programming a periphery flash ROM is provided. The system in-cludes a host computer, an IDE interface, a flash controller, a flash ROM, and a micro-processor. The flash controller is coupled to the host computer through the IDE interface. The flash ROM and the microprocessor are also coupled to the flash controller. When the system enters a flash ROM programming mode, task files used between the IDE interface and the host computer are redefined by the host computer and is interpreted by the flash controller so that a firmware code from the host computer is written into the flash ROM through the flash controller. After the flash ROM is completely programmed, the task files return to their original definition. The microprocessor is required to disable the access to the flash ROM during the flash ROM programming mode.

Abstract: A method of selecting registers is proposed, which is used to gain access to a register in a primitive register set which is used to provide a plurality of physical registers, virtual registers, physical program counters, and virtual program counters arranged into six modes. The primitive register set is first mapped to a converted register set which contains only two modes of registers that are mapped to the six modes of registers in the primitive register set. The access to the primitive register set is carried out by a bit sequence. If Converted Mode 0 in the converted register set is selected, the selection is mapped to one of the physical registers and physical program counter in the Converted Mode 0; and if Converted Mode 1 is selected, the selection is mapped to one of the virtual registers and virtual program counter in the Converted Mode 1.

Abstract: A microcontroller system includes a security lock circuit to regulate access requests to contents of locations of a program memory. The regulation is selective, based on an operating mode of the security lock circuit, and also based on the source of the access request and the location of the program memory for which the access request is intended. Among other advantages, one major advantage provided by the security lock circuit is that concurrent programming (i.e., programming of one area of memory using instructions executing from another area of memory) can be initiated under predetermined secure conditions.

Abstract: A data processing system is provided that comprises a special-purpose processing unit (VU), a general-purpose processing unit that is suited to general-purpose data processing unit (PU) and a fetch unit for supplying a special-purpose instruction to the VU and supplying a general-purpose instruction to the PU, wherein the PU is equipped with a first mode for operating based on a first instruction from the fetch unit and a second mode for operating based on a second instruction from the VU. The resources of the PU are made available for use by the VU so that the resources of the PU can be used by the VU with effectively no overheads being required by the transfer of data between the VU and the PU. As a result, a processor with even greater flexibility and faster processing can be provided.

Abstract: Chip cards comprising a microprocessor and a memory are used for various applications. It is also desirable that such chip cards can be used for different applications. This requires a strict and reliable separation of the various user programs so that mutual accessing is not possible. This is achieved notably by subdivision into a system mode, in which all access rights are free, and a user mode which is adjusted by way of a given bit in the program status word. This mode bit controls inter alia a separation in the bus for the special function registers so that given registers are not accessible in the user mode. These registers may contain information enabling the access to given memory sections only, so that this access cannot be modified in the user mode.