Abstract: A processor element, structured to execute a 32-bit fixed length instruction set architecture, is backward compatible for executing a 16-bit fixed length instruction set architecture by translating each of the 16-bit instructions into a sequence of one or more 32-bit instructions. The 32-bit instruction set architecture includes “prepare to branch” instructions that allow target addresses for branch instructions to be set up in advance of the branch. The 32-bit prepare to branch and branch instructions are combined to execute a 16-bit branch instruction coupled with a 16-bit Delay Slot instruction.

Abstract: A method and apparatus for providing software compatibility in a processor architecture. In one embodiment, a method involves accessing a control register mask and adjusting a control value for a control register as a function of the control register mask. The masked control value is programmed into the control register.

Abstract: A tenant processor module is shown comprising a processor core, a plurality of strapping devices, and an input bus. The plurality of strapping devices are configured to indicate configuration information to a receiving circuit board assembly coupled to the processor module. The input bus, coupled to the processor core, receives the configuration information back from the circuit board assembly and provides them to the processor core at a first time. At a second time, the input bus receives operational data from the circuit board assembly and provides them to the processor core.

Abstract: A control unit that includes a processor having at least a first chip select output and a second chip select output. A signal provided by the first chip select output is activated during a normal operating mode of the control unit, and a signal provided by the second chip select output is activated during an application mode of the control unit. The control unit also includes a RAM memory having a chip select input for selecting the RAM memory and having a memory area for use as an application memory. A combination element electrically couples the signal provided by the first chip select output and the signal provided by the second chip select output to the chip select input of the RAM memory such that the signal provided by the first chip select output and the signal provided by the second chip select output do not have a perturbing effect on each other.

Abstract: A method and apparatus for transitioning a processor from a first mode of operation for processing a first instruction set architecture (instruction set) to a second mode of operation for processing a second set instruction set. The method provides that instructions of a first instruction set architecture (instruction set) are processed in a pipelined processor in a first mode of operation, and instructions of a second, different, instruction set, are processed in the pipelined processor in a second, different, mode of operation. While operating in one mode and before a switch to the other mode occurs, the pipeline is loaded with a set of instructions that transition the processor from one mode to the other, wherein the set of instructions are substantially insensitive to the mode that the processor operates in.

Abstract: A reconfigurable processing system executes instructions and configurations in parallel. Initially, a first instruction loads configurations into configuration registers. The configuration field of a subsequently fetched instruction selects a configuration register. The instruction controls and controls of the configuration in the selected configuration register are decoded and modified as specified by the instruction. The controls provide data operands to the execution units which process the operands and generate results. Scalar data, vector data, or a combination of scalar and vector data can be processed. The processing is controlled by instructions executed in parallel with configurations invoked by configuration fields within the instructions. Vectors are processed using a vector register file which stores vectors. A vector address unit identifies addresses of vector elements in the vector register file to be processed.

Abstract: A method and apparatus for allowing developers to develop software for their product. The method includes providing a first mode signal to a processor to operate in a development mode. The method also includes executing instructions stored in a first region of the memory in response to the first mode signal, providing data to the processor, and writing the data into a second region of the memory.

Abstract: A PCI interface is provided to support a 16- or 32-bit PCI host employing little-endian or big-endian byte ordering. The PCI interface may be arranged on a multiport switch to enable a PCI host to access internal registers and an external memory via a PCI bus. When a 16-bit PCI host is provided with access to a 32-bit internal register, two consecutive 16-bit data transfers are performed. The first 16 bits of data are temporarily stored in a holding register until the following 16 bits are transferred. The PCI host accesses the external memory via posting write buffers and prefetch read buffers arranged between an external memory interface and the PCI interface. When the multiport switch is configured to support a big-endian PCI host, bytes of a word transferred between the external memory and a write or read buffer are swapped to rearrange byte ordering of the word.

Abstract: An apparatus and method for changing privilege level in a processor configured to pipeline instructions are presented. The processor includes a first memory storing an architectural privilege level that is set at a first privilege level, a second memory storing a plurality of instructions, and a pipeline including a plurality of processing stages. A first instruction is fetched from the memory and a determination is made whether the first instruction requires the first privilege level be changed to a second privilege level, and in response thereto, any subsequent instructions are flushed from the pipeline before recording the second privilege level in the first memory.

Abstract: Power conservation without performance reduction in a power-managed system is disclosed. A method according to one embodiment of the invention includes three steps. In the first step, it is determined whether a computer program running on a computer is substantially memory-intensive or substantially compute-intensive. In a second step, the clock speed of the computer system is increased, and the number of memory access wait states of the computer system is adjusted incident to determining that the computer program is substantially compute-intensive. In a third step, the clock speed of the computer system is decreased, and the number of memory access wait states of the computer system is adjusted incident to determining that the computer program is substantially memory-intensive.

Abstract: Integrated circuitry comprises target circuitry and test circuitry. The target circuitry uses a clock signal to transfer a target signal within the integrated circuitry. The test circuitry samples the target signal at a selected time from a plurality of possible times within a clock cycle of the clock signal. The test circuitry samples the target signal in response to a test signal indicating the selected time.

Abstract: A dual mode branch and branch control system and method is disclosed for accommodating a processor that can operate in either of two operating modes, each using a different type of branch instruction. In a first instruction set, a first type branch instruction includes a separate branch instruction and a branch control instruction, while in the second instruction set, a second type branch instruction includes only a branch instruction. The processor is optimized to handle the first instruction set so that the branch instruction is arrangeable in a program sequence so that an execution unit in the processor can compute a branch target address based on the branch control instruction without a latency penalty. The first type branch instructions also include a folded-compare format, while the second type branch instructions have separated compare and branch instructions.

Abstract: A structure for a data object is disclosed with a field and format structure optimized for use by a set of pipeline stages that are interconnected logically through a common pipeline memory. The data object includes both a first portion containing data relating to one or more of a plurality of parameters associated with the control and/or the configuration of one or more processing circuitry blocks, and a second portion containing data associated with computations performed by the processing circuitry blocks. Other portions contain both general and specific types of operational control information used by the processing circuitry blocks. The data object acts as a form of common data exchange mechanism between disparate types of pipeline stages, including in hybrid (mixed) software-hardware pipelines. The control data in the data object can be used by a first pipeline stage to affect or adaptively change operational functioning of downstream pipeline stages.

Abstract: A central processing unit (CPU) for easily testing and debugging an application program, which includes a data communications unit for performing data communications with a host computer, a status register having a flag representing whether an operational mode of the CPU is a general operational mode representing a general operational state or a debugging mode representing a debugging state, a debugging stack pointer register which is used as a stack pointer designating a stack memory storing data of a debugging program, and a comparator for comparing a value stored in a break register with break data, wherein the CPU is converted into the debugging mode if the break register value is same as the break data, the flag of the status register has a value representing a debugging mode, a start address for performing a debugging program is loaded in a program counter, and the debugging program is executed to perform a debugging according to a command from the host computer via the data communications unit.

Abstract: A microcontroller system has a first and a second block of non-volatile programmable memory and includes a program memory space allocation circuitry. In a first mode of operation, the first and second blocks of programmable memory are prevented from being written by commands external to the microcontroller system. In a second mode, however, the first and second blocks of programmable memory are prevented from being written by commands external to the microcontroller system but the second block of programmable memory can be written based upon execution of commands stored in the first block of programmable memory. By having circuitry to so allocate the programmable memories, the security of the programmable memories is enhanced.

Abstract: A method of implementing a scaleable architecture for a communications system is disclosed, based on minimizing a total gate count for the communications system to reduce cost, complexity, etc. The method considers the requirements of particular communications transmission process that is dividable into individual transmission tasks. A computational complexity for each of said N individual transmission tasks respectively, said computational complexity being based on a number of instructions per second (MIPs) required by a computational circuit to perform each of said N individual transmission tasks; a number of gates and/or transistors required to implement each of individual transmission task using a hardware based or software based computing circuit, etc. After determining an effective number of MIPs acheivable by such circuits, the N tasks are allocated in a gate efficient manner for a final design architecture, or for a working implementation in the field.

Abstract: A microcomputer for feeding source data necessary for operations without any delay while retaining the consistency on instruction lines between the ordinary single operations and the SIMD (Single Instruction Multiple Data) type parallel operations. The microcomputer comprises: a first memory and a second memory adapted to be individually fed with a common address from the address generating unit; a first execution unit coupled to the first memory and the second memory; and a second execution unit coupled to the first memory and the second memory. The second execution unit is mounted together with the central processing unit, the first memory, the second memory and the first execution unit on a common semiconductor substrate.

Abstract: Disclosed is method and apparatus (20) for improving the performance of a pipeline system in which a FIFO (24) is incorporated in the pipeline between an upstream processing module (22) and a downstream processing module (26), each of the modules (22, 26) having access to a common external memory (32), this being typical in many ASIC arrangements. The method commences with detecting when the FIFO (24) is substantially full and transferring commands from the upstream module (22) to the external memory (32). Commands received by the downstream module (26) from each of the FIFO (24) and the external memory (32) are interpreted to determine a source of following ones of the commands.

Abstract: A data processing system and method of monitoring the performance of a data processing system in processing data requests, where said data processing system processes data requests within a multilevel memory hierarchy. At least one token is passed with a data request along a particular path within the multilevel memory hierarchy. The time duration for the token to completely pass along the particular path is stored if expected conditions are encountered along the particular path within the multilevel memory hierarchy, such that the performance of said data processing system requesting data along that particular path under the expected conditions is determined and is available for subsequent performance monitoring.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A method verifies that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically. In accordance with the present invention, a test suite written and compiled in big endian mode is loaded into memory. The test suite is converted to little endian mode and stored back to memory. Next, the processor status is changed from big endian mode to little endian mode, and the test suite is executed. Finally, the results of the test suite are examined to ensure that the processor properly executed the instructions in little endian mode.

Abstract: An instruction fetch unit 10 issues a normal ALU operating instruction or a wide ALU operating instruction using two operating units to a first pipeline 14. The instruction fetch unit 10 also issues a normal ALU operating instruction to a second pipeline 16. Occasionally, a wide ALU operating instruction using both a first integer unit 20 and a second integer unit 24 to the first pipeline 14 while a normal ALU operating instruction using the second integer unit 24 to the second pipeline 16. In this case, if the normal ALU operating instruction is earlier, then the normal ALU operating instruction is executed preferentially. If the wide ALU operating instruction is earlier, then the wide ALU operating instruction is executed preferentially.

Abstract: A RISC type microprocessor for implementing multi-stage pipeline processing. The RISC type microprocessor includes mode allocating means, interrupt controlling means and a jump instruction table. The mode allocating means is used for allocating a first mode for cyclically executing processes corresponding to a plurality of interrupts at predetermined intervals or a second mode for successively executing the processes corresponding to the interrupts. The interrupt controlling means is used for controlling the interrupts corresponding to the mode allocated by the mode allocating means, and is operable to save particular information to a stack upon occurrence of an interrupt and to fetch the particular information from the stack upon completion of the interrupt process. The jump instruction table is used in processing interrupts without stopping the multi-stage pipeline processing.

Abstract: A module is interposed between the operating system and/or applications of a data processing system and the device driver for a graphics adapter within the data processing system. The interposed module may selectively intercept all graphics device driver function requests or simply pass such requests to a device driver supporting specialized (e.g., non-VGA) graphics modes. Standard (e.g., VGA) graphics mode(s) device driver support is accessible to the interposed module. When a specialized graphics mode is selected, the interposed is inactive and passes graphics function requests to the specialized device driver. When a standard graphics mode is selected, the interposed module is active and intercepts all graphics function requests, processing such request with available standard graphics mode support. Change of the graphics mode from standard to specialized or vice versa results in the interposed module changing from active to inactive or vice versa.

Abstract: A pair of communications adapters each include a number of digital signal processors and network interface circuits for the attachment of a multi-channel telephone line. A bus connecting the communications adapters can carry data between a network line attached to one of the adapters and the digital signal processors of the other adapter. The digital signal processors on each card are connected to a host, or controller, processor. Each digital signal processor interrupts its host processor by transmitting an interrupt control block as data to a data memory of the host processor, and by subsequently sending an interrupt causing the host processor to examine the data memory. Preferably, the interrupt control block includes data representing a number of requested interrupts.

Abstract: A microprocessor circuit arrangement is capable of retrieving and executing program instructions from a program memory having one of multiple possible bit-widths using address signals. A microprocessor uses a set of program instructions to select a memory configuration for retrieving the program instructions. The program memory stores the set of program instructions such that the microprocessor can retrieve the set of program instructions regardless of which bit-width is used to store the set of program instructions. Additional circuitry maps the address signals for retrieving the program instructions from the program memory.

Abstract: A system and method for thermal overload detection and protection for a processor which allows the processor to run at near maximum potential for the vast majority of its execution life. This is effectuated by the provision of circuitry to detect when the processor has exceeded its thermal thresholds and which then causes the processor to automatically reduce the clock rate to a fraction of the nominal clock while execution continues. When the thermal condition has stabilized, the clock may be raised in a stepwise fashion back to the nominal clock rate. Throughout the period of cycling the clock frequency from nominal to minimum and back, the program continues to be executed. Also provided is a queue activity rise time detector and method to control the rate of acceleration of a functional unit from idle to full throttle by a localized stall mechanism at the boundary of each stage in the pipe.

Abstract: A data processing system which executes pipeline processing that decodes a subsequent instruction in an execute phase of a current instruction in response to a clock signal. The data processing system includes a CPU and a mode management block. The CPU supplies an address bus with at least one predetermined address in an execute phase of a clock supply stop instruction. The mode management block produces a clock stop signal if the predetermined address agrees with a self-address assigned to the management block in advance, thereby halting the supply of the clock signal. This makes it possible to solve a problem of a conventional data processing system in that it executes the instruction next to the clock supply stop instruction in spite of execution of the clock supply stop instruction because the clock stop signal is actually output when the clock supply stop instruction shifts from the execute phase to the write back phase, in which case the next instruction proceeds in the execute phase.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.

Abstract: A complexity-adaptive hardware/software system and method for a microprocessor to execute any of a plurality of diverse applications according to a predetermined instruction set architecture. The system includes dynamic hardware structures and configurable clocking system of the microprocessor for executing any particular application among the plurality of diverse applications, the dynamic hardware structures and configurable clocking system being adaptable to be organized in any of a plurality of potential configurations which are selectable according to the particular application to be executed. Configuration control is performed in response to the particular application to be executed, the instruction set architecture, and the potential configurations in which the dynamic hardware structures and configurable clocking system may be organized.

Abstract: In a data processing apparatus, a decoding unit decodes instructions. A calculator operates N-bit data in accordance with the decoded results. A flag storage unit stores a plurality of flag groups which are changed in correspondence to data having different widths, based on the operated results. Selectors select a predetermined flag group in accordance with the direction of a conditional branch instruction. A branch judging unit judges whether a branch is taken or not by referring to the selected flag group.

Abstract: Dynamically typed registers in a processor are provided by associating a type specifier with a register specifier for each register in the processor, storing the register specifiers and associated type specifiers in a register type table. The type specifier associated with an operand register of an instruction is employed to dispatch the instruction to an appropriate execution unit within the processor. The results of the instruction are stored in a register having an associated type specifier matching the execution unit type. Register specifiers are dynamically allocated to particular execution units within the processor by altering the type specifier associated with the register specifiers. Register values may be either discarded or converted when the register specifier type is altered. A general instruction allows conversion of the value from one type to another without storing the converted value in memory.

Abstract: A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.

Abstract: A digital signal processor which supports an instruction set including both 16-bit instructions and 32-bit instructions, so that particular portions of a program requiring only 16-bit instructions may be encoded in a 16-bit mode, thus reducing the program memory needed to store these portions. The digital signal processor switches between the 16- and 32-bit modes only in response to flow control instructions such as JUMP, CALL or RETURN instructions. JUMP and CALL instructions are coded to indicate the processor mode applicable to the instructions to which the JUMP or CALL instruction goes to, so that the processor may change modes as needed when executing the JUMP or CALL instruction. When a CALL is executed the current processor mode is stored on the processor's stack, so that in response to a RETURN instruction the processor can return to this mode by retrieving the stored mode from the stack.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: In the CIS installation area of a PC card, the A region contains the basic attribute information of the card, the B region contains data of CIS1 for a modem, and the C region contains CIS2 for an ATA memory. The PC card is provided with a selection signal input means which selectively designates the CIS. A selection signal discriminator receives a signal from the selection signal input means and determines the selective designation of the CIS. When CIS1 and CIS2 are selectively designated together, a CIS switch setting element sets the start of the CIS read-in by a personal computer to the leading address of CIS1, and when CIS2 only is selectively designated, it switchably sets the start of the CIS read-in by the personal computer to the leading address of CIS2.

Abstract: A method and apparatus for providing a programmable logic datapath that may be used in a field programmable device. According to one aspect of the invention, a programmable logic datapath is provided that includes a plurality of logic elements to perform various (Boolean) logic operations. The programmable logic datapath further includes circuitry to selectively route and select operand bits between the plurality of logic elements (operand bits is used hereinafter to refer to input bits, logic operation result bits, etc., that may be generated within the logic datapath). In one embodiment, by providing control bits concurrently with operand bits to routing and selection (e.g., multiplexing) circuitry, the programmable logic datapath of the invention can provide dynamic programmability to perform a number of logic operations on inputs of various lengths on a cycle-by-cycle basis.

Abstract: It is an object of the present invention to provide a one-chip microcomputer which permits the access time for an external memory to be equal to that for an internal memory. The one-chip microcomputer 10 includes an internal ROM 11, control circuit 12, output terminals 13, input terminals 14, control circuit 15, selector 16, instruction register 17, delay circuit 18, and fetch control signal select gate 19. For selection of the external ROM 30, a control arrangement 20 and a delay circuit 18 are employed in one embodiment to adjust the time at which ROM data is fetched by the instruction register 17, based on the delay time for accessing the external ROM 30.

Abstract: A data processor of the invention includes plural memories, plural arithmetic units, a data transfer unit and a network. The data transfer unit transfers various data to predetermined memories, and switches the connections between the memories and the arithmetic units by using the network. The control unit adds a processability judgement signal to a data read from a predetermined memory in reading the data, so as to make a pair of the data and the processability judgement signal. Each of the arithmetic units receives the data and the processability judgement signal, conducts predetermined processing on the received data, delays the received processability judgement signal by the number of cycles equal to its own processing cycle, and outputs resultant data obtained through the processing and the delayed processability judgement signal.

Abstract: A method for performing 16 Bit BIOS interrupt calls under a 32 Bit protected mode application. This has been impossible to-date and has forced BIOS development teams to add support into the BIOS for 32 bit function calls from 32 bit applications.

Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset.

Abstract: The data processing system includes a plurality of execution units forming a plurality of processing pipelines. The plurality of processing pipelines process instructions and include a storage pipeline. The data processing system further includes an instruction unit and a storage control unit. The instruction unit outputs instructions to the plurality of execution units, and controls execution of multiple threads by the plurality of execution units. If an instruction for a first thread in the storage pipeline experiences a cache miss and the instruction unit decides to switch threads, the instruction unit begins processing a second thread. The instruction unit also issues a data request to the storage control unit to obtain the missing data. During processing of the second thread, unused slots will appear in the storage pipeline because it is not possible to always dispatch instructions to completely keep the pipelines filled.

Abstract: A programmable cryptographic system (100) provides high performance cryptographic processing support for cryptographic algorithms. Two or more independent cryptographic algorithms may be performed at the same time through the processes of background staging and algorithm multi-tasking. A four stage software instruction pipeline and dynamically programmable function units support high performance cryptographic processing performance on the order of 60 mega bits per second (Mbps) aggregate throughput.

Abstract: A parallel processing system or processor has a computing architecture including a plurality of execution units to repeatedly distribute instruction streams within the processor via corresponding buses, and a series of processing units to access the buses and selectively execute the distributed instruction streams. The execution units each retrieve an instruction stream from an associated memory and place the instruction stream on a corresponding bus, while the processing units individually may select and execute any instruction stream placed on the corresponding buses. The processing units autonomously execute conditional instructions (e.g., IF/ENDIF instructions, conditional looping instructions, etc.), whereby an enable flag within the processing unit is utilized to indicate occurrence of conditions specified within a conditional instruction and control selective execution of instructions in response to occurrence of those conditions.

Abstract: A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA).

Abstract: A single chip microprocessor or memory device has reprogrammable characteristics according to the invention. In the case of the microprocessor, a fixed processing cell is provided as is common to perform logic calculations. A portion of the chip silicon real-estate, however, is dedicated a programmable gate array. This feature enables application-specific configurations to allow adaptation to the particular time-changing demands of the microprocessor and provide the functionality required to best serve those demands. This yields application acceleration and in system-specific functions. In other cases the configurable logic acts as network interface, which allows the same basic processor design to function in any environment to which the interface can adapt.The invention also concerns a memory device having a plurality of memory banks and configurable logic units associated with the memory banks. An interconnect is provided to enable communication between the configurable logic units.

Abstract: A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowledge special cycle in response to a request by the computer system to slow down its clock. This request is asserted by the computer system if the system has been idle for a predetermined period of time. The halt special cycle is generated by the microprocessor when a HALT instruction is executed. The stop grant acknowledge and halt special cycles place the microprocessor into a low power state. Since the microprocessor is in low power mode, the L2 cache memory is also placed into low power mode for further power conservation. The L2 cache memory is implemented either with synchronous or asynchronous static random access memories (SRAMs).

Abstract: A chip includes a programmable logic device and a microprocessor, wherein at least one of the associated registers of the microprocessor is distributed in the programmable logic device. The distributed register is coupled to both the microprocessor and the programmable logic device. In this manner, the microprocessor has the ability to access the register and place a value into the programmable logic device all in one clock cycle. Additionally, the logic functions in the programmable logic device are also advantageously available to the microprocessor.

Abstract: A 32-bit processor control unit receives from a memory an instruction. The control unit then determines whether the received instruction is intended for a 32-bit processor or for a 16-bit processor. If the received instruction is analyzed to be a 32-bit processor instruction, the control unit controls the 32-bit processor with the aid of two 16-bit instruction control units. If the received instruction is a 16-bit processor instruction, the 32-bit processor control unit sends a 16-bit processor mode signal to each of the 16-bit instruction control units. One of the two 16-bit instruction control units controls one of two 16-bit processors which are divisions of the 32-bit processor while the other 16-bit instruction control unit controls the other 16-bit processor. The present invention makes it possible to have a single, wide bitwidth processor serve as a plurality of narrow bitwidth processors depending upon the type of processing.

Abstract: A program driver means is disclosed that allows for the exchange of inforion between a NTDS device and a device having a bus topology, especially a VMEbus. The program driver utilizes chain commands which are fully programmable at the user level. The processor itself is programmed at the register level to assure the fastest data rate possible (32 bit access) across the VMEbus. The processor driver is invisible to the user.