Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

Abstract: A method and circuit arrangement utilize a general purpose processing unit having a low power DSP mode for reconfiguring the general purpose processing unit to efficiently execute DSP workloads with reduced power consumption. When in a DSP mode, one or more of a data cache, an execution unit, and simultaneous multithreading may be disabled to reduce power consumption and improve performance for DSP workloads. Furthermore, partitioning of a register file to support multithreading, and register renaming functionality, may be disabled to provide an expanded set of registers for use with DSP workloads. As a result, a general purpose processing unit may be provided with enhanced performance for DSP workloads with reduced power consumption, while also not sacrificing performance for other non-DSP/general purpose workloads.

Abstract: A processor performance state optimization includes a system to change a performance state of a processor. In an embodiment, the system to change a performance state of the processor includes a processor and a step logic sub-system operatively coupled with the processor and is operable to communicate a performance state change request to the processor. A core voltage regulator is operatively coupled with the step logic sub-system. An end performance state sub-system to determine a desired end performance state is coupled with the step logic sub-system. And, an enable sub-state transition sub-system to enable sub-state transitions is coupled with the step logic sub-system.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a plurality of graphics engines each to independently perform graphics operations; and, a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a power excursion control logic to limit a power consumption level of the processor from being above a defined power limit for more than a duty cycle portion of an operating period. Other embodiments are described and claimed.

Abstract: A system and method(s) for conserving vehicle power when a primary power system of a vehicle is powered down during a voice call. The method includes the steps of: (a) receiving an indication that the vehicle's primary power system is powered down during the voice call; (b) after a predetermined period of time, determining whether to power down a secondary power system associated with a vehicle telematics system; (c) when it is determined that the secondary power system should be powered down, powering down the secondary power system; and (d) when it is determined that the secondary power should not be powered down, waiting the predetermined period of time before again determining whether to power down the secondary power system. The determination of steps (b) and (d) include detecting an absence of voice activity during the predetermined period of time of steps (b) or (d).

Abstract: The described embodiments comprise a computing device with a first processor core and a second processor core. In some embodiments, during operations, the first processor core receives, from the second processor core, an indication of a memory location and a flag. The first processor core then stores the flag in a first cache line in a cache in the first processor core and stores the indication of the memory location separately in a second cache line in the cache. Upon encountering a predetermined result when evaluating a condition for the indicated memory location, the first processor core updates the flag in the first cache line. Based on the update of the flag, the first processor core causes the second processor core to perform an operation.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response, to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: A multi-element device includes a plurality of memory elements, each of which includes a memory array, access circuitry to control access to the memory array, and power control circuitry. The power control circuitry, which includes one or more control registers for storing first and second control values, controls distribution of power to the access circuitry in accordance with the first control value, and controls distribution of power to the memory array in accordance with the second control value. Each memory element also includes sideband circuitry for enabling a host system to set at least the first control value and the second control value in the one or more control registers.

Abstract: A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing a plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal.

Abstract: A current controller for generating a control signal which controls supply current flowing from a power source to a load includes an interface circuit which sets a threshold based on an instruction from an outside of the current controller, a threshold setting circuit which stores and outputs the threshold, a sensing circuit which determines a current or a temperature of a sensing element, and outputs a signal indicating that the supply current should be interrupted as the control signal if a determined current or a determined temperature exceeds the threshold, and a sensing control circuit which generates a clock signal including pulses with a predetermined period. The sensing circuit determines the current or the temperature of the sensing element during an active period of the clock signal.

Abstract: Attenuation systems have cooling components that produce power in response to heat generated by the attenuator. The cooling components can be used to power cooling fans if a primary power source of the fans fails.

Abstract: Systems, methods, and other embodiments associated with wake-on-frame mechanisms are described. According to one embodiment, an apparatus includes a packet source configured to send packets to a frame processing device and a wake-on-frame mechanism that is selectable by the frame processing device between an enabled state and a disabled state. If the wake-on-frame mechanism is in the enabled state, a packet source that has a frame to send to the frame processing device sends a wake signal to the frame processing device prior to sending the packet. The packet source sends the packet to the frame processing device after receiving a ready signal from the frame processing device.

Abstract: An access detection section detects access to an access object circuit and outputs a signal which restricts switching the access object circuit from a first operation state to a second operation state (low power consumption operation state) in which power consumption is lower than power consumption in the first operation state (normal operation state) until no-access period which lasts from last access to next access reaches a first period. An operation control section controls operation of the access object circuit according to the output of the access detection section.

Abstract: Various aspects provide for implementing a cache coherence protocol. A system comprises at least one processing component and a centralized controller. The at least one processing component comprises a cache controller. The cache controller is configured to manage a cache memory associated with a processor. The centralized controller is configured to communicate with the cache controller based on a power state of the processor.

Abstract: Systems, methods, and other embodiments associated with a processor configured with a zero power hibernation/sleep mode during which the processor consumes no power are described. According to one embodiment, a processor includes a power management logic. The power management logic is configured to receive a control signal requesting the processor to transition into a power saving mode that reduces power to the processor while retaining a current state of the processor. The power management logic is configured to store, in response to the control signal, a current state of components of the processor in a non-volatile memory. The power management logic is configured to adjust power to the processor to a zero power mode to place the processor into the power saving mode, wherein during the zero power mode the processor is receiving no power.

Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract: This disclosure relates to an apparatus and method for managing the memory of a mobile terminal. The mobile terminal includes a main system that operates with normal power, and a subsystem that operates with low power. The subsystem operates at least one feature of the mobile terminal while the main system is in a sleep mode. Binary data may be used to operate the at least one feature of the mobile terminal. When binary data is stored in memory operatively coupled to the main system, the binary data is retrieved and copied to memory operatively coupled to the subsystem, allowing the subsystem to operate the feature while the main system is in sleep mode.

Abstract: A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

Abstract: An image forming apparatus has the following three power saving modes: (1) a first power saving mode for cutting off power supply to the load; (2) a second power saving mode for cutting off power supply to the load and setting at least the CPU of the controller to STR state; and (3) a third power saving mode for providing power supply only to a wireless LAN module and the power supply cutoff controller, wherein to recover the image forming apparatus from the power saving mode, an external terminal implements both a second method of transmitting a certain type of packet to the wired LAN module and a third method of transmitting a certain type of packet to the wireless LAN module when the external terminal accesses the image forming apparatus at the application level.

Abstract: A method for a near field communication circuit includes entering a low power mode and subsequently determining to exit the low power mode. The method further includes generating an open loop clock signal and providing the open loop clock signal to circuits of the near field communication circuit during a low power mode exit duration. Subsequently a reference clock signal is received from a host and used to clock the near field communication circuit.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: A display device includes a display panel including a gate line, a data line, and a pixel connected to the gate line and the data line, a data driver connected to the data line, a gate driver connected to the gate line, and a signal controller controlling the data driver and the gate driver, wherein a circuits powering power source voltage that is normally used for driving the data driver is selectively not applied during a new-image blanking time when the signal controller is not supplying image data to the data driver.

Abstract: An Ethernet passive optical network over coaxial (EPOC) system rate mechanism. A network device is provided that includes a physical layer device (PHY) that is configured for coupling to a coaxial cable, a medium independent interface that facilitates data transmission at 10 Gbit/s or greater, and a reconciliation sublayer that is coupled to the PHY via the medium independent interface. The reconciliation sublayer has a codeword detector that is configured to detect a reserved codeword that is received from the PHY over the medium independent interface. The codeword detector can be configured to forward a rate control signal to a media access control (MAC) based on the detection of the reserved codeword.

Abstract: A controller includes a low power processor to couple to a sensor, the low power processor configured to receive data from the sensor and apply rules to the received data and provide an interrupt in accordance with the applied rules. A high power processor is coupled to receive interrupts from the low power processor in a sleep mode, to wake upon receipt of the interrupt, and to receive and process the data to determine actions to take based on the data, wherein the high power processor initiates the actions.

Abstract: In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for the graphics process in order to allocate performance resources to the graphics process and in some cases, between the graphics process and a central processing unit.

Abstract: Disclosed is a palm gesture recognition method comprising a step of obtaining plural images according to an order of time; a step of acquiring plural palm shaped images from the plural images; a step of extracting plural features describing an open or closed palm gesture from each of the plural palm shaped images; a step of calculating a maximum feature difference vector formed by a maximum difference of each of the plural features; and a step of determining, on the basis of the maximum feature difference vector, that there is the open or closed palm gesture or there isn't the open or closed palm gesture in the plural images.

Abstract: A low-power mode for interfaces, such as secure digital input/output (SDIO) interfaces, is described. The low-power mode provides significant power savings while allowing rapid resumption of data transfer on the interface. The SDIO low-power mode gates an SDIO clock and transitions the SDIO bus to a 1-bit mode. One line of the bus carries the 1-bit data while another line carries interrupts from an SDIO peripheral. Normal data transmission results in enabling the SDIO clock and setting the bus set to the 4-bit mode.

Abstract: Various embodiments of the present disclosure are directed to managing load steps caused by processing circuitry. The processing circuitry may generate a series of clock pulses at an average clock period. The processing circuitry may estimate a current consumption of the processing circuitry at each clock pulse. Accordingly, a clock pulse from the series of clock pulses may be omitted when a change in the current consumption exceeds a predetermined threshold amount, thereby increasing the average clock period.

Abstract: A system-on-chip including a host interface module configured to interface the system-on-chip to a host processor of a wireless device and to communicate with the host processor of the wireless device via a bus. The bus uses an application programming interface of the system-on-chip. The host processor uses the application programming interface to configure a power save mode of the system-on-chip. A power management module operated the system-on-chip in the power save mode without performing a handshake with the host processor via the bus in response to the host processor stopping communication with the system-on-chip. The handshake includes (i) sending a request to enter the power save mode to the host processor via the bus and (ii) receiving an acknowledgement of the request from the host processor via the bus.

Abstract: Methods and apparatus are disclosed to manage power consumption at a graphics engine. An example method to manage power usage of a graphics engine via an application level interface includes obtaining a policy directive for the graphics engine via the application level interface, the policy directive identifying a threshold corresponding to power consumed by the graphics engine operating in a first graphics state. The example method also includes determining a power consumed by the graphics engine during operation. The example method also includes comparing the power consumed to the threshold of the policy directive, and when the threshold is met, setting the graphics engine in a second graphics state to cause the graphics engine to comply with the policy directive.

Abstract: In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

Abstract: In an embodiment, a mobile device includes a sensor processor system, an application processor system and a power management controller that controls power being applied to the application processor system. The sensor processor system monitors sensors connected to the mobile device. The sensor processor system detects a pre-defined gestures and an environmental condition or event based on the monitoring. The pre-defined gesture corresponds to one or more actions initiated by a user of the mobile device (e.g., the user jogs with the mobile device, places the mobile device in his/her pocket or backpack, etc.). The sensor processor system selects a power profile to be applied to the application processor system based on the detection, and instructs the power management controller to apply the selected power profile to the application processor system.

Abstract: In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the core clock signal based on the determined operating frequency. Other embodiments are described and claimed.

Abstract: A management node at first extracts free computation nodes executing none of jobs in order to assign a new job to any one of computation nodes, and specifies a communication target computation node when executing an execution target job. Subsequently, the management node calculates, with respect to all of the computation nodes executing none of the jobs at that point of time, a determination value Vi on the basis of a power saving mode transition rate Si and an average value Di of distance counts from the communication target node, and specifies the free computation node having the maximum determination value Vi as the execution target job assignment destination.

Abstract: An exemplary low power consumption circuit includes a microprocessor, a power supply switch module and a main circuit module. The microprocessor is capable of outputting a power control signal and changing a pulse characteristic of the power control signal when the microprocessor switches from a first working mode to a second working mode. The power supply switch module is capable of outputting a power supply signal. The power supply switch module is electrically coupled to the microprocessor to receive the power control signal and thereby modulates a duty cycle of the power supply signal according to a change of the pulse characteristic of the power control signal. The main circuit module is electrically coupled to the power supply switch module to receive the power supply signal and operative with energy provided by the power supply signal. Moreover, a method for reducing power consumption is also provided.

Abstract: A request for a high voltage mode is received and a high voltage timer is started in response to determining that a remaining amount of high voltage credits exceeds a voltage switch threshold value. A switch to the high voltage mode is made in response to the request. A low voltage mode is switched to in response to an indication. The request may be received from an application running on a data processing system. If the indication is that the high voltage timer has expired, a low voltage timer is started in response to switching to low voltage mode. If the high voltage request is still active when the low voltage timer expires, a switch back to high voltage mode occurs and a new high voltage timer is started.

Abstract: A method, apparatus or stored program for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer, in which the usage of the CPU is measured, so that the clock throttle rate of the CPU can be automatically adjusted on the measured usage of the CPU, thereby reducing the consumption of electric power without any influence on the performance of the computer.

Abstract: A touch sensing device is provided. The touch sensing device includes a multiplexer and a control unit, and is electrically connected to a touch panel. The touch panel includes a plurality of first-direction electrodes; a plurality of second-direction electrodes; and a dielectric layer, for generating at least one electric field change corresponding to at least one touch point in response to the at least one touch point. The at least one electric field change is generated at an overlapping region of the first-direction and second-direction electrodes. The multiplexer is electrically connected to the touch panel via the first-direction and second-direction electrodes, and selectively performs voltage driving or voltage sensing for the first-direction and second-direction changes a control signal to be transmitted to the multiplexer and receives a sense signal from the multiplexer.

Abstract: A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated.

Abstract: Methods, apparatuses, and computer program products for real-time temperature sensitive machine level code compilation and execution are provided. Embodiments include compiling and executing, by a just-in-time (JIT) compiler, machine level code; during execution of the machine level code, determining, by the JIT compiler, an execution temperature for the machine level code, including reading temperature measurements from one or more processor temperature sensors; based on the determined execution temperature, identifying, by the JIT compiler, a portion of the machine level code that, when executed, caused temperature measurements of one or more processor temperature sensors to exceed a predetermined threshold temperature; recompiling, by the JIT compiler, the machine level code including modifying the identified portion to generate a new execution temperature that is lower than the previously determined execution temperature; and executing, by the JIT compiler, the recompiled machine level code.

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation circuit to receive and distribute a first clock signal at a first operating frequency provided from a phase lock loop of the processor to a plurality of units of the core. The clock generation circuit may include a dynamic clock logic to receive a dynamic clock frequency command and to cause the clock generation circuit to distribute the first clock signal to at least one of the units at a second operating frequency. Other embodiments are described and claimed.

Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.

Abstract: Method and apparatus are provided for thermal management of mobile devices. In one novel aspect, a micro-throttle method is used to control the fast rising temperature for the device. In one embodiment, the thermal management method determines a temperature of the mobile device and compares the temperature with a plurality of predefined temperature thresholds. The thermal management applies a first micro-throttle solution upon detecting the temperature reaches a first predefined temperature threshold and applies a second micro-throttle solution upon detecting the temperature reaches a second predefined temperature threshold. In one embodiment, the first and the second micro-throttle solution control the slope of the rising temperature to be below a first predefined slope and a second predefined slope, respectively. In one embodiment, the temperature is controlled by adjusting the operating frequency or voltage of at least one heat-generating components of the mobile device.

Abstract: An information processing apparatus has a sub system that, while a main system is in power saving state, analyzes a protocol of a network communication and recovers the main system to an ordinary power mode from the power saving state, in accordance with the protocol. There is a setting unit that sets a re-transition condition which is a condition to make the main system switch to the power saving state again, depending on a kind of the network communication. Further, there is a control unit that monitors whether the re-transition condition is satisfied and switches the main system to the power saving state in response to the re-transition condition being satisfied.

Abstract: Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response, to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.