Abstract: A semiconductor device 1 includes a clock generation circuit 15 that changes a frequency of an output clock signal according to a control signal div, an arithmetic circuit (e.g., CPU0) that operates according to the clock signal, a storage circuit (e.g., IC0) that is activated according to access from the arithmetic circuit CPU0, a memory access detection unit 12 that detects a number of accesses from the arithmetic circuit CPU0 to the storage circuit IC0, and when the number of accesses increases, outputs a request signal (e.g., psreq1), and a clock control circuit 14 that generates the control signal div for lowering the frequency of the clock signal according to the request signal psreq1.

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

Abstract: A semiconductor apparatus according to the present invention includes a circuit including a predetermined function, a clock generating circuit that generates a clock signal supplied to the circuit, a clock control circuit that controls the clock generating circuit, and a notification signal generating circuit that generates a notification signal for notifying a timing for the clock control circuit to control the clock generating circuit. A voltage supplied to the semiconductor apparatus is adjusted according to the notification signal.

Abstract: This disclosure relates to an apparatus and method for managing the memory of a mobile terminal. The mobile terminal includes a main system that operates with normal power, and a subsystem that operates with low power. The subsystem operates at least one feature of the mobile terminal while the main system is in a sleep mode. Binary data may be used to operate the at least one feature of the mobile terminal. When binary data is stored in memory operatively coupled to the main system, the binary data is retrieved and copied to memory operatively coupled to the subsystem, allowing the subsystem to operate the feature while the main system is in sleep mode.

Abstract: Methods, systems and devices that include a dynamic clock and voltage scaling (DCVS) solution configured to compute and enforce performance guarantees for a group of processors to ensure that the processors does not remain in a busy state (e.g., due to transient workloads) for a combined period that is more than a predetermined amount of time above that which is required for one of the processors to complete its pre-computed steady state workload. The DCVS may adjust the frequency and/or voltage of one or more of the processors based on a variable delay to ensure that the multiprocessor system only falls behind its steady state workload by, at most, a predefined maximum amount of work, irrespective of the operating frequency or voltage of the processors.

Abstract: An image forming apparatus has the following three power saving modes: (1) a first power saving mode for cutting off power supply to the load; (2) a second power saving mode for cutting off power supply to the load and setting at least the CPU of the controller to STR state; and (3) a third power saving mode for providing power supply only to a wireless LAN module and the power supply cutoff controller, wherein to recover the image forming apparatus from the power saving mode, an external terminal implements both a second method of transmitting a certain type of packet to the wired LAN module and a third method of transmitting a certain type of packet to the wireless LAN module when the external terminal accesses the image forming apparatus at the application level.

Abstract: A method for a near field communication circuit includes entering a low power mode and subsequently determining to exit the low power mode. The method further includes generating an open loop clock signal and providing the open loop clock signal to circuits of the near field communication circuit during a low power mode exit duration. Subsequently a reference clock signal is received from a host and used to clock the near field communication circuit.

Abstract: A system-on-chip bus system includes a bus configured to connect function blocks of a system-on-chip to each other, and a clock gating unit connected to an interface unit of the bus and configured to basically gate a clock used in the operation of a bus bridge device mounted on the bus according to a state of a transaction detection signal.

Abstract: A display device includes a display panel including a gate line, a data line, and a pixel connected to the gate line and the data line, a data driver connected to the data line, a gate driver connected to the gate line, and a signal controller controlling the data driver and the gate driver, wherein a circuits powering power source voltage that is normally used for driving the data driver is selectively not applied during a new-image blanking time when the signal controller is not supplying image data to the data driver.

Abstract: An Ethernet passive optical network over coaxial (EPOC) system rate mechanism. A network device is provided that includes a physical layer device (PHY) that is configured for coupling to a coaxial cable, a medium independent interface that facilitates data transmission at 10 Gbit/s or greater, and a reconciliation sublayer that is coupled to the PHY via the medium independent interface. The reconciliation sublayer has a codeword detector that is configured to detect a reserved codeword that is received from the PHY over the medium independent interface. The codeword detector can be configured to forward a rate control signal to a media access control (MAC) based on the detection of the reserved codeword.

Abstract: A controller includes a low power processor to couple to a sensor, the low power processor configured to receive data from the sensor and apply rules to the received data and provide an interrupt in accordance with the applied rules. A high power processor is coupled to receive interrupts from the low power processor in a sleep mode, to wake upon receipt of the interrupt, and to receive and process the data to determine actions to take based on the data, wherein the high power processor initiates the actions.

Abstract: In accordance with some embodiments, a graphics process frame generation frame rate may be monitored in combination with a utilization or work load metric for the graphics process in order to allocate performance resources to the graphics process and in some cases, between the graphics process and a central processing unit.

Abstract: Disclosed is a palm gesture recognition method comprising a step of obtaining plural images according to an order of time; a step of acquiring plural palm shaped images from the plural images; a step of extracting plural features describing an open or closed palm gesture from each of the plural palm shaped images; a step of calculating a maximum feature difference vector formed by a maximum difference of each of the plural features; and a step of determining, on the basis of the maximum feature difference vector, that there is the open or closed palm gesture or there isn't the open or closed palm gesture in the plural images.

Abstract: A low-power mode for interfaces, such as secure digital input/output (SDIO) interfaces, is described. The low-power mode provides significant power savings while allowing rapid resumption of data transfer on the interface. The SDIO low-power mode gates an SDIO clock and transitions the SDIO bus to a 1-bit mode. One line of the bus carries the 1-bit data while another line carries interrupts from an SDIO peripheral. Normal data transmission results in enabling the SDIO clock and setting the bus set to the 4-bit mode.

Abstract: Methods and apparatus are disclosed to manage power consumption at a graphics engine. An example method to manage power usage of a graphics engine via an application level interface includes obtaining a policy directive for the graphics engine via the application level interface, the policy directive identifying a threshold corresponding to power consumed by the graphics engine operating in a first graphics state. The example method also includes determining a power consumed by the graphics engine during operation. The example method also includes comparing the power consumed to the threshold of the policy directive, and when the threshold is met, setting the graphics engine in a second graphics state to cause the graphics engine to comply with the policy directive.

Abstract: Various embodiments of the present disclosure are directed to managing load steps caused by processing circuitry. The processing circuitry may generate a series of clock pulses at an average clock period. The processing circuitry may estimate a current consumption of the processing circuitry at each clock pulse. Accordingly, a clock pulse from the series of clock pulses may be omitted when a change in the current consumption exceeds a predetermined threshold amount, thereby increasing the average clock period.

Abstract: A system-on-chip including a host interface module configured to interface the system-on-chip to a host processor of a wireless device and to communicate with the host processor of the wireless device via a bus. The bus uses an application programming interface of the system-on-chip. The host processor uses the application programming interface to configure a power save mode of the system-on-chip. A power management module operated the system-on-chip in the power save mode without performing a handshake with the host processor via the bus in response to the host processor stopping communication with the system-on-chip. The handshake includes (i) sending a request to enter the power save mode to the host processor via the bus and (ii) receiving an acknowledgement of the request from the host processor via the bus.

Abstract: In one embodiment, a processor includes a core with a front end unit, at least one execution unit, and a back end unit. Multiple voltage drop detectors can be located within the core each to output a voltage drop signal when a detected voltage falls below a threshold voltage. In turn, a current transient logic coupled to receive the voltage drop signals can control a micro-architectural parameter of at least one of the front end unit, execution unit and back end unit responsive to receipt of a voltage drop signal. Other embodiments are described and claimed.

Abstract: In an embodiment, a mobile device includes a sensor processor system, an application processor system and a power management controller that controls power being applied to the application processor system. The sensor processor system monitors sensors connected to the mobile device. The sensor processor system detects a pre-defined gestures and an environmental condition or event based on the monitoring. The pre-defined gesture corresponds to one or more actions initiated by a user of the mobile device (e.g., the user jogs with the mobile device, places the mobile device in his/her pocket or backpack, etc.). The sensor processor system selects a power profile to be applied to the application processor system based on the detection, and instructs the power management controller to apply the selected power profile to the application processor system.

Abstract: In one embodiment, the present invention includes a method for receiving utilization data from thread units of one or more processor cores, determining an operating frequency for a core clock signal based on the utilization data, a target utilization value, and an operating mode of the processor, and generating the core clock signal based on the determined operating frequency. Other embodiments are described and claimed.

Abstract: An exemplary low power consumption circuit includes a microprocessor, a power supply switch module and a main circuit module. The microprocessor is capable of outputting a power control signal and changing a pulse characteristic of the power control signal when the microprocessor switches from a first working mode to a second working mode. The power supply switch module is capable of outputting a power supply signal. The power supply switch module is electrically coupled to the microprocessor to receive the power control signal and thereby modulates a duty cycle of the power supply signal according to a change of the pulse characteristic of the power control signal. The main circuit module is electrically coupled to the power supply switch module to receive the power supply signal and operative with energy provided by the power supply signal. Moreover, a method for reducing power consumption is also provided.

Abstract: A management node at first extracts free computation nodes executing none of jobs in order to assign a new job to any one of computation nodes, and specifies a communication target computation node when executing an execution target job. Subsequently, the management node calculates, with respect to all of the computation nodes executing none of the jobs at that point of time, a determination value Vi on the basis of a power saving mode transition rate Si and an average value Di of distance counts from the communication target node, and specifies the free computation node having the maximum determination value Vi as the execution target job assignment destination.

Abstract: A request for a high voltage mode is received and a high voltage timer is started in response to determining that a remaining amount of high voltage credits exceeds a voltage switch threshold value. A switch to the high voltage mode is made in response to the request. A low voltage mode is switched to in response to an indication. The request may be received from an application running on a data processing system. If the indication is that the high voltage timer has expired, a low voltage timer is started in response to switching to low voltage mode. If the high voltage request is still active when the low voltage timer expires, a switch back to high voltage mode occurs and a new high voltage timer is started.

Abstract: A method, apparatus or stored program for adjusting the clock throttle rate of a central processing unit (CPU) included in a computer, in which the usage of the CPU is measured, so that the clock throttle rate of the CPU can be automatically adjusted on the measured usage of the CPU, thereby reducing the consumption of electric power without any influence on the performance of the computer.

Abstract: A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated.

Abstract: A touch sensing device is provided. The touch sensing device includes a multiplexer and a control unit, and is electrically connected to a touch panel. The touch panel includes a plurality of first-direction electrodes; a plurality of second-direction electrodes; and a dielectric layer, for generating at least one electric field change corresponding to at least one touch point in response to the at least one touch point. The at least one electric field change is generated at an overlapping region of the first-direction and second-direction electrodes. The multiplexer is electrically connected to the touch panel via the first-direction and second-direction electrodes, and selectively performs voltage driving or voltage sensing for the first-direction and second-direction changes a control signal to be transmitted to the multiplexer and receives a sense signal from the multiplexer.

Abstract: Methods, apparatuses, and computer program products for real-time temperature sensitive machine level code compilation and execution are provided. Embodiments include compiling and executing, by a just-in-time (JIT) compiler, machine level code; during execution of the machine level code, determining, by the JIT compiler, an execution temperature for the machine level code, including reading temperature measurements from one or more processor temperature sensors; based on the determined execution temperature, identifying, by the JIT compiler, a portion of the machine level code that, when executed, caused temperature measurements of one or more processor temperature sensors to exceed a predetermined threshold temperature; recompiling, by the JIT compiler, the machine level code including modifying the identified portion to generate a new execution temperature that is lower than the previously determined execution temperature; and executing, by the JIT compiler, the recompiled machine level code.

Abstract: In an embodiment, a processor includes a core to execute instructions, where the core includes a clock generation circuit to receive and distribute a first clock signal at a first operating frequency provided from a phase lock loop of the processor to a plurality of units of the core. The clock generation circuit may include a dynamic clock logic to receive a dynamic clock frequency command and to cause the clock generation circuit to distribute the first clock signal to at least one of the units at a second operating frequency. Other embodiments are described and claimed.

Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).

Abstract: A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: Method and apparatus are provided for thermal management of mobile devices. In one novel aspect, a micro-throttle method is used to control the fast rising temperature for the device. In one embodiment, the thermal management method determines a temperature of the mobile device and compares the temperature with a plurality of predefined temperature thresholds. The thermal management applies a first micro-throttle solution upon detecting the temperature reaches a first predefined temperature threshold and applies a second micro-throttle solution upon detecting the temperature reaches a second predefined temperature threshold. In one embodiment, the first and the second micro-throttle solution control the slope of the rising temperature to be below a first predefined slope and a second predefined slope, respectively. In one embodiment, the temperature is controlled by adjusting the operating frequency or voltage of at least one heat-generating components of the mobile device.

Abstract: An information processing apparatus has a sub system that, while a main system is in power saving state, analyzes a protocol of a network communication and recovers the main system to an ordinary power mode from the power saving state, in accordance with the protocol. There is a setting unit that sets a re-transition condition which is a condition to make the main system switch to the power saving state again, depending on a kind of the network communication. Further, there is a control unit that monitors whether the re-transition condition is satisfied and switches the main system to the power saving state in response to the re-transition condition being satisfied.

Abstract: A host chipset heartbeat may be utilized, in some embodiments, to handle interrupts from external devices on a power efficient basis. The availability of the host chipset heartbeat may be signaled to external devices and those external devices may time their activities to a period of time when not only are resources available, but the assertion of the activity is advantageous because the host chipset is already transitioning from a lower power consumption state.

Abstract: Optimizing an I2C bus frequency, the bus including signal lines coupling a master and slave nodes, a signal line coupled to a rise time detection circuit monitoring a voltage of the signal line, the voltage alternating between a logic low and logic high, where optimizing the frequency includes: detecting, during a rise in the signal line, a first voltage, the first voltage being greater than the logic low voltage; starting a counter to increment once for each clock period of the circuit; detecting a second voltage on the signal line, the second voltage greater than the first and less than the logic high; stopping the counter; calculating, in dependence upon the clock period and the counter value, a rise time; determining whether the rise time is greater than a maximum threshold; and increasing the I2C bus frequency if the calculated rise time is greater than the maximum threshold.

Abstract: A method and system provides dynamic power control based on thermal sensitivity of a processor system. The method and system includes a circuit that reduces the clock frequency for the processor system in response, to thermal characteristics satisfying a pre-determined threshold that allows maximal thermal temperature limit utilization without substantially degrading processor performance.

Abstract: A method and system for determining an energy-efficient operating point of the platform or system. The platform has logic to dynamically manage setting(s) of the processing cores and/or platform components in the platform to achieve maximum system energy efficiency. By using the characteristics of the workload and/or platform to determine the optimum settings of the platform, the logic of the platform facilitates performance guarantees of the platform while minimizing the energy consumption of the processor core and/or platform. The logic of the platform identifies opportunities to run the processing cores at higher performance levels which decreases the execution time of the workload and transitions the platform to a low-power system idle state after the completion of the execution of the workload. Since the execution time of the workload is reduced, the platform spends more time in the low-power system idle state and therefore the overall system energy consumption is reduced.

Abstract: A method is provided for optimizing power consumption of a digital circuit which provides operational functionality based upon operating demands. The digital circuit is subject to a supply voltage level and a clock frequency. The method includes determining an acceptable delay value, from a plurality of predetermined acceptable delay values, for the digital circuit based upon current operating demands and the clock frequency. The supply voltage level and the clock frequency are applied to a delay monitor circuit. The delay experienced by the delay monitoring circuit is measured. The measured delay is compared with the determined acceptable delay value. Based on the outcome of the comparing step, the supply voltage level applied to the digital circuit is selectively adjusted. An arrangement for implementing the method is also provided.

Abstract: To reduce power consumption, a data transmission apparatus comprises: a memory; a timing instruction unit which indicates a start timing of outputting data from the memory; a first interface which outputs data stored in the memory according to the timing instruction unit; a second interface which transfers the data from the first interface to a buffer; and a control unit which issues a command to perform transition of the first interface and the second interface to a power saving state based on the data output start timing indicated by the timing instruction unit, and a sum of a time required to perform transition of the first interface and the second interface to the power saving state and a time required to return from the power saving state.

Abstract: One embodiment provides an information processing apparatus including a processor; memory blocks; an internal voltage generator connected to the memory blocks; an input/output circuit connected to the memory blocks; switches each installed corresponding to the internal voltage generator, the input/output circuit, and the memory blocks, and configured to switch ON/OFF of the connection with a power source; a data register configured to store a data set that controls the ON/OFF of the switches; and a data management circuit configured to set the data set in the data register, wherein when a clock signal input to the processor is turned to OFF, the data management circuit generates a first type of the data set, which switches ON the switch connected to the internal voltage generator and switches OFF the switches connected to the memory blocks, and sets the first type of the data set in the data register.

Abstract: Systems and methods may provide for identifying a workload cycle for a computing platform, wherein the workload cycle is to include a busy duration and an idle duration. Additionally, platform energy consumption information may be determined for the workload cycle, and a frequency setting may be selected for the busy duration based at least in part on the platform energy consumption information.

Abstract: A central processing unit sets which of the following modes a data processing device is to operate in accordance with a user program. The high-speed operation mode allows operation within a first range in which an external supply voltage is relatively high. The wide voltage range operation mode allows operation within a second range in which the external supply voltage includes the first range and a relatively low voltage range, and an upper limit of a frequency of the first clock in the wide voltage range operation mode is lower than an upper limit of a frequency of the first clock in the high-speed operation mode. The frequency of the first clock in the low power consumption operation mode is lower than the frequency of the first clock in the high-speed operation mode and the frequency of the first clock in the wide voltage range operation mode.

Abstract: An information processing apparatus 1 includes a memory 13 that stores information used for arithmetic processing. The information processing apparatus 1 includes a CPU 11 that operates arithmetic processing by using the information stored in the memory 13. The information processing apparatus 1 includes a measuring unit 15 that measures power consumption of the memory 13. The information processing apparatus 1 includes a CPU frequency controlling unit setting unit 31 that sets an operating frequency of the CPU 11 according to the power consumption measured by the measuring unit 15.

Abstract: A method of operating an electronic system including a heterogeneous multi-core processor is provided. The method includes measuring the temperature and/or workload of a big (high-performance) core and switching a current core load from the big core to a small (low-power) core in response to the measured temperature and workload of the big core.

Abstract: An information processing apparatus includes a processor that is capable of switching a performance level to one of a plurality of performance levels with different power consumption, and a storage unit that stores a program for controlling the performance level of the processor. The processor executing the program detects the periodicity of load variation of the information processing apparatus, and changes, according to the periodicity of the load variation, a determination interval for determining whether to switch the performance level of the processor.

Abstract: An information processing method using a first information processing apparatus, the first information processing apparatus including a power supply circuit, a first processor configured to receive power supply from the power supply circuit, and a second processor configured to receive power supply from the power supply circuit, the information processing method includes decreasing an operating frequency of the first processor, based on a decrease in an amount of power supply from the power supply circuit; and stopping data processing of the first processor in a state in which the second processor is being operated, after decreasing the operating frequency of the first processor.

Abstract: One embodiment of the present invention relates to a low-power micro-controller unit having both a standby micro-controller optimized for low power consumption and a main micro-controller optimized for high performance. A power supply is coupled to the main micro-controller and the standby micro-controller. The power supply provides power to one or more of the low-power, standby micro-controller and the high performance, main micro-controller by separate power supply paths, depending on system needs. The separate power supply paths allow the main micro-controller and the standby micro-controller operate independent of each other. During a low-power standby operating mode, power can be disconnected to the main micro-controller, while providing power to the standby micro-controller, thereby eliminating the leakage current associated with the large number of transistors in the main micro-controller, while still retaining the computational capabilities of the standby micro-controller.

Abstract: A power-saving method for a first-in-first-out (FIFO) buffer implemented in a memory. The memory is segmented into a plurality of logical segments. For each logical segment, for each power saving mode, a recovery time and recovery overhead to an operational mode, and a transition overhead for transitioning the logical segment into the power saving mode, are determined. During each clock cycle, a determination is made as to whether a net power saving will result by entering each logical segment into a power saving mode based on a minimum time before a read or write pointer will enter the logical segment as well as the recovery time, the recovery overhead, and the transition overhead. The logical segment is transitioned to the power saving mode only if a net power saving will result, and is returned to the operational mode when the minimum time is no longer greater than the recovery time.

Abstract: For example, a circuit arrangement is provided comprising a clock generator configured to generate a clock signal, a circuit having a low power mode, and a controller, configured to receive, when the circuit is in the low power mode, a request specifying that the circuit should return from the low power mode and trigger the circuit to return from the low power mode when the number of clock cycles of the clock signal since the reception of the request has reached a threshold value.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.