Abstract: A battery powered mobile device has battery monitoring circuit that measures one or more parameters indicative of a current state of the battery. A plurality of operational systems and processes form a part of the mobile device. A programmed processor is programmed to carry out a process that includes: determining a current state of the battery by receiving data representing the one or more parameters from the battery monitoring circuit indicative of the current state of the battery; calculating a battery power factor as a function of the parameter; comparing the battery power factor to a threshold; when the battery power factor exceeds the threshold, identifying a system or process within the mobile device whose power consumption can be reduced; and reducing the power consumption by altering or disabling the identified system or process.

Abstract: A power management system for stack memory thread tasks according to some examples of the disclosure may include a non-collapsible memory region, a collapsible memory region configured below the non-collapsible memory region, a memory management unit in communication with the non-collapsible memory region and the collapsible memory region, the memory management unit operable to allocate a portion of the non-collapsible memory region and a portion of the collapsible memory region to a thread task upon initialization of the thread task and power down the portion of the collapsible memory region allocated to the thread task upon receiving a power down command.

Abstract: In certain aspects, a method for frequency scaling comprises determining whether only a subset of multiple processors is active, wherein the multiple processors share one or more resources. The method also comprises increasing a frequency of at least one processor in the subset of the multiple processors if a determination is made that only the subset of the multiple processors is active and the frequency of the at least one processor is below a frequency threshold. This may be done, for example, to increase the time duration of an idle mode for the one or more shared resources and achieve an overall power reduction for a system including the multiple processors, the one or more shared resources, and/or other function blocks.

Abstract: Examples of techniques for a built-in self-test (BIST) for embedded spin-transfer torque magnetic random access memory (STT-MRAM) are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include: initiating, by a processor, a BIST for the STT-MRAM; performing, by the processor, an error-correcting code (ECC) test for a portion of the STT-MRAM; responsive to the ECC test not being passed, determining whether a maximum signal is reached; responsive to the maximum signal not being reached, increasing the signal and performing the ECC test again; and responsive to the maximum signal being reached, determining that the portion of the STT-MRAM is bad.

Abstract: An information processing device includes: a memory; and a processor coupled to the memory. The processor is configured to: set a first limit value of power consumption that the processor is permitted to consume during execution of a program to be analyzed, control execution of the program, control the processor to enable a generation of at least one interrupt during the execution of the program, acquire executed function information indicating a currently executed function included in the program and a first operational frequency of the processor during the execution of the function included in the program, and output the executed function information and limit information indicating whether the first operational frequency of the processor was limited by the first limit value to the memory.

Abstract: A component carrier with a housing and a converter board disposed within the housing. The converter board including a U.2 connector, an M.2 connector configured to receive an M.2 solid state drive having a cache memory, and a capacitor. The capacitor provides backup power for a power loss protection system allowing flush cache storage. The housing configured to receive one or more M.2 solid state drives coupled with the converter board.

Abstract: A wet cell battery, where a first cell in a wet-cell battery includes a set of anode electrodes and a set of cathode electrodes, and where electrically conductive debris accumulates on a surface inside the first cell to an expected height. An anode electrode in the set of anode electrodes has an anode end closest to the surface, and a cathode electrode in the set of cathode electrodes has a cathode end closest to the surface. A first gap distance between the anode end and the surface is different from a second gap distance between the cathode end and the surface. When the electrically conductive debris accumulates up to the expected height, the debris fails to make simultaneous electrical contact with the anode electrode and the cathode electrode due to the different gap distances.

Abstract: The present disclosure describes apparatuses and techniques for managing aggregate IC current demand. In some aspects, respective indications of first and second amounts of current consumed by IC components are received from the IC. The first and second amounts of current are combined to determine an aggregate current demand for the components of the IC. This aggregate current demand is then compared to a threshold for an amount of current that can be provided to the components of IC. Responsive to the aggregate current demand exceeding the threshold, an operational characteristic of one of the components is modified to reduce the aggregate current demand of the components of the IC. This can be effective to prevent the IC from drawing more current than can by supplied to the IC.

Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.

Abstract: Hardware acceleration for a kernel can include selecting, using a processor, a kernel, determining, using the processor, a clock frequency for the selected kernel, and programming, using the processor, a clock circuit to generate a clock signal having a clock frequency compatible with the clock frequency of the selected kernel. Using the processor, the selected kernel can be implemented as a kernel circuit within a region of programmable circuitry. The kernel circuit can be clocked using the clock signal from the clock circuit having the compatible clock frequency.

Abstract: The present invention includes means of using a customized coprocessor to replace a main processor to process or interact with a data processing unit in a complex scene and reducing clock frequencies of the main processor and related modules, thereby achieving low power consumption of the three-dimensional measurement chip. The present invention includes: step 1: determining a system structure of a three-dimensional measurement processing chip; step 2: classifying data processing units according to scene requirements; step 3: adding coprocessors on a system bus; step 4: designing a customized coprocessor or small data control unit; step 5: designing a semi-customized coprocessor or small data control unit; step 6: optimizing software codes and reducing a clock frequency; step 7: verifying the chip to confirm that the chip satisfies design requirements. The present invention is applicable to a plurality of integrated circuits or any internetwork system consisting of a plurality of integrated circuits.

Abstract: A clock management unit (CMU) includes a first clock control circuit controlling a first clock source, a second clock control circuit sending a first clock request to the first clock control circuit in response to an intellectual property (IP) block clock request from an IP block and controlling a second clock source, and a CMU controller. The second clock source receives a clock signal from the first clock source. A power management unit (PMU) sends a PMU clock request to the CMU controller. The CMU provides the clock signal to the IP block in response to the PMU clock request.

Abstract: Aspects of the disclosure provide a circuit that includes processing circuits and a power mode control circuit. The processing circuits are configured to have at least a first power saving mode and a second power saving mode having different power saving efficiency under different scenarios. The processing circuits are configured to determine a power saving mode for the processing circuits based on a threshold that is a function of one or more operational parameters. Then, the power mode control circuit is configured to receive information from the processing circuits that is indicative of the power saving mode, and control the processing circuits to enter the determined power saving mode.

Abstract: Various exemplary embodiments relate to an event-driven processing unit (EPU) and a related method. A microprocessor may halt processing instructions when it executes a halting command. Thereafter, an EPU clock may stop its processing cycle and therefore halt microprocessor execution until it receives a start signal by a pattern detector. The pattern detector may use a plurality of bit slices to monitor a plurality of external inputs for the occurrence of events specified by the user. Some embodiments may also allow the user to check functioning by skipping upcoming instructions if a monitored event did not occur. By halting the EPU clock and the execution flow of the microprocessor, the event-driven microprocessor minimizes waste associated with executing a main control loop while waiting for a monitored event to occur. This may save processing capacity, memory, and power associated with continually running the main control loop.

Abstract: The visualization of progress of a distributed computational job at multiple points of execution. After a computational job is compiled into multiple vertices, and then those multiple vertices are scheduled on multiple processing nodes in a distributed environment, a processing gathering module gathers processing information regarding processing of multiple vertices of a computational job, and at multiple instances in time in the execution of the computational job. A user interface module graphically presents a representation of an execution structure representing multiple nodes of the computational job, and dependencies between the multiple nodes, where the nodes may be a single vertex or a group of vertices (such as a stage).

Abstract: In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.

Abstract: Provided are a method and a device for determining a clock frequency of a router card. The method includes steps A to D. In step A, a target average port traffic is obtained by using the number of ports and a total to-be-served traffic higher than zero of a target network node for each of neighboring network nodes. In step B, a clock frequency meeting the demand of the target average port traffic is determined as a clock frequency of any router card, the clock frequency of which has not been set, in the target network node. In step C, the total to-be-served traffic and the number of ports are updated. In step D, step A is performed, in a case that there is the updated total to-be-served traffic higher than zero.

Abstract: A controller is provided with a plurality of CPUs and temperature sensors disposed in the vicinity of the CPUs, individually. The CPUs reciprocally read temperature data detected by the temperature sensors. When the read temperature data exceed a predetermined threshold, it is determined that the CPUs are likely to undergo thermal runaway, and the CPUs are then stopped.

Abstract: According to one embodiment, a controller determines a write operation, when a write request to a memory, a write address and data are received, by comparing an amount of use of a write buffer and a threshold for determining a change of a write operation to the memory. The memory is capable of overwriting first data to second data at an identical physical address of the memory. By the determined write operation, the received data is written to the received write address of the memory.

Abstract: A method for managing energy usage by a mobile device is described. An environmental characteristic is monitored over environments in which the mobile device is operable. A location of the mobile device is tracked in relation to the environments. The mobile device is informed with data relating to the environmental characteristic of the environment in which the mobile device location is tracked. A characteristic of the mobile device is sensed. The data, related to the environmental characteristic of the tracked location, is compared to the sensed mobile device characteristic. An action is determined related to the energy-using operation of the mobile device based on the comparison. The energy-using operation of the mobile device is controlled, based on the determined action.

Abstract: Methods, systems, and computer readable media for obtaining power consumption data associated with packet processing are disclosed. One method for obtaining power consumption data associated with packet processing occurs at a test device. The method includes sending, via a first communications interface, at least one test packet to a system under test (SUT). The method also includes receiving, via a second communications interface, power consumption data associated with the at least one test packet. The method further includes correlating the power consumption data and test packet information.

Abstract: A circuit comprising an ECM system is provided. The circuit includes a current monitor circuit configured to monitor the ECM system to measure a set of currents supplied to a set of circuits. The circuit also includes an alert circuit configured to generate an alert based on at least one current of the set of currents in comparison to at least one threshold. The circuit further includes a throttle circuit configured to throttle a performance of at least one circuit in order to decrease the current to the at least one circuit based on the generation of the alert. The current used by the circuit may act as an analogue for the system power used. Accordingly, the current used by the circuit may be used to determine when to throttle one or more aspects of the functionality of the circuit.

Abstract: Managing system clocks of virtual machines. A host system clock value of a host system clock of a host system is obtained, and a virtual machine system clock value of a system clock of a virtual machine managed by the host system is determined. The determining of the virtual machine system clock value includes using the host system clock value and a system clock adjustment value. The system clock of the virtual machine is adjusted using the virtual machine system clock value.

Abstract: Managing system clocks of virtual machines. A host system clock value of a host system clock of a host system is obtained, and a virtual machine system clock value of a system clock of a virtual machine managed by the host system is determined. The determining of the virtual machine system clock value includes using the host system clock value and a system clock adjustment value. The system clock of the virtual machine is adjusted using the virtual machine system clock value.

Abstract: A system-on-chip includes a symmetric multi-processor including a plurality of cores, each configured to operate in a high performance operating mode and a low performance operating mode. The system-on-chip further includes a clock management unit configured to provide an operating clock signal to the symmetric multi-processor, a state management unit configured to monitor operating states of the cores, a temperature management unit configured to monitor a temperature of the symmetric multi-processor, and a symmetric multi-processor control unit configured to determine the operating clock signal and the operating states of the cores based on a workload of the symmetric multi-processor. The symmetric multi-processor control unit is further configured to differentially determine a maximum operating clock frequency for the cores based on the temperature and the operating states of the cores, which indicate a quantity of cores that are currently in operation.

Abstract: A computing system includes a multi-core processor and a core controller. The core controller is for: monitoring utilization of the multi-core processor; calculating a target performance index according to the utilization of the multi-core processor, a target utilization and a first performance index, wherein the first performance index is associated with a first entry of a dynamic voltage frequency scaling (DVFS) table that corresponds to a current setting for the multi-core processor; and selecting a second entry of the DVFS table that corresponds to a target-setting according to the target performance index and a second performance index that is associated with the second entry. The target-setting is used to configure the multi-core processor.

Abstract: Energy efficiency is managed in a multi-cluster system. The system detects an event in which a current operating frequency of an active cluster enters or crosses any of one or more predetermined frequency spots of the active cluster, wherein the active cluster includes one or more first processor cores. When the event is detected, the system performs the following steps: (1) identifying a target cluster including one or more second processor cores, wherein the each first processor core in the first cluster and each second processor core in the second cluster have different energy efficiency characteristics; (2) activating at least one second processor core in the second cluster; (3) determining whether to migrate one or more interrupt requests from the first cluster to the second cluster; and (4) determining whether to deactivate at least one first processor core of the active cluster based on a performance and power requirement.

Abstract: A method for operating a set-top-box that supports 3D video content is disclosed. The method involves transmitting video content from an HDMI port of the set-top-box to a display device at a first resolution. The method also involves, in response to a change in the HDMI_Video_Format field or in the 3D_Structure field of an HDMI Vendor Specific InfoFrame, automatically switching to transmitting video content from the HDMI port of the set-top-box at a second resolution. The method also involves, after the switch to the second resolution, automatically switching back to transmitting video content from the HDMI port of the set-top-box at the first resolution in order to trigger a re-sync operation at the display device.

Abstract: An apparatus and method for performing the dynamic frequency control of a central processing unit (CPU). The apparatus for performing the dynamic frequency control of a central processing unit (CPU) includes a frequency setting unit, a latency measurement unit, a frequency adjustment unit, and a control unit. The frequency setting unit sets optimum frequency using the measured amount of load. The latency measurement unit measures scheduler execution information. The frequency adjustment unit adjusts the optimum frequency using the scheduler execution information. The control unit incorporates the adjusted optimum frequency into a CPU.

Abstract: A method includes generating temperature information from a plurality of temperature sensors within a computing device; and processing the temperature information to generate voltage reduction steps based on an observed rate of change of the temperature information.

Abstract: Example implementations and techniques are described in which a processor uses a dynamic adjustment algorithm, including algorithms based on performance and energy models, to readjust frequency settings for a graphics processing unit (GPU), and independently for a system memory or for a system memory bus, to an optimal level for meeting sustained performance requirements with the low level of power consumption.

Abstract: The invention is an apparatus for dynamic provisioning available as a multi-mode device that can be dynamically configured for balancing between storage performance and hardware acceleration resources on reconfigurable hardware such as an FPGA. An embodiment of the invention provides a cluster of these multi-mode devices that form a group of resilient Storage and Acceleration elements without requiring a dedicated standby storage spare. Yet another embodiment of the invention provides an interconnection network attached cluster configured to dynamically provision full acceleration and storage resources to meet an application's needs and end-of-life requirements of an SSD.

Abstract: A charging system comprises an electronic device and a power adapter for charging the electronic device. The electronic device has a bi-directional communication with the power adapter; and the electronic device is arranged to send a health check command to the power adapter, and the power adapter performs a self-health check operation and reports a checking result to the electronic device. In addition, the electronic device may calculate a cable impedance, and control a compensation function of the power adapter by referring to the calculated cable impedance.

Abstract: Technologies for high-speed data transmission including a network port logic having a communication lane coupled to a physical medium dependent/physical medium attachment (PMD/PMA) sublayer, a physical coding sublayer (PCS), and a media access control (MAC) sublayer. The communication lane receives serial binary data at a line speed such as 25 gigabits per second. The PMD/PMA converts the serial binary data into parallel data, and the PCS decodes that parallel data using a line code also used for a slower line speed such as 10 gigabits per second. The network port logic may include four independent communication lanes, with each communication lane coupled to a dedicated PMD/PMA, PCS, and MAC. The network port logic may also include a multi-lane PCS and multi-lane MAC to receive and transmit data striped over the four communication lanes. Other embodiments are described and claimed.

Abstract: A communication device includes a main controller and a second controller that responds, independently of the main controller, to received data based on a proxy program. The communication device also includes a storage that stores, every time data is received, a combination of attributes of the data and details of a response to the data made by the main controller. The communication device also includes a generating circuit that determines at least one pattern with which a response, independently of the main controller, is possible based on a plurality of combinations stored in the storage to generate the proxy program based on the pattern determined. The communication device also includes an applying circuit that applies the proxy program generated by the generating circuit to the second controller.

Abstract: A method for performing system power control within an electronic device and an associated apparatus are provided. The method includes the steps of: utilizing a power consumption index generator positioned in a specific subsystem to generate a power consumption index corresponding to the specific subsystem, where the electronic device includes a plurality of subsystems, and the specific subsystem is one of the plurality of subsystems; and triggering a power limiter protection operation for the electronic device according to the power consumption index. For example, the power consumption index corresponding to the specific subsystem may represent a power consumption value of the specific subsystem, and the method may further include: comparing the power consumption value of the specific subsystem with a peak power threshold to determine whether the power consumed by the specific subsystem reaches the peak power threshold to generate a determining result, for triggering the power limiter protection operation.

Abstract: An electronic device that may process a security packet is provided. The electronic device includes a first processor configured to transmit a security context and a second processor configured to process a packet to which security is applied using the security context.

Abstract: One or more techniques and/or systems are provided for suspending logically related processes associated with an application, determining whether to resume a suspended process based upon one or more wake policies, and/or managing an application state of an application, such as timer and/or system message data. That is, logically related processes associated with an application, such as child processes, may be identified and suspended based upon logical relationships between the processes (e.g., a logical container hierarchy may be traversed to identify logically related processes). A suspended process may be resumed based upon a set of wake policies. For example, a suspended process may be resumed based upon an inter-process communication call policy that may be triggered by an application attempting to communicate with the suspended process. Application data may be managed while an application is suspended so that the application may be resumed in a current and/or relevant state.

Abstract: A memory device includes a memory cell that is configured to store a data bit, comprising at least one read transistor that is configured to form either a discharging path or a leakage path when the data bit is read; a conductive line coupled to the read transistor; and at least a first track transistor, coupled to the conductive line, and configured to provide a first current signal having a first current level that tracks a second current level of a second current signal, wherein the second current signal is provided when either one of the discharging and leakage paths is formed, and wherein the first the second current signals are used to determine a logical state of the data bit.

Abstract: Various aspects of a power management approach for a system-on-a-chip (SoC) is disclosed herein. In one aspect, the approach includes implementing a power profile for supplying power to a plurality of subsystems on a shared power bus in the SoC. The power profile includes at least one adjustable parameter for controlling the supplied power during an active use state. The approach further includes detecting a power profile change trigger; modifying the power profile based on the power profile change trigger; and adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level.

Abstract: In an approach for generating a file, a computer generates a modified layout for an integrated circuit. The computer receives a draft layout for an integrated circuit. The computer identifies a resonator, wherein the resonator comprises a capacitor connected to ground and an inductor connected to a clock grid. The computer creates alternative resonator wiring of the received draft layout associated with the identified resonator. The computer generates a modified draft layout based on the created alternative resonator wiring for the integrated circuit.

Abstract: A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

Abstract: A power control system for saving power by powering on enough application servers to satisfy the current load workload as well as any required reserve capacity based on administrative settings is disclosed. As the load increases, more servers are powered on. As the load decreases some servers are powered off. The power control system provides a reasonable end user experience at the least cost based on power consumption of the servers.

Abstract: Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

Abstract: In an embodiment, a processor includes first logic to determine first power to be provided to a first portion of a computational resource during a time period. The first portion may be reserved for execution by the processor of a first workload to be executed during the time period. The first power may be determined based at least in part on the first workload and independently of a second workload. The processor may include second logic to determine second power to be provided to a second portion of the computational resource during the time period. The second portion may be reserved for execution by the processor of the second workload during the time period. The second power may be determined based at least in part on the second workload and independently of the first workload.

Abstract: An improved system and method are disclosed for providing virtual parallel access to a shared resource. In one example, the method includes receiving a request from a device to take control of the shared resource. After determining that another device is currently in control of the shared resource, a timer is started. Control of the shared resource will automatically pass from the device currently in control to the requesting device when the timer expires. Input received from the device currently in control is executed. Input received from the device that has requested control is buffered and executed once control is transferred.

Abstract: An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory, where the specified load instruction comprises a load instruction resulting from execution of an x86 special bus cycle. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand.

Abstract: In an embodiment, a processor includes a logic to cause at least one core to operate with a power control cycle including a plurality of on times and a plurality of off times according to an ON-OFF keying protocol, where the on and off times vary depending on whether and when an interrupt is incurred. Other embodiments are described and claimed.

Abstract: Transaction exchanges are controlled between two integrated circuits in a system having the integrated circuits (ICs), a power supply supplying power to a link between the ICs, thereby enabling transaction exchanges between both ICs and a controller controlling the ICs and the power supply. This involves receiving an order at the controller, wherein the order requires the link to be closed. An instruction is sent from the controller to each of the two ICs, wherein the instruction causes each of the ICs to stop initiating new transaction requests. For each one of the ICs, in response to detecting that the one of the two ICs has stopped initiating new transactions, it is detected when all pending transactions initiated by the one of the two ICs have been executed. The link is closed in response to detecting that all pending transactions of both of the two ICs have been executed.

Abstract: Provided is a control method of a system-on-chip including a multi-core processor. The control method includes detecting a rate of runnable tasks to be performed in the multi-core processor and a driving voltage or a driving clock of the multi-core processor, determining whether variation of the rate of the runnable tasks sampled from a first time point to a current time and variation of the driving voltage or the driving clock sampled from a second time point to the current time satisfy a hotplug condition, and hotplugging in or out at least one core included in the multi-core processor when the rate of the runnable tasks and the driving voltage or the driving clock each satisfy the hotplug condition.