Abstract: A semiconductor device includes a first control circuit controlling a first child clock source to receive a clock signal from a parent clock source, a first channel management (CM) circuit transmitting a first clock request to the first control circuit in response to a second clock request received from a first IP block, a second control circuit controlling a second child clock source to receive the clock signal from the parent clock source, a second CM circuit transmitting a third clock request to the second control circuit in response to a fourth clock request received from a second IP block, and a power management unit transmitting a power control command to the first CM circuit and the second CM circuit to control a power state of the first IP block and the second IP block. The first CM circuit and the second exchange signals to maintain a master-slave relationship.

Abstract: A method of operating an embedded USB2 (eUSB2) repeater includes receiving a downstream packet at a USB2 port and transitioning a USB transmitter from an idle state to a standby state responsive to receiving the downstream packet. The method further includes transitioning the USB transmitter from the standby state to an active state if an upstream packet is received at an eUSB2 port within a first time period of receiving the downstream packet and transmitting the upstream packet. The method also includes transitioning the USB transmitter from the active state to the standby state after transmission of the upstream packet. The method also includes transitioning the USB transmitter from the standby state to the idle state if more upstream packets are not received at the eUSB2 port within a second time period.

Abstract: A semiconductor apparatus may include logic circuits and a control logic. The control logic may be configured to monitor characteristics of the logic circuits to allow the semiconductor apparatus to perform at different operating speeds.

Abstract: A clock task processing method includes before or when running a service process by using at least one data core, disabling a clock interrupt of the at least one data core, and processing a clock task in the at least one data core by using at least one control core of multiple control cores that cannot process service data.

Abstract: Example implementations relate to an access point (AP) that can via up from power save mode via a including Bluetooth low energy (BLE) system-on-chip (SoC) within the AP. The AP can include a power source, a power reset logic component in communication with the power source, a BLE SoC, a processor, and a non-transitory memory resource instructions executable by the processor that signals the AP is in a power save mode, receives an indication, via the BLE SoC, to wake up the AP, and wake up, via the BLE SoC, the AP in response to receiving the indication.

Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.

Abstract: Embodiments are generally directed to providing power savings for a neural network architecture with zero activations during inference. An embodiment of an apparatus includes one or more processors including one or more processor cores; and a memory to store data for processing including neural network processing, wherein the apparatus to perform a fast clear operation to initialize activation buffers for a neural network by updating metadata to indicate zero values, the neural network including a plurality of layers, wherein the apparatus is to compare outputs for the neural network to the metadata values and to write an output to memory only if the output is non-zero.

Abstract: Examples herein relate to an adjustment of a power limit of a processor. Examples disclose setting the power limit of the processor. The examples also obtaining a temperature difference between a die temperature of a core within the processor and a throttle temperature. In response to a determination that the temperature difference is at most equal to a temperature activation point, adjusting the power limit of the processor so that the adjust power limit is less than the set power limit.

Abstract: In an embodiment, the present invention includes an execution unit to execute instructions of a first type, a local power gate circuit coupled to the execution unit to power gate the execution unit while a second execution unit is to execute instructions of a second type, and a controller coupled to the local power gate circuit to cause it to power gate the execution unit when an instruction stream does not include the first type of instructions. Other embodiments are described and claimed.

Abstract: A method and apparatus for mission critical standby of a portable communication device are disclosed. A portable communication device may include a primary processor for a first operating platform, a secondary processor for a second operating platform and communicatively coupled to the primary processor, and a power state manager that may have a first mode and a second mode. The power state manager may be configured to determine whether the primary processor is in a powered off state and sequence supply of power to the secondary processor. The first mode may allow the primary processor to monitor a power state of the secondary processor based on a determination that the primary processor is not in the powered off state and the second mode may enable the power state manager to monitor the power state based on a determination that the primary processor is in the powered off state.

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to transition devices between operational modes. An example apparatus comprising: an activity detector configured to be coupled to a communication bus; a communication bus controller coupled to the activity detector; a hardware wakeup controller coupled to the activity detector; a switching circuit coupled to the hardware wakeup controller; a first oscillator coupled to the switching circuit; and a second oscillator the second oscillator coupled to the switching circuit and the hardware wakeup controller.

Abstract: A method and system for programming a microcontroller (MCU) to implement a data transfer, the MCU having a flash memory, a central processing unit (CPU) and a direct memory access controller (DMAC). In one embodiment, the method includes calling a function stored in the flash memory, wherein a first parameter is passed to the function when it is called, wherein the first parameter identifies a first data structure that is stored in flash memory, and wherein the first data structure includes first DMAC control values. The CPU reads the first DMAC control values in response to the CPU executing instructions of the function. The CPU then writes the first DMAC control values to respective control registers of the DMAC in response to the CPU executing instructions of the function.

Abstract: Methods and apparatuses to manage working states of a data processing system. At least one embodiment of the present invention includes a data processing system with one or more sensors (e.g., physical sensors such as tachometer and thermistors, and logical sensors such as CPU load) for fine grain control of one or more components (e.g., processor, fan, hard drive, optical drive) of the system for working conditions that balance various goals (e.g., user preferences, performance, power consumption, thermal constraints, acoustic noise). In one example, the clock frequency and core voltage for a processor are actively managed to balance performance and power consumption (heat generation) without a significant latency. In one example, the speed of a cooling fan is actively managed to balance cooling effort and noise (and/or power consumption).

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.

Abstract: In one embodiment, a clock-gating system for a pipeline includes a clock-gating device configured to gate or pass a clock signal to the pipeline, and a clock controller. The clock controller is configured to track a number of input packets at an input of the pipeline, to track a number of output packets at an output of the pipeline, to determine whether to gate or pass the clock signal based on the number of the input packets and the number of the output packets, to instruct the clock-gating device to pass the clock signal if a determination is made to pass the clock signal, and to instruct the clock-gating device to gate the clock signal if a determination is made to gate the clock signal.

Abstract: The present disclosure relates to a device including a built-in-self-test (BIST) circuit configured to run a BIST pattern in a loop mode on a memory which is customized for activity factors corresponding to a programmable number of operations, the BIST circuit being further configured to measure dynamic power on a supply while running the BIST pattern in the loop mode on the memory.

Abstract: Noise generation caused by sudden rising of a rotational speed of a heat radiation fan when a user has no intension is prevented. A temperature management system located on an information processing apparatus is configured by a system including a processor and scheduled tasks, a performance control system which controls processing ability of the processor and a temperature control system which includes a heat radiation fan and controls a heat radiation amount thereof. The processor executes the scheduled tasks when a state where a usage rate is low, such as an idle state, lasts. The temperature control system controls the rotational speed of the heat radiation fan in accordance with temperatures of electronic devices including the processor. The performance control system lowers processing ability of the processor before the rotational speed of the heat radiation fan rises in accordance with a temperature of the processor which executes the scheduled tasks.

Abstract: A method of operating an application processor including a central processing unit (CPU) with at least one core and a memory interface includes measuring, during a first period, a core active cycle of a period in which the at least one core performs an operation to execute instructions and a core idle cycle of a period in which the at least one core is in an idle state, generating information about a memory access stall cycle of a period in which the at least one core accesses the memory interface in the core active cycle, correcting the core active cycle using the information about the memory access stall cycle to calculate a load on the at least one core using the corrected core active cycle, and performing a DVFS operation on the at least one core using the calculated load on the at least one core.

Abstract: In some examples, a peak power system includes a plurality of system components, one or more of the system components to dynamically provide a peak power requirement of the component. The system also includes a peak power manager to receive the peak power requirement of the one or more of the system components. The peak power manager can also dynamically provide, based on a system peak power limit and based on at least one updated peak power requirement received from at least one of the one or more system components, an updated component peak power limit to one or more of the system components.

Abstract: Systems and a method for controlling power of a device with power management software are described. In one embodiment, a computer implemented method initiates power control having ON-OFF keying to control power consumption of a device for energy efficiency and energy conservation. An ON-OFF period of the ON-OFF keying for the device is computed. The method sets a target frequency, a target supply voltage, and a power gate control for the device based on the ON-OFF keying.

Abstract: A method of operating a system-on-chip (SOC) including a central processing unit (CPU) and a target hardware to which a dynamic voltage and frequency scaling (DVFS) is applied, includes determining an operating scheme of the target hardware, setting a DVFS application scheme for applying the DVFS to the target hardware, based on the operating scheme of the target hardware, and performing the DVFS on the target hardware, based on the DVFS application scheme.

Abstract: A method for recovering a digital file from a locked device is provided. An identity token is received at a recovery app on the locked device. The recovery app retrieves a digital file from the locked device and sends the digital file and the identity token to a service external to the device.

Abstract: The present control apparatus includes a timer for measuring a predetermined time and a clock generation circuit for supplying a clock to a peripheral device. Furthermore, the control apparatus includes a CPU for alternatingly stopping and restarting driving of the clock generation circuit based on the measuring of the predetermined time performed by the timer. On the other hand, the peripheral device includes an interrupt mask that restricts output of an interrupt signal to the control apparatus via the peripheral bus. When the driving of the clock generation circuit is to be stopped, the control apparatus sets the interrupt mask, and when the driving of the clock generation circuit is to be restarted, the control apparatus cancels the interrupt mask.

Abstract: A Universal Serial Bus 2.0 (USB2 or eUSB2) device includes an integrated circuit (IC) having a physical layer to send and receive data on a pair of signal lines, a repeater communicatively coupled to the physical layer via the pair of signal lines, and having a port to send and receive data on a second pair of signal lines and a power management unit to provide power to the physical layer and the repeater during an active state and to gate power to the physical layer and the repeater during a low power state.

Abstract: A method for reducing power consumption in an electronic control unit (ECU) equipped with an Ethernet communication function and mounted in a vehicle include initializing a physical layer upon restarting of the physical layer and setting a transmission mode to a data mode. The method includes generating a clock signal having a first frequency for Ethernet communication, checking presence or absence of a normal frame to be transmitted, checking presence or absence of an idle frame based on a reception signal symbol, and determining whether to change the frequency of the clock signal based on checking results in the checking of presence or absence of a normal frame and the checking of presence or absence of an idle frame.

Abstract: An integrated circuit device is provided. The integrated circuit device may include a central processing unit (CPU) configured to operate in one of a plurality of modes and a wake-up control circuit configured to control the CPU. The wake-up control circuit may include a clock generator configured to generate an internal clock signal, a multiplexer configured to select a signal from among an external signal and the internal clock signal and to provide the CPU with the selected signal as an operating clock signal, and a controller configured to control the CPU and the clock generator based on the external signal.

Abstract: The disclosed embodiments provide a system that intelligently migrates workload between servers in a data center to improve efficiency in associated power supplies. During operation, the system receives time-series signals associated with the servers during operation of the data center, wherein the servers include low-priority servers and high-priority servers. Next, the system analyzes the time-series signals to predict a load utilization for the servers. The system then migrates workload between the servers in the data center based on the predicted load utilization so that: the high-priority servers have sufficient workload to ensure that associated power supplies for the high-priority servers operate in a peak-efficiency range; and the low-priority servers operate with less workload or no workload.

Abstract: A method for power management of a mobile device includes detecting whether a removable power source has been removed from the mobile device. In response to detecting that the power source has been removed, entering a hot swap mode for a first time period by deactivating a first component of the mobile device and maintaining, via a backup power source in the mobile device, a powered state of a second component of the mobile device and an application state of the mobile device. The method further includes, after the first time period, entering a suspend mode for a second time period by deactivating the second component and continuing to maintain the application state of the mobile device for the second time period.

Abstract: Processor frequencies can be managed. For example, a computing device can determine (i) a first estimate of an operating characteristic of a processor in using a first pair of frequencies to perform a task, and (ii) a second estimate of the operating characteristic of the processor in using a second pair of frequencies to perform the task. The computing device can select the first pair of frequencies based on determining that the first estimate is closer to a target operating-characteristic of the processor while performing the task than the second estimate. Based on selecting the first pair of frequencies, the computing device can set a clock rate of the processor to a lower frequency in the first pair of frequencies while performing the task. The computing device can also set the clock rate of the processor to a higher frequency in the first pair of frequencies while performing the task.

Abstract: A method for controlling an operation unit, a system for controlling an operation unit, and a computer storage medium are provided. The method includes: determining a relative current value; determining target frequencies corresponding to all currently running operation units, determining the temperatures of all of the currently running operation units, and calculating the sum of current values of all of the currently running operation units based on the target frequencies and the temperatures, wherein the target frequency corresponding to each running operation unit is a series of frequencies with which the operation unit can run; and comparing the calculated sum of the current values with the determined relative current value, and if the sum of the current values is smaller than the relative current value, determining the target frequency corresponding to the sum of the current values as a running frequency to be selected.

Abstract: Methods and apparatus relating to rotational graphics sub-slice and Execution Unit (EU) power down to improve power performance efficiency are described. In one embodiment, power-gating is rotated amongst single sub-slices within each slice of a plurality of slices based on an indication to reduce power consumption of a computational logic. The computational logic includes the plurality of slices and each of the plurality of slices includes a plurality of sub-slices to perform one or more computations. Other embodiments are also disclosed and claimed.

Abstract: Embodiments are directed to capturing and storing historical data regarding thermal remediations, to predicting and acting on remediation futures and to communicating with applications regarding thermal remediations implemented on the computer system. In one scenario, a computer system determines which thermal remediations are currently being implemented on a monitored computing device. The thermal remediations are based on the monitored computing device's current operating environment including the physical thermal environment and/or the current software execution environment. The computer system further tracks thermal remediation levels for those thermal remediations that are currently being implemented on the monitored computing device, the thermal remediation levels indicating the degree to which each thermal remediation is implemented.

Abstract: A printing apparatus which prevents communication from becoming impossible. The printing apparatus has a control unit and a printer unit. At start-up of the control unit, a first communication speed is set as a communication speed for communication between the control unit and the printer unit, and also a predetermined command is transmitted to the printer unit. Whether or not a response to the predetermined command has been received from the printer unit is determined. As a result of the determination, when no response to the predetermined command has been received from the printer unit, a second communication speed different from the first communication speed is set as the communication speed for the communication between the control unit and the printer unit, and also, a reset command is transmitted to the printer unit.

Abstract: In an embodiment, a processor may include a first clock circuit to generate a first clock signal, a plurality of functional blocks, and clock logic. Each functional block may include a sub-clock circuit to generate a second clock signal based on the first clock signal, and a counter to store a count of active consumer of the second clock signal. The clock logic may, in response to a determination that the counter of a first functional block has a value less than one, disable the sub-clock circuit of the first functional block. Other embodiments are described and claimed.

Abstract: A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training.

Abstract: A low power autonomous peripheral operative to receive configuration or command data and to perform the designated operation(s) without interaction of a processor.

Abstract: Provided are a semiconductor device and a semiconductor system. A semiconductor device includes a hardware auto clock gating (HWACG) logic configured to provide clock gating of an intellectual property (IP) block; and a memory power controller configured to perform power gating of a memory electrically connected with the IP block, based on the HWACG logic providing the clock gating for the IP block. The HWACG logic includes a first clock source configured to provide a first clock signal; a second clock source configured to receive the first clock signal provided by the first clock source, and provide a second clock signal to the IP block; a first clock control circuit configured to control the first clock source; and a second clock control circuit configured to transmit a clock request to the first clock control circuit, and control the second clock source, based on an operation state of the IP block.

Abstract: The present disclosure relates to a bus interface system including a bus line, master integrated circuitry (IC), and slave IC. The master IC is coupled to the bus line and configured to transmit the data signal to the slave IC through the bus line. The slave IC is coupled to the bus line so as to receive the data signal from the master IC and includes a supply capacitor, which is configured to store power from the data signal and provide a supply voltage to the slave IC. When the bus line is in the low state, the supply capacitor is isolated from the bus line. When the bus line is in the high state, the supply capacitor is allowed to extract power from the data signal on the bus line.

Abstract: Aspects of the present invention include a device including processing circuitry that detects a first user action according to a first signal received from a first sensor while operating in a first mode, the first user action being gripping and lifting up of the device, changes an operation mode from the first mode to a second mode based on the first user action, detects a second user action according to a second signal received from a second sensor while operating the second mode, the second user action being a touch operation, performs an operation based on the second user action, and changes the operation mode from the second mode to a third mode after a predetermined period of time elapses, the second mode consuming more power than the first mode, and the third mode consuming more power than the first mode.

Abstract: A method for providing a power estimation for an electronic system is disclosed. Initially, a system architecture of an electronic system design is initially developed, and the system architecture of the electronic system design is then converted to a power flow architecture of the electronic system design. For each power domain within the power flow architecture of the electronic system design, a power domain type is designated. Subsequently, power information are added to the power flow architecture of the electronic system. Finally, a power roll-up calculation is performed on the power flow architecture of the electronic system design in order to yield a final system power value for the electronic system design.

Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.

Abstract: According to various embodiments, a computing system may be provided. The computing system may include: a circuit configured to operate at a plurality of operation frequencies; a graphics output configured to output image data for display; a rate determiner configured to determine a frame rate of the graphics output; and a frequency setter configured to set an operation frequency of the circuit based on the determined frame rate.

Abstract: According to an embodiment, storage configurations are identified for storing items, such as database tables, partitions, or any other types of objects or data structures, within a desired storage area, such as an in-memory data store or any other limited storage resource. Each of the storage configurations is assigned to a particular item of the items. Each of the storage configurations associates the assigned particular item with one or more storage configuration options. Storage recommendations are generated for at least a set of the storage configurations. A different storage recommendation exists for each storage configuration in the set of the storage configurations. The storage recommendation associates the storage configuration with a range of possible storage sizes for a particular storage area of a system. Based on the storage recommendations, recommended system configurations a generated for different possible storage sizes of the particular storage area.

Abstract: An electrical connector device for connecting a bus bar to one or more electrical contacts of a circuit interrupting device is provided. The electrical connector device includes an electrically conductive body having a first end configured to engage the one or more electrical contacts of the circuit interrupting device, and a second end configured to engage the bus bar. The electrically conductive body includes a central portion and an outer portion, and has a cavity defined therein between the central portion and the outer portion. The electrical connector device also includes an evaporative heat transfer device including a wick and a working fluid each disposed within the cavity defined within the electrically conductive body. The heat transfer device is configured to facilitate heat transfer from the first end of the electrically conductive body to the second end.

Abstract: A reconfigurable, multi-core processor includes a plurality of memory blocks and programmable elements, including units for processing, memory interface, and on-chip cognitive data routing, all interconnected by a self-routing cognitive on-chip network. In embodiments, the processing units perform intrinsic operations in any order, and the self-routing network forms interconnections that allow the sequence of operations to be varied and both synchronous and asynchronous data to be transmitted as needed. A method for programming the processor includes partitioning an application into modules, determining whether the modules execute in series, program-driven parallel, or data-driven parallel, determining the data flow required between the modules, assigning hardware resources as needed, and automatically generating machine code for each module.

Abstract: Technologies for secure hybrid standby power management include a computing device with a processor supporting low-power idle standby. An operating system writes a power management sleep request, such as an ACPI S3 request, to a power management control register of the computing device. The processor traps the write to the power management control register and executes a firmware sleep mapper that causes the processor to enter an idle standby power state such as S0ix. The firmware sleep mapper may be included in a firmware isolated memory region. The address of the firmware sleep mapper may be included in a model-specific register of the processor. The processor may verify the firmware sleep mapper before execution. In response to a wake event, the processor resumes the firmware sleep mapper, which switches the processor to real mode and jumps to a waking vector of the operating system. Other embodiments are described and claimed.

Abstract: A semiconductor device includes a first clock control circuit for controlling a first clock source; a second clock control circuit for sending a first clock request to the first clock control circuit in response to a block clock request from an intellectual property (IP) block, and controlling a second clock source, which receives a clock signal from the first clock source, to generate a stopped clock signal, which is a clock signal turned off for a predetermined amount of time; and a driver circuit for receiving a block control signal, and outputting the block control signal to the IP block while the short stopped clock signal is output to the IP block.

Abstract: One embodiment relates to a method of saving power in a memory subsystem. A first procedure is performed to save memory controller power by changing a clock toggle rate, and a second procedure is performed to save memory subsystem power by changing a clock frequency for the memory subsystem. A third procedure is performed to rebound back to full speed. Another embodiment relates to a memory subsystem which includes a memory controller, a memory, and a physical input/output interface. The memory controller performs at least a first procedure to save memory controller power by changing a clock toggle rate. Other embodiments and features are also disclosed.

Abstract: In an embodiment, a processor includes at least one processor core and at least one graphics processor. The at least one graphics processor may include a register file having a plurality of entries, where at least a portion of the at least one graphics processor is to operate at a first operating frequency and the register file is to operate at a second operating frequency greater than the first operating frequency, to enable the at least one graphics processor to issue a plurality of write requests to the register file in a single clock cycle at the first operating frequency and receive a plurality of data elements of a plurality of read requests from the register file in the single clock cycle at the first operating frequency. Other embodiments are described and claimed.

Abstract: A method includes detecting a communication event over a communication bus 130 coupled to a device, and in response to detecting the communication event, deactivating a module of the device. The method may further include sending a data throttle packet over the communication bus 130 while the deactivated module reactivates.