Abstract: Methods and devices are provided for monitoring a battery to determine whether sufficient battery power remains to perform an event at a pre-scheduled time. A communications device includes a processor that receives instructions to perform the event at the pre-scheduled time, determines a first amount of time until the event is performed, detects an idle mode of the communications device, the idle mode consuming a minimum amount of power, calculates a second amount of time until the battery is depleted, the second amount of time being calculated while the communications device operates in the idle mode, determines whether the second amount of time is less than the first amount of time, activates a first alert if the second amount of time is less than the first amount of time while remaining in the idle mode, and performs an action prior to the pre-scheduled time while remaining in the idle mode.

Abstract: A multiprocessor system dynamically updates CPU affinities for processes executing on processors of the multiprocessor system based on an external signal. The external signal is generated by a monitor device. The external signal identifies the processors and the processes that require updating. In response to the external signal, the multiprocessor system redistributes the processes identified in the external signal and powers on or off one or more processors based on a processor threshold associated with the multiprocessor system.

Abstract: A display apparatus for a portable terminal includes an expandable flexible display unit, a sensing unit including of a plurality of magnets and a plurality of sensors sensing the magnets to sense an amount of display unit area accommodated in an accommodation unit of the display unit, and a controller setting pixel values according to sensed amount of the display unit area.

Abstract: An image forming apparatus includes a first volatile storage unit storing information for returning the image forming apparatus to a normal startup state, a second non-volatile storage unit storing the information for returning the image forming apparatus to the normal startup state, and a control unit configured to, if the image forming apparatus being performing normal job processing is shifted to the power-saving mode, switch between a hibernation mode and a quick mode depending on a shift time to the hibernation mode, the hibernation mode in which the control unit causes the second storage unit to store information for performing the normal job processing to shift the image forming apparatus to the power-saving mode, the quick mode in which the control unit causes the first storage unit to store the information for performing the normal job processing to shift the image forming apparatus to the power-saving mode.

Abstract: Systems and methods for reducing power consumption of systems using serialized data transmission. In a multi-node system, the reiterative steps for the setup of the lanes within links between the nodes produces both a time invariant set of parameters associated with the channel properties of the lanes and a time variant set of parameters associated with receiver clock alignment. The time invariant set is stored in persistent storage. Links may be turned on and turned off. When a link is turned on again, the stored time invariant set may be used as initial values to reconfigure both the time invariant and the time variant sets, thereby greatly reducing the delay to begin using the link again. The reduced delay may significantly speed up the wakening process for the links, thereby encouraging the use of low-power techniques that include tuning off lanes.

Abstract: Embodiments of the invention describe systems and processes directed towards reducing memory subsystem idle power consumption. Embodiments of the invention enable low power states for various components of a memory subsystem under certain operating conditions, and exiting said low power states under certain operating conditions. Embodiments of the invention may comprise of logic, modules or any combination thereof, to detect operating conditions in a computing system. Some of these operating conditions may include, but are not limited to, a memory controller being empty of transactions directed towards its respective memory unit(s), a processor core executing a processor low-power mode, and a processor socket (operatively coupling the processing core and the memory unit) executing an idle mode. In response to detecting said operating conditions, embodiments of the invention may execute a low-power idle state for the memory unit(s) and various components of the memory subsystem.

Abstract: Provided according to one or more embodiments herein are methods, systems and related architectures for facilitating network communications between a wireless network-connected thermostat and a cloud-based management server in a manner that promotes reduced power usage and extended service life of a rechargeable battery of the thermostat, while at the same time accomplishing timely data transfer between the thermostat and the cloud-based management server for suitable and time-appropriate control of an HVAC system.

Abstract: The present invention relates to a method for reducing the electricity consumption of an Ethernet interface involving switching to a low power mode when no activity is detected on the physical layer thereof for a first predetermined duration (T_L1_INACTIVE). The method is characterized in that the interface also switches to a low power mode when no activity is detected on the MAC layer thereof for a second predetermined duration (T_L2L).

Abstract: In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by translating virtual memory addresses into physical addresses on a computing system having hybrid memory. In a first stage of memory translation, an operating system translates virtual addresses to intermediate physical addresses. In a second stage of memory translation, a chip or virtualization software translates the intermediate physical address to physical addresses based on the characteristics of the physical memory and the characteristics of the processes associated with the physical memory.

Abstract: The graphics pipeline produces real time utilization data for each of a plurality of functional units making up an overall graphics processor or graphics system on a chip. This information may be used for fine grain management of power consumption and performance at the functional unit level as opposed the overall device level. As a result, the graphics functional units may be managed dynamically based on real time hardware metrics to improve performance and reduce power consumption. The technique may be implemented in a software module in one embodiment.

Abstract: An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Abstract: A receiving apparatus including a first communication unit that receives first image data from a transmission apparatus, a second communication unit that receives second image data from the transmission apparatus, a power supply unit that supplies power to at least one of the first communication unit and the second communication unit, and a control unit that causes a display device to display an image generated based on the first image data and the second image data, where the control unit controls the power supply unit so as to limit power supply to one of the first communication unit and the second communication unit in response to completion of the display of the image by the display device.

Abstract: An image forming apparatus is connected to a host device including first and second power domains which are separately supplied with power and includes first and second memories to be disposed in the second power domain, a main controller disposed in the first power domain and to perform a control operation using the first memory in a normal mode, and a sub-controller disposed in the second power domain and perform a control operation using the second memory in a power-saving mode, where when the normal mode is changed to the power-saving mode a power supply to the first power domain is shut off, the first memory operates in a self-refresh mode, and the main controller copies central processing unit (CPU) context information into a context storage unit, and when the power-saving mode is changed to the normal mode, the main controller is booted using the CPU context information stored in the context storage unit.

Abstract: A method of controlling an integrated circuit chip including first and second clock sources, the first clock source being more thermally stable and having a higher power consumption, the integrated circuit chip being operable in a first mode in which the first clock source is inactive and the second clock source active and in a second mode in which the first and second clock sources are active, the method including operating the integrated circuit chip in the first mode; taking a measurement indicative of temperature; if the measurement indicates that the temperature is outside of a temperature band: activating the first clock source so as to operate the integrated circuit chip in the second mode; recalibrating the second clock source against the first clock source; and following the recalibration, deactivating the first clock source so as to return the integrated circuit chip to the first mode.

Abstract: According to an embodiment, a control system includes a detector, an estimating unit, a determining unit, and a controller. The detector detects an idle state. The estimating unit estimates an idle period. When the idle state is detected, the determining unit determines whether a first power consumption when writeback of data which needs to be written back to a main storage device is performed and supply of power to a cache memory is stopped, is larger than a second power consumption when writeback of the data is not performed and supply of power is continued for the idle period. The controller stops the supply of power to the cache memory when the first power consumption is determined to be smaller than the second power consumption and continues the supply of power when the first power consumption is determined to be larger than the second power consumption.

Abstract: We report methods, integrated circuit devices, and fabrication processes relating to power management transitions of multiple compute units sharing a cache. One method includes indicating that a first compute unit of a plurality of compute units of an integrated circuit device is attempting to enter a low power state, determining if the first compute unit is the only compute unit of the plurality in a normal power state, and in response to determining the first compute unit is the only compute unit in the normal power state: saving a state of a shared cache unit of the integrated circuit device, flushing at least a portion of a cache of the shared cache unit, repeating the flushing until either a second compute unit exits the low power state or the cache is completely flushed, and permitting the first compute unit to enter the low power state.

Abstract: Automated infrastructure management systems and methods document infrastructure elements within a facility, provide a comprehensive record of all network-connected equipment within a facility, and facilitate trouble shooting of network-connected equipment. An automated infrastructure management system includes a plurality of intelligent patch panels, each comprising a plurality of connector ports connected to individual communication channels of a network, a controller in communication with at least some of the intelligent patch panels that obtains connectivity information for the intelligent patch panel's ports, and management software in communication with the controller.

Abstract: A processor is described that includes a plurality of execution cores. The processor also includes power management circuitry to dynamically determine a number of the execution cores that, when active, will cause the processor to operate in a substantially linear power consumption vs. frequency region of operation such that performance gain as a function of power consumption increase with the number of cores is higher as compared to any other number of active execution cores within an established power envelope.

Abstract: A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the cores in the multicore processor; and restoring, when the suspend instruction is detected, data stored in a volatile memory accessed by a core receiving the suspend instruction, the data being restored in a shared memory accessed by the cores in operation and based on parity data stored in the volatile memories accessed by the cores in operation other than the core receiving the suspend instruction.

Abstract: A memory device includes a voltage regulator, whose output provides a voltage supply for various other components of the memory device, including a command user interface. The memory device is placed into an ultra-deep power-down mode by providing to the memory device a software command, which causes the output of the voltage regulator to be disabled. To bring the memory device out of the ultra-deep power-down mode, a chip select signal is provided to the memory device, which includes a wake-up circuit that remains powered on even when the memory device is in the ultra-deep power-down mode. Receipt of the chip select signal while the memory device is in the ultra-deep power-down mode causes the output of the voltage regulator to be enabled, thereby providing power to the components that were completely powered down.

Abstract: Power management system or a touch controller can include a transmit section for transmitting stimulation signals to an associated touch sensor panel to drive the panel, where the touch controller can selectively adjust the transmit section to reduce power during the transmission. The touch controller can also include a receive section for receiving touch signals resulting from the driving of the panel, where the touch controller can selectively adjust the receive section to reduce power during the receipt of the touch signals. The touch controller can also include a demodulation section for demodulating the received touch signals to obtain touch event results, where the touch controller can selectively adjust the demodulation section to reduce power during the demodulation of the touch signals. The touch controller can also selectively reduce power below present low levels during idle periods. The touch controller can be incorporated into a touch sensitive device.

Abstract: Systems and methods are provided for placing a portion of a memory into a low power mode. A system includes a hot spot region creator configured to determine an activity level for each of a plurality of regions of a memory, where certain of the regions are determined to be active regions, and where certain of the regions are determined to be inactive regions and rearrange the data to position the active region data in a contiguous active portion of memory and to position the inactive regions data in a contiguous inactive portion of memory. A memory controller is configured to place the contiguous inactive portion of memory into a low power mode.

Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

Abstract: A status switching method for a mobile device is disclosed. The status switching method includes receiving a first request for switching a radio function of the mobile device from a first status to a second status; keeping the radio function in the first status for a specific duration; switching the radio function to the second status if not receiving a second request for switching the radio function of the mobile device from the second status to the first status during the specific duration; and remaining the radio function in the first status if receiving a second request for switching the radio function of the mobile device from the second status to the first status during the specific duration; and switching the radio function to the first status.

Abstract: An information processing device (1) includes a main CPU (2) and a sub CPU (3). The main CPU (2) is provided with a function of managing schedules of task processing and idle processing and executes sleep control which reduces power consumption of the main CPU (2) as the idle processing when the task processing is not executed. The sub CPU (3) measures elapsed time during which the sleep control is executed, detects an interrupt event occurring during the sleep control, and notifies the elapsed time until the interrupt event occurs to the main CPU (2). The main CPU (2) terminates the sleep control in accordance with the notification of the elapsed time and reflects the elapsed time in the schedule. As a result, inconsistency of a timer caused by the sleep control can be solved, and the information processing device which can use a scheduler correctly even if the sleep control is executed is provided.

Abstract: According to one embodiment, a semiconductor storage device includes a nonvolatile memory, memory controller storing control information, a switch between the nonvolatile memory/memory controller and a power supply terminal, a second memory, an interpreter interprets a command, a switch controller, and a third memory stores an address of the control information in the second memory. The memory controller instructs the switch controller to open the switch after writing the control information into the second memory and reads the control information from the second memory based on the address stored in the third memory when the memory controller is electrically connected to the first power supply terminal.

Abstract: Various embodiments are described herein with regards to performing a selective fault recovery for an electronic device having a plurality of subsystems in which one of the subsystems has a fault. The selective fault recovery techniques described herein allow a user to use non-faulty subsystem of the electronic device while selective fault recovery is being conducted on the subsystem having the fault.

Abstract: One embodiment provides an information processing apparatus including a processor; memory blocks; an internal voltage generator connected to the memory blocks; an input/output circuit connected to the memory blocks; switches each installed corresponding to the internal voltage generator, the input/output circuit, and the memory blocks, and configured to switch ON/OFF of the connection with a power source; a data register configured to store a data set that controls the ON/OFF of the switches; and a data management circuit configured to set the data set in the data register, wherein when a clock signal input to the processor is turned to OFF, the data management circuit generates a first type of the data set, which switches ON the switch connected to the internal voltage generator and switches OFF the switches connected to the memory blocks, and sets the first type of the data set in the data register.

Abstract: In accordance with at least one embodiment, memory power gating at word level is provided. In accordance with at least one embodiment, a word level power-gating technique, which is enabled by adding an extra control bit to each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.) of a memory array, provides fine-grained power reduction for a memory array. In accordance with at least one embodiment, a gating transistor is provided for each subarray (e.g., each word, each row, each wordline, each bitline, each portion of an array, etc.).

Abstract: Methods and apparatus to optimize package level power state usage are described. In one embodiment, a processor control logic receives a request to enter a lower power consumption state (such as a package level deeper sleep state). The control logic determines the time difference or delta between a last entry into the lower power consumption state and the current time. The control logic then causes the flushing of a last level cache based on a comparison of the time difference and a threshold value corresponding to the lower power consumption state. Other embodiments are also claimed and disclosed.

Abstract: Systems and methods are disclosed for providing multi-user power saving codebook optimization. One such method comprises: generating a unique codebook for a plurality of computing devices, each unique codebook configured for encoding memory data in the corresponding computing device; providing the unique codebooks to the corresponding computing devices via a communications networks; receiving compression statistics from one or more of the computing devices via the communications network, the compression statistics related to the corresponding unique codebook; and generating an optimized codebook for at least one of the computing devices based on the received compression statistics.

Abstract: The method for adjusting a shutdown threshold voltage includes: obtaining a current voltage of a battery of an electronic device; when the current voltage is greater than or equal to a lowest shutdown threshold of the electronic device and less than or equal to a general shutdown threshold of the electronic device, obtaining at least one piece of application information of at least one application program, where an application shutdown threshold of an application program corresponding to each piece of application information of the at least one piece of application information is greater than the lowest shutdown threshold and less than or equal to the current voltage; and setting a current shutdown threshold, which is corresponding to the current voltage, of the electronic device to a maximum application shutdown threshold of at least one application shutdown threshold corresponding to the at least one application program.

Abstract: A processing node tracks probe activity level associated with its cache. The processing node and/or processing system further predicts an idle duration. If the probe activity level increases above a threshold probe activity level, and the idle duration prediction is above a threshold idle duration threshold, the processing node flushes its cache to prevent probes to the cache. If the probe activity level is above the threshold probe activity level but the predicted idle duration is too short, the performance state of the processing node is increased above its current performance state to provide enhanced performance capability in responding to the probe requests.

Abstract: A mechanism is provided for run-time task-level dynamic energy management. An instruction address for a first instruction of the application is mapped to a portion of application code in the application in response to an application being marked for energy management. A monitoring of the hardware resource activities is done for the portion of the application code. A level of energy management is then implemented for the portion of the application code based on a value of the tick indicator, resource activities, and an intensity indicator.

Abstract: A power-saving method for a first-in-first-out (FIFO) buffer implemented in a memory. The memory is segmented into a plurality of logical segments. For each logical segment, for each power saving mode, a recovery time and recovery overhead to an operational mode, and a transition overhead for transitioning the logical segment into the power saving mode, are determined. During each clock cycle, a determination is made as to whether a net power saving will result by entering each logical segment into a power saving mode based on a minimum time before a read or write pointer will enter the logical segment as well as the recovery time, the recovery overhead, and the transition overhead. The logical segment is transitioned to the power saving mode only if a net power saving will result, and is returned to the operational mode when the minimum time is no longer greater than the recovery time.

Abstract: A system and method of dynamically managing a power supply allocation for each one of the server blades in a blade server includes a blade server system having a blade chassis, multiple server blades coupled to the blade chassis, a power supply system coupled to the blade chassis, a chassis management module coupled to the blade chassis, wherein the blade chassis includes electrical and data communication interconnections between the server blades, the redundant power supply system and the chassis management module. The chassis management module includes computer readable media having program instructions for dynamically managing a power supply allocation for each one of the server blades.

Abstract: Techniques are described to transmit commands to a display device. The commands can be transmitted in header byte fields of secondary data packets. The commands can be used to cause a target device to capture a frame, enter or exit self refresh mode, or reduce power use of a connection. In addition, a request to exit main link standby mode can cause the target enter training mode without explicit command to exit main link standby mode.

Abstract: Embodiments of the invention are generally directed to a low power standby mode control circuit. An embodiment of an apparatus includes a processor, an interface for a connection with a second apparatus, and an operational circuit, wherein the processor is to disable one or more power connections to the operational circuit in a standby mode. The apparatus further includes a standby mode control circuit, the standby control circuit to operate using a standby power source, wherein the standby mode control circuit is to detect a stimulus signal from the second apparatus and in response to the stimulus signal the standby control circuit is to signal the processor, the processor to enable the one or more power connections of the operational circuit.

Abstract: An image forming apparatus includes first and second memories, and a main controller and a sub-controller. The main controller performs a control operation using the first memory in a normal mode state, the sub-controller is mounted on an engine unit provided in the image forming apparatus to perform an image forming job by driving the engine unit in a normal mode state under the control of the main controller, the main controller transmits a low-power mode change request to the sub-controller if a condition for changing a mode state from the normal mode state to a low-power mode state is satisfied, and the sub-controller copies a low-power service program stored in the first memory into the second memory if the low-power mode change request is received, and performs a low-power service by executing the low-power service program through accessing of the second memory.

Abstract: Systems and methods are provided for implementing a persistent battery system shutdown condition when a battery pack voltage level drops below a predetermined minimum acceptable operating voltage threshold that is above a pre-determined permanent failure operating voltage threshold at which the battery pack is permanently disabled. The disclosed systems and methods may be implemented such that shutdown portion of the power-consuming components of the information handling system are not allowed to be restarted until external power has been first provided and applied to at least partially recharge the battery cells of the battery pack to a battery voltage level that is above the minimum acceptable operating voltage threshold and/or when sufficient external power is applied to power the information handling system and at the same time charge the battery cells of the battery pack.

Abstract: A temperature sensor may sense the temperature of a multi-core processor. In response to the temperature of the multi-core processor exceeding a temperature threshold for the multi-core processor, one or more busy processor cores of the multi-core processor may be power collapsed without reducing clock speed of the multi-core processor.

Abstract: A system and method for managing battery usage of a mobile device. The power level of the battery is obtains and compared to a threshold level. When the power level is equal to or less than the threshold level, user applications that are operating on the mobile device are identified. Operating user applications that are members of a set of user applications are identified. The execution of the selected user application is suspended or terminated.

Abstract: A technique for operating a processor includes detecting an interrupt having a first core of the processor as a destination core. The technique includes handling the interrupt by a second core of the processor in response to the first core being in a low-power state. The first core may be capable of executing a greater number of instructions-per-cycle than the second core and the second core may consume less power than the first core. The first core may be coupled to a first voltage plane and the second core may be coupled to a second voltage plane having lower power than the first voltage plane.

Abstract: An electronic control unit of one embodiment includes first and second microcomputers for mutually monitoring operations, an output circuit for outputting a signal that is outputted from at least one of the first and second microcomputers, a power supply circuit for supplying electric power to the output circuit, and a stop unit for stopping supply of the electric power from the power supply circuit to the output circuit. The first microcomputer has operation modes including a normal mode and a low power mode. In the low power mode, the first microcomputer stops monitoring the operation of the second microcomputer and outputs a power supply stop signal that operates the stop unit to stop the supply of the electric power from the power supply circuit to the output circuit.

Abstract: Systems and methods presented herein provide a storage system that adaptively powers-down one or more disk drives based on the predicted idle time of each disk drive. One embodiment includes a storage controller that includes a processor operable to track idle durations of the disk drive. When an idle duration ends, the processor associates the idle duration with a time window that includes that idle duration. Each time window is associated with a number of previous idle durations of the disk drive. Upon detection of a current idle duration, the processor identifies a time window with the highest number of previous idle durations of the disk drive. Then, the processor determines whether a maximum time associated with the identified time window exceeds a predetermined threshold. When the maximum time exceeds the predetermined threshold, the processor powers-down the disk drive.

Abstract: One or more techniques and/or systems are provided for regulating an amount of power on a power grid using a datacenter. This allows demand to be more closely brought into alignment with supply. For example, when supply exceeds demand by a predetermined level, the datacenter may increase consumption, causing demand to increase, and when demand exceeds supply and/or comes within a predetermined threshold of supply, the datacenter may decrease consumption, causing demand to decrease. In this way, the datacenter can be utilized as a regulatory tool on the grid. It may be appreciated that given the technology used by and/or operations performed by datacenters, datacenters are uniquely situated to achieve these ends as compared to other (large) energy consumers, such as manufacturing facilities that cannot shift around and/or shut-down operations swiftly.

Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Abstract: Techniques and apparatuses for providing power-aware thread scheduling and dynamic use of processors are disclosed. In some aspects, a multi-core system is monitored to determine core activity. The core activity may be compared to a power policy that balances a power savings plan with a performance plan. One or more of the cores may be parked in response to the comparison to reduce power consumption by the multi-core system. In additional aspects, the power-aware scheduling may be performed during a predetermined interval to dynamically park or unpark cores. Further aspects include adjusting the power state of unparked cores in response to the comparison of the core activity and power policy.

Abstract: The present invention provides a METHOD AND APPARATUS FOR HOLISTIC POWER MANAGEMENT TO DYNAMICALLY AND AUTOMATICALLY TURN SERVERS, NETWORK EQUIPMENT AND FACILITY COMPONENTS ON AND OFF INSIDE AND ACROSS MULTIPLE DATA CENTERS BASED ON A VARIETY OF PARAMETERS WITHOUT VIOLATING EXISTING SERVICE LEVELS. This method and apparatus pertains specifically to a method and apparatus for power management in data centers and large server environments. Until today all servers running a specific application or virtualized environment are kept turned on to support various levels of application demand. With the invention of Holistic Power Management this invention completely automates the tasks required to shutdown and turn off servers not needed and to turn them on and start them up independent of their physical location. Furthermore this invention makes such changes dynamically based on application load, environmental conditions and energy pricing and availability and can adjust cooling services accordingly.

Abstract: When a bus stop request control unit issues a module-specific bus stop request signal, a bus stop control unit coupled to a bus slave determines a module that serves as a bus master of the bus slave and on which the bus slave is dependent, for example, on the basis of information in a dependence setting register. The bus stop control unit then outputs a prior bus stop request signal to the module on which the bus slave is dependent, so as to stop use of a bus of the module. Upon receipt of a module-specific bus stop completion signal indicating that processing of stop of the bus of the module on which the bus slave is dependent is complete, the bus stop control unit outputs a module-specific bus stop request signal to the module which serves as a bus slave and whose bus is to be stopped.