Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract: In a case where a first condition is met while a communication device may in a high consumption state, the communication device may transit to a first low consumption state. In a case where a second condition is met while the communication device is in a specific state which is one state of the high consumption state and the first low consumption state, the communication device may transit to a second low consumption state. The communication device may be configured to execute a packet process in a case where a receiving process for receiving a packet is executed after the communication device had transited to the first low consumption state. The communication device may be configured not to execute the packet process in a case where the receiving process for receiving the packet is executed after the communication device had transited to the second low consumption state.

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract: A technique for performing power management for configurable processor resources of a processor determining whether to increase, decrease, or maintain resource units for each of the configurable processor resources based on utilization of each of the configurable processor resources. A total weighted power number for the processor is substantially maintained while resource units for each of the configurable processor resources whose utilization is above a first level is increased and resource units for each of the configurable processor resources whose utilization is below a second level is decreased. The total weighted power number corresponds to a sum of weighted power numbers for the configurable processor resources.

Abstract: A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system, obtaining the current performance state level and at least an operable performance state levels of the processor when the system firmware determines that the temperature and loading of the processor exceeds a predetermined value respectively, wherein the performance state level is associated to the frequency of the processor, and setting the processor to one of the operable performance state levels, wherein the frequency of the performance state level is lower than the frequency of the current performance state level, according to the current performance state level and the operable performance state levels.

Abstract: A method of power management for devices in a data storage fabric is disclosed. The data storage fabric includes a PHY having a first power condition and a second power condition coupled to a power condition independent device on the data storage fabric. The power condition independent device detects a change in the power configuration of the PHY from the first power condition to the second power condition. The power condition independent device then changes its power state to a comparable power state preselected to correspond with the second power condition.

Abstract: Energy saving circuit of a computer is connected between a power supply and a motherboard. The energy saving circuit includes six electronic switches and a switch. When the computer is in the stand-by state, and the switch is pressed, the motherboard of the computer receives a standby voltage and the motherboard maintains the stand-by state. The energy-saving circuit can shut off the standby voltage by pressing the switch when the computer is powered off to save energy.

Abstract: A system and method for power management of storage resources are disclosed. A method may include detecting an occurrence of an event associated with a storage resource disposed in an array of storage resources. The method may further include transitioning the storage resource into a specified power state in response to the detection of the occurrence of the event. A system may include a storage resource and a power management module communicatively coupled to the storage resource. The storage resource may be disposed in an array of storage resources. The power management module may be operable to detect an occurrence of an event associated with the storage resource, and may be operable to transition the storage resource into a specified power state in response to the detection of the occurrence of the event.

Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.

Abstract: An inertial force sensor includes the following elements: a sensor element for converting an inertial force into an electrical signal; a sensor signal processor connected to the sensor element, for outputting an inertial force value; and a power controller for controlling electric power supply to the sensor signal processor, based on the inertial force value. When the inertial force value is maintained for a predetermined time period within a predetermined range in which a reference value is the middle value of the range, the power controller reduces the electric power supply to the sensor signal processor and updates the reference value to the inertial force value obtained after a lapse of the predetermined time period.

Abstract: A processor includes a communicating unit, a receiving unit, a processing unit, and a power-off controller. The receiving unit receives an operation from a user. The processing unit executes processing according to a processing request received by at least one of the communicating unit and the receiving unit. If a power-off request is received from a terminal by the communicating unit, the power-off controller stops the processing unit and disconnects a power supply when the operation received from the user by the receiving unit is not being processed and a condition determined in accordance with a processing mode of the power-off request is satisfied.

Abstract: Based on bounds of a period of reduced operation for a base device, a base device generates a power management message for transmission to a peripheral device. In the power management message, the base device inserts bounds of a period of reduced operation for the peripheral device. As a result, the periods of reduced operation conserve battery power in both devices and the two devices may reestablish a communications channel upon reaching the end of the period of reduced operation and resuming normal operations.

Abstract: When there is a memory module mounted in a memory slot, a memory power circuit provides a voltage to the memory slot. First and second power pins of the memory slot are connected. A first electronic switch is turned on. A second electronic switch is turned off. A programmable logic controller (PLC) outputs a first control signal to the memory power circuit to output the voltage to the memory slot. When there is no memory module mounted in the memory slot and the motherboard is powered on, the memory power circuit provides a voltage to the memory slot. The first and second power pins of the memory slot are disconnected. The first electronic switch is turned off. The second electronic switch is turned on. The PLC outputs a second control signal to control the memory power circuit not to output the voltage to the memory slot.

Abstract: In one embodiment, the present invention includes an apparatus having a core including functional units each to execute instructions of a target instruction set architecture (ISA) and a power controller to control a power mode of a first functional unit responsive to a power identification field of a power instruction of a power region of a code block to be executed on the core. Other embodiments are described and claimed.

Abstract: There is provided a signal processing device which is capable of suppressing the influence of a digital data process on an analog signal process without completely stopping a digital data processing circuit. A signal, processing device includes an analog signal processing circuit, a digital data processing circuit, a determination section configured to determine an influence of the digital data processing circuit on the analog signal processing circuit, and a control section configured to stop a partial circuit of the digital data processing circuit or lower processing capability thereof in response to a determination result of the determination section.

Abstract: A deactivated passive user interaction sensor may be activated or deactivated on demand based on an expected use of the sensor. The expected use may be ascertained by detecting a predetermined user interaction at another sensor that is already active. Once the predetermined user interaction is detected, the active sensor may be deactivated and the sensor that is expected to be used may be activated. Total sensor power consumption may be reduced by providing a predetermined sensor activation and deactivation sequence for at least three sensors in a computing system based on predetermined user interactions with an active sensor. Methods, apparatuses, systems, and computer readable media are provided.

Abstract: A component control system includes a component. At least one component element is included in the component. A component controller is included in the component, coupled to the at least one component element, and operable to couple to an Information Handling System (IHS) controller. The component controller is operable to receive a normalized component performance (NCP) value from the IHS controller. The NCP value is associated with at least one component output range. The component controller is also operable to provide a control signal that is associated with the NCP value to the at least one component element. In response to receiving the control signal, the at least one component element operates such that the component produces at least one component output, and each component output produced by the component is within a corresponding component output range.

Abstract: Example embodiments disclosed herein relate to a computing system including a controller hub to control system sleep states, and an embedded controller including an internal timer. The embedded controller is to remove power from the controller hub when the system enters a sleep state and to enable power to the controller hub prior to the system wake time. The internal timer is to determine when to enable power to the controller hub. Example methods and machine-readable storage media are also disclosed.

Abstract: A High Speed Inter Chip (HSIC) system and method for minimizing power consumption by controlling the state of the HSIC module through a control line are provided. The method between a host and a slave includes transitioning, when no communication request exists for a first reference time in an active state where all functions of the HSIC modules are enabled, to a suspend state where least functions used for maintaining a communication link of the HSIC modules and transitioning, when no communication request exists for a second reference time in the suspend state, to a power-off state where the HSIC modules turn off The HSIC communication method and apparatus are advantageous to minimize the electric current consumption of the HSIC consumption system.

Abstract: The present invention relates to a method and device that conserves power. In some embodiments, the device is a battery powered storage device. The invention employs a large cache and aggressive caching algorithm to serve data from the storage media (hard disk or SSD) or write data to the storage media. The cache provides an efficient location from which to serve data, especially multi-media. In one embodiment, the algorithm determines when to place the drive into a lower power state, such as idle, or standby, based on the amount of anticipated idle time provided by the large cache.

Abstract: A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node includes a network port, a network chip and a control unit. The network port is connected to the network switch via a cable. The network chip detects the cable to obtain a connection state with the external network at the server node after the network switch is started, and accordingly outputs a connection state signal. The control unit turns on or shuts down the server node according to the connection state signal and an on/off state of the server node.

Abstract: A power supply circuit includes a basic input output system (BIOS), a super input output (SIO), a bivibrator, a logical selector, and a voltage converter. The basic input output system (BIOS) is configured for storing different operation modes of a computer. The super input output (SIO) is configured for generating standby mode signals according to the different operation modes. The bivibrator is configured for generating a reference signal when upon receiving a clock signal from the computer when the computer is turned on. The logical selector is configured for generating a standby control signal in response to the reference signal and one of the standby mode signals. The voltage converter is configured for transforming the first standby voltage into a second standby voltage to drive the SIO. The SIO receives the second standby voltage before the clock signal is delayed and provided to the SIO to start the computer.

Abstract: A device managing apparatus for monitoring and managing a device connected to a data transmission path includes an obtaining part configured to obtain power consumption status data from the device, the power consumption status data indicating a power consumption status of a communication unit included in the device, a selecting part configured to select a communication method according to the power consumption status data obtained from the obtaining part, and a communicating part configured to perform data communications with the device by using the communication method selected by the selecting part.

Abstract: A method of operating a processing device is provided. The method includes, responsive to an idle state of the processing device, transitioning the processing device to a substantially disabled state. The processing device, for example, may be a graphics processing unit (GPU). Transitioning the processing device to a substantially disabled state upon detection of an idle state may result in power savings. Corresponding systems and computer program products are also provided.

Abstract: A mechanism is provided for minimizing power consumption for operation of a fixed-frequency processing unit. A number of timeslots are counted in a time window where throttling is engaged to the fixed-frequency processing unit. The number of timeslots where throttling is engaged is divided by a total number of timeslots within the time window, thereby producing a performance loss (PLOSS) value. A determination is made as to whether determining whether the (PLOSS) value associated with the fixed-frequency processing unit is greater than an allowed performance loss (APLOSS) value. Responsive to the PLOSS value being less than or equal to the APLOSS value, a decrease in voltage supplied to the fixed-frequency processing unit is initiated.

Abstract: An approach is provided for optimizing power consumption and costs associated with routing information over a transport environment. A first collection interval corresponding to retrieval of a first data set specifying power consumption information and associated cost information for a plurality of routing nodes is determined. The first data set is compared with a second data set specifying power consumption information and associated cost information for a second collection interval. Routing metrics of the plurality of routing nodes are determined based on the comparison, wherein the routing metrics specify relative desirability of the plurality of routing nodes for establishing one or more communication paths formed by one or more of the plurality of routing nodes based on the routing metrics.

Abstract: Various techniques for managing power consumption of computing devices within a data protection system are disclosed. For example, one method involves accessing policy information, which the policy information indicates when one or more data protection system activities should be performed and identifies whether a computing device is participating in the data protection system activities. Based upon this policy information, the method then identifies whether power consumption of the computing device can be reduced. In response to identifying that the power consumption of the computing device can be reduced, a power management command is automatically sent via a network. Performance of the power management command reduces the power consumption of the computing device.

Abstract: In various aspects, a portable electronic device includes electrical components supported by a housing, the electrical components including a user interface coupled to a processor and a storage medium including an emergency power storage module coupled to the processor. The portable apparatus further includes one or more power storage devices configured to provide electrical energy to the electrical components, at least one power storage device operably controlled by the emergency power storage module to provide emergency electrical energy to the electronic components for an emergency communication.

Abstract: A circuit for changing load operation using temporary power-off means having a power-off detection circuit with input end connected to a power source and its output end is connected to a microprocessor (MCU) connected to at least one load driving circuit. A load appliance is mounted on each of the load driving circuits. The microprocessor (MCU) has a program controlling each load appliance. During operation, the power is restored immediately after the power source is temporarily powered off, such that the power-off detection circuit detects a temporary turned-off signal and sends the signal to the microprocessor (MCU). Accordingly, the program to control each of the load appliances in the microprocessor (MCU) manipulates each load appliance for performing another operation or function.

Abstract: A method and circuit arrangement utilize a general purpose processing unit having a low power DSP mode for reconfiguring the general purpose processing unit to efficiently execute DSP workloads with reduced power consumption. When in a DSP mode, one or more of a data cache, an execution unit, and simultaneous multithreading may be disabled to reduce power consumption and improve performance for DSP workloads. Furthermore, partitioning of a register file to support multithreading, and register renaming functionality, may be disabled to provide an expanded set of registers for use with DSP workloads. As a result, a general purpose processing unit may be provided with enhanced performance for DSP workloads with reduced power consumption, while also not sacrificing performance for other non-DSP/general purpose workloads.

Abstract: Technologies are described herein for providing power savings in a data center. Some example technologies may identify some user-provided hardware independent power saving codes from multiple virtual machines within the data center. The technologies may convert at least a portion of the user-provided hardware independent power saving codes into a device power management message specific to a computing system in the data center. The technologies may provide the device power management message to the computing system. The computing system may be configured to enable or disable one or more devices within the computing system according to the device power management message.

Abstract: The vector data path is divided into smaller vector lanes. The number of active vector lanes is controllable on the fly by the programmer to match the requirements of the executing program, and inactive vector lanes are powered down by the CPU to increase power efficiency of the vector processor.

Abstract: The present invention provides a communication system including a relay device that is capable of simplifying the configuration of a control device for controlling a device based on relay information and reducing cost of the whole system, the relay device and a method for controlling power supply. A GW device includes first to fourth communication parts respectively connected to communication buses, which are connected to ECUs respectively. The GW device receives a message transmitted from each of ECUs, extracts signal information S1 to S5 related to equipment in the vehicle included in the message from the received message, collects the extracted signal information S1 to S5 to create a message (ID4), and transmits the created message to a power supply control device. The power supply control device controls on/off of the ECUs and each of loads based on signal information included in the message received from the GW device.

Abstract: The present invention relates to an apparatus for blocking standby power of computer peripheral devices, comprising: a synchronization signal sensing control unit which senses the existence of horizontal and vertical synchronization signals provided to a monitor from a computer body, and outputs a switching control signal according to the sensed result; and a power switching unit which is provided with external power and situated on a power supply path for supplying power to the computer peripheral devices, and has a structure adapted for conducting or blocking the corresponding path according to the switching control signal.

Abstract: The operating voltage of an integrated circuit (e.g., a processor) is changed in response to one or more conditions (e.g., a laptop computer is connected to an AC power source). Both the operating frequency and the operating voltage of the integrated circuit are changed. The voltage regulator providing the operating voltage to the integrated circuit is caused to transition between voltage levels using one or more intermediate steps. The integrated circuit continues to operate in the normal manner both at the new voltage and throughout the voltage transition.

Abstract: A method and apparatus for user activity-based dynamic power management and policy creation for mobile platforms are described. In one embodiment, the method includes the monitoring of one or more sensor values of a mobile platform device to gather sensor activity data. Once the sensor activity data is gathered, the user state may be predicted according to the gathered user activity and an updated user state model. In one embodiment, the user state model is updated according to the sensor activity data. In one embodiment, a switch occurs from the present power management policy to a new power management policy if the new user state differs from a present user state by a predetermined amount. In one embodiment, at least one time-out parameter of a selected power management policy may be adjusted to comply with a predicted user state. Other embodiments are described and claimed.

Abstract: An indicator light control circuit includes a basic input output system (BIOS) integrated circuit (IC), a microcontroller, a signal control unit, an electronic switch, and an indicator light. The microcontroller includes a general purpose input output (GPIO) pin. When different operating options of the indicator light are set into and by the BIOS IC, the BIOS IC controls the GPIO pin of the microcontroller to output command signals, such as a low voltage signal, a high voltage signal and pulse signals, then the signal control unit generates and outputs signals according to the command signals. Thus, the electronic switch is operated to turn on or turn off or to pulse when controlling the operation of the indicator light(s).

Abstract: A media access control (MAC) security apparatus for a local area network interface includes a parser, an encryption engine, an authentication engine, and a first buffer. The parser is configured to output packets. The encryption engine is configured to receive the packets from the parser and generate encrypted data based on the packets received from the parser and cryptographic primitives. The encryption engine includes an advanced encryption standard engine configured to form the cryptographic primitives. The authentication engine is configured to perform authentication operations of the local area network interface based on the encrypted data from the encryption engine. The first buffer is configured to interface the encryption engine to the parser. The parser and the encryption engine process data at different rates. The first buffer is configured to compensate for the different rates.

Abstract: A method including: accounting for a transition time for a device to transition between two of first, second, and powered off states; generating a control signal based on the transition time; receiving, at the device and from a processor, an output signal and the control signal; and consuming power, via the device, while operating in the first state and the second state. The method further includes: in response to the control signal, transitioning the device to the second state based on a frequency of the output signal or the control signal; subsequent to transitioning to the second state, performing a function based on the first output signal; and subsequent to performing the function, generating an output via the device; generating a feedback signal based on the output; and based on the feedback signal, transitioning the device to either the first state or the powered off state.

Abstract: Techniques to control power and processing among a plurality of asymmetric cores. In one embodiment, one or more asymmetric cores are power managed to migrate processes or threads among a plurality of cores according to the performance and power needs of the system.

Abstract: Methods and systems are provided for managing power consumption in network devices. In a network device that may comprise a plurality of ports, each of which being identified by a unique identifier and being adapted to handle separate network traffic, it may be determined whether a first port of the network device may need to be reactivated, where the first port may have been previously shut down by directing of traffic corresponding to the first port, through a virtual port generated on a second port. When the first port is to be reactivated, the virtual port may be turned off, and the first port may then be reactivated. Traffic being routed through the virtual port may be routed before shutting it down; and the paused traffic to and from the network device may be resumed through the first port after it is reactivated.

Abstract: An embodiment of the invention includes a circuit to determine the power lost between a network device and a network power supply. Using this determination, an embodiment of the network device may increase its power consumption by an amount equal to the difference between the actual cable power loss and the worst-case cable power loss. This allows the network device to draw more power than allowed by network power standards without triggering the power-limiting circuitry of the network power source or overloading the network power device. The network device can determine an operating configuration that utilizes this additional power consumption to improve performance. The network device may also determine the existence of network power device or cable fault conditions, and adjust its operating configuration as necessary. Operating configurations can include enabling additional or more powerful wired or wireless network interfaces.

Abstract: The present invention features a personal computing device that may be powered by a single battery having a single lithium-ion cell or by a plurality of lithium-ion cells connected in parallel. The personal computing device may provide computing power comparable to that of conventional laptop computers and execute an operating system and application software comparable to that executed by conventional laptop computers. Furthermore, the battery's time between charging, when used to power the personal computing device, may be similar to the time between charging of a multi-cell battery when used to power a conventional laptop computer.

Abstract: The present invention features a personal computing device that may be powered by a single battery having a single lithium-ion cell or by a plurality of lithium-ion cells connected in parallel. The personal computing device may provide computing power comparable to that of conventional laptop computers and execute an operating system and application software comparable to that executed by conventional laptop computers. Furthermore, the battery's time between charging, when used to power the personal computing device, may be similar to the time between charging of a multi-cell battery when used to power a conventional laptop computer.

Abstract: In general, this disclosure describes techniques for managing power consumption states of a computing device. In one example, a method includes detecting, using at least one sensor of a computing device comprising a plurality of components, at least one indication of user contact with at least one surface of the computing device, wherein the at least one indication of user contact conforms with a touch pattern. The method further includes in response to detecting the at least one indication of user contact with at least one surface of the computing device, modifying a power consumption state of the computing device, wherein which components of the computing device receive power is based on the power consumption state.

Abstract: An audio device and a method of operating the same are provided. The audio device includes a storage unit, a first memory and a second memory, a hardware decoder, a software decoder, a first direct memory access (DMA) block, a second DMA block, and a controller. The controller converts the audio device from an ultra low power mode in which the first PCM information is transmitted to an audio interface buffer through the first memory, the hardware decoder, and the first DMA block or a low power mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the first DMA block to a normal mode in which the second PCM information is transmitted to the audio interface buffer through the second memory, the software decoder, and the second DMA block.

Abstract: Provided is a method in a control circuitry controlling the operations of a central processing unit, CPU. The CPU is associated with a nominal clock frequency. The CPU is further coupled to an I/O range and configured to deliver input to an application. According to the method, the control circuitry controls (110, 150) the CPU to poll the I/O range for input to the application. The control circuitry also monitors (120, 160) whether or not each poll results in input to the application and adjusts (140) a clock frequency at which the CPU operates to a clock frequency lower than the nominal clock frequency if a pre-defined number of polls resulting in no input is detected (130). A control circuitry and a central computer server of an automated exchange system are also provided.

Abstract: Provided is a liquid crystal display device wherein it is possible to specifically prevent the pseudo contouring of an area in which an image having a large motion vector is displayed, such as a telop area. A telop area (R1) (an example of a component image area) in which the motion vector is set in advance and which has a magnitude greater than or equal to a predetermined magnitude is detected. The intermittent lighting timing of an illumination portion is controlled in a manner such that the turn-off period having a predetermined length is set between the point in which the detected telop area (R1) writes a video signal to a liquid crystal element and the point in which the liquid crystal element responds.

Abstract: A disk array unit connected to a host unit to give information thereto and receive information therefrom. The disk unit includes a plurality of disk units for storing information transmitted from the host unit and a management information recording device, formed by utilizing information storage areas in the disk units, for causing information relating to a logical unit for storing information from the host unit to correspond to information relating to the units. The invention further includes a control unit, when there is no access from the host unit to the logical unit for a predetermined time, for determining the disk units corresponding to the logical unit based on information recorded in the management information recording device and performing power saving of power supply for the disk units.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.