Abstract: In some embodiments, the invention provides a higher efficiency, real-time platform power management architecture for computing platforms. A more direct power management architecture may be provided using integrated voltage regulators and in some embodiments, a direct power management interface (DPMI) as well. Integrated voltage regulators, such as in-silicon voltage regulators (ISVR) can be used to implement quicker, more highly responsive power state transitions.

Abstract: A mechanism is provided for an integrated circuit with power gating. A power header switch is configured to connect and disconnect any one of multiple circuits to a common voltage source, where a powered off circuit is disconnected from the common voltage source. A power-up sequencer includes an initial stages power-up component and a final stages power-up component. The final stages power-up component is configured to execute final stages of a power-up process for the powered off circuit, and the initial stages power-up component is configured to execute initial stages of the power-up process for the powered off circuit. The initial stages power-up component is activated in response to a predictive power-up request.

Abstract: A mechanism is provided for an integrated circuit with power gating. A power switch is configured to connect and disconnect circuits to a common voltage source. A capacitor tank is configured to supply wakeup charge to a given circuit. A controllable element is connected to the given circuit and to the capacitor tank. The controllable element is configured to controllably connect and disconnect the capacitor tank to the given circuit in order to supply the wakeup charge to the given circuit. The controllable element is configured to, responsive to the power switch disconnecting the given circuit from the common voltage source and to the given circuit being turned on to wakeup, supply the wakeup charge to the given circuit being turned on by transferring the wakeup charge from the capacitor tank to the given circuit. This reduces the electrical charge transferred from the circuits connected to the common voltage source.

Abstract: Method and scheduler in an operating system, for scheduling processing resources on a multi-core chip. The multi-core chip comprises a plurality of processor cores. The operating system is configured to schedule processing resources to an application to be executed on the multi-core chip. The method comprises allocating a plurality of processor cores to the application. Also, the method comprises switching off another processor core allocated to the application, not executing the sequential portion of the application, when a sequential portion of the application is executing on only one processor core. In addition, the method comprises increasing the frequency of the one processor core executing the application to the second frequency, such that the processing speed is increased more than predicted by Amdahl's law.

Abstract: An image forming apparatus includes: an image forming unit; a power supply controller controls the image forming apparatus to operate in a normal mode and a power saving mode, in which supply of power to the image forming unit is cut off; and a plurality of interfaces that receives a transition command for transitioning from the power saving mode to the normal mode. The power supply controller performs an interface-power supply process of supplying power to at least one interface; a first change process of changing power supply destinations in the interface-power supply process so as to reduce an amount of power supply in the interface-power supply process; and a second change process of changing the power supply destinations in the interface-power supply process after the first change process so as to further reduce the amount of power supply.

Abstract: A technique to change a thermal design power (TDP) value. In one embodiment, one or more environmental or user-driven changes may cause a processor's TDP value to be changed. Furthermore, in some embodiments a change in TDP may alter a turbo mode target frequency.

Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and each way is powered independently of the other ways. A target active way count is maintained and the system cache attempts to keep the number of currently active ways equal to the target active way count. The bandwidth and allocation intention of the system cache is monitored. Based on these characteristics, the system cache adjusts the target active way count up or down, which then causes the number of currently active ways to rise or fall in response to the adjustment to the target active way count.

Abstract: In one embodiment, the present invention includes a method for receiving an incoming packet in a packet buffer and associating it with a flow identifier. Based on the flow identifier, a core to which the incoming packet is to be directed may be determined, and a power management hint can be transmitted to cause the core to be powered up. Other embodiments are described and claimed.

Abstract: Aspects of a method and system for physical layer control of low latency state transitions for energy efficiency. In this regard, a determination may be made to reconfigure a network device from an energy saving mode of operation to a higher performance mode of operation. A first portion of the network device may be reconfigured prior to sending an indication of the reconfiguration to a link partner, and a remaining portion of the network device may be reconfigured after sending the indication. The link partner may begin reconfiguration from an energy saving mode of operation to higher performance mode of operation upon receiving the indication. The energy saving mode may comprise a low power idle (LPI) or a subset PHY mode. The reconfiguration may comprise allocating memory to, and/or de-allocating memory from, buffering received and/or to-be-transmitted data.

Abstract: The invention relates to a method for operating an electronic system, wherein the energy consumption of at least parts of the system is regulated such that on the basis of at least a time-related curve of the current (IFE1, . . . , IFEn) detected within the system, a gradient value (diFE1, . . . , diFEn) of the current value generated at least partially from circuitry is formed. On the basis of the gradient value, a circuit-related manipulation of at least one physical variable of the system is carried out. The invention further relates to an arrangement for carrying out the method.

Abstract: Apparatuses, systems, and methods are disclosed for managing lifetime for a data storage device. A target module determines a write bandwidth target for a data storage device. An audit module monitors write bandwidth of the data storage device relative to the write bandwidth target. A throttle module adjusts execution of one or more write operations on the data storage device in response to the write bandwidth of the data storage device failing to satisfy the write bandwidth target.

Abstract: A first battery 102 is removably housed in a first battery housing unit 108, and a second battery 103 is removably housed in a second battery housing unit 110. When it is detected that a lid 107 or 109 that is used when the first battery 102 or the second battery 103 is replaced is in an open state, system control sections 113 and 114 start a restriction mode for restricting an operation of an information processing device 100 such that power consumption by the information processing device 100 is curtailed.

Abstract: Methods and apparatus relating to link power savings with state retention are described. In one embodiment, one or more components of two agents coupled via a serial link are turned off during idle periods while retaining link state in each agent. Other embodiments are also disclosed.

Abstract: A printing apparatus having a printing engine, a first control unit, and a second control unit, in which a normal operation is performed by at least the printing engine and the first control unit, a first power saving operation is performed by at least the first control unit while the printing engine is stopped, and a second power saving operation is performed by only the second control unit, the printing apparatus including: a first storage unit of the first control unit that stores a setting value reflecting a setting change performed while the printing apparatus is operated and an operation value not reflecting the setting change performed while the printing apparatus is operated; a second storage unit of the second control unit that stores the setting value and the operation value.

Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple small sections, and each section is supplied with power from a separately controllable power supply. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. Incoming requests are grouped together based on which section of the system cache they target. When enough requests that target a given section have accumulated, the voltage supplied to the given section is increased to a voltage sufficient for access. Then, once the given section has enough time to ramp-up and stabilize at the higher voltage, the waiting requests may access the given section in a burst of operations.

Abstract: A multi-core processor system, a dynamic power management method thereof and a control apparatus thereof are provided. In the method, a workload of a multi-core processor during a runtime stage is obtained. Next, a hot-plug operation is respectively performed on a plurality of slave cores according to the workload and a working state of each slave core. Then, a bus master status and the working state of a boot core are monitored to determine whether to power off the boot core, in which the bus master status is generated by combining a plurality of device statuses reflected by a plurality of peripheral devices. Finally, when the bus master status is determined as idle, the boot core is powered off.

Abstract: An electronic device, a control method of the electronic device, and an image forming apparatus to cut off unnecessary power after recognizing connection/disconnection statuses of Universal Serial Bus (USB) hosts/devices connected to a USB hub are provided. The electronic device includes a USB hub connected to a USB host/device, a first switch configured to switch power supply to the USB hub for reducing power consumption, a controller configured to turn the first switch off to cut off power supply to the USB hub when no USB host/device is connected to the USB hub or only a USB host/device not requiring constant power supply is connected to the USB hub.

Abstract: An information processing system includes a receiving unit that receives user operation; a setting unit that holds association information in which pieces of necessity information each indicating necessity of a shutdown process indicating a process required for stopping power supply to a corresponding device are associated with a plurality of devices, respectively; a first instruction unit that instructs a target device for which the power supply is to be stopped to perform the shutdown process when the receiving unit receives operation to stop the power supply and the target device requires the shutdown process based on the association information; and a second instruction unit that instructs a power supply control device that controls execution or stop of the power supply to the target device to stop the power supply to the target device when the shutdown process of the target device is completed.

Abstract: Computing devices and methods for resetting an inactivity timer of each of a first and second computing device are described. In one embodiment, the method comprises establishing a communication channel between the first computing device and the second computing device, receiving activity input responsive to a user interaction at the first computing device, resetting the inactivity timer of the first computing device, and transmitting a notification via the communication channel to the second computing device that the activity input was received at the first computing device, the inactivity timer of the second computing device being reset in response to receipt of the notification.

Abstract: Dynamically reconfigurable multi-core microprocessors and associated methods are provided. A multi-core microprocessor is provided that supports the ability of system software to disable, or kill, selected cores in such a way that they do not cause drag on the processor bus shared with the other cores. Another multi-core microprocessor is provided that supports reconfiguration of an inter-core coordination system of the microprocessor, wherein cores may be selectively designated as masters for purposes of driving signals onto an inter-core communication wire.

Abstract: A novel information processing apparatus maintains file system information in a secondary storage device during power saving mode. The information processing apparatus keeps storing file information and mounting information in the secondary storage device without releasing it in shutdown process 303 when it transitions to power saving mode, and uses the saved file information 401 and mounting information 402 in reinitializing process 304 when it returns from power saving mode. User program 201 does not need to execute file initializing process. Also, since mounting information 402 is kept, the information processing apparatus can access the file system in the secondary storage device immediately if the power of the secondary storage device is on and the secondary storage device is available.

Abstract: A processor may determine the actual residency time of a non-core domain residing in a power saving state and based on the actual residency time the processor may determine an optimal power saving state (P-state) for the processor. In response to the non-core domain entering a power saving state, an interrupt generator (IG) may generate a first interrupt and the device drivers or an operating system may use the first interrupt to start a timer (first value). In response to the non-core domain exiting the power saving state, the IG may generate a second interrupt and the device drivers or an operating system may use the second interrupt to stop the timer (final value). The power management unit may use the final and the first value to determine the actual residency time.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, a power delivery logic coupled to the plurality of cores, and a power controller including a first logic to cause a first core to enter into a first low power state of an operating system power management scheme independently of the OS, during execution of at least one thread on the first core. Other embodiments are described and claimed.

Abstract: A method for saving a battery power of a terminal includes receiving a touch input on a touch screen, detecting an input stop event where the touch input is stopped, switching the touch screen to a turned-off state or a dim state, in response to the input stop event, and detecting an input resume event where the touch input is resumed during the turned-off state or the dim state, and switching the touch screen to be a turned-on state in response to the input resume event. Other embodiments including an apparatus for saving a battery power are also disclosed.

Abstract: An image forming apparatus includes: an image forming unit; a power supply controller controls the image forming apparatus to operate in a power saving mode, in which supply of power to the image forming unit is cut off, and a normal mode; and a plurality of interfaces that receives a transition command for transitioning from the power saving mode to the normal mode. The power supply controller is configured to perform: an interface-power supply process of supplying power to at least one interface; a determining process of determining whether availability is high or low for an operating interface receiving power supply in the interface-power supply process; and a changing process of changing a power supply target from the operating interface to an idle interface when the availability of the operating interface is determined to be low.

Abstract: A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.

Abstract: Various features are provided to improve communication performance and power conservation in a client terminal by relying on the assistance of a proxy device. For instance, rather than reporting channel measurements via a primary communication channel to a network, the client terminal may be adapted to perform (a) channel measurement feedback using out-of-band signaling via the proxy device and/or (b) active synchronization with assistance of a proxy device. In this manner, the client terminal may be able to disable or reduce power consumption over a primary communication interface for the primary communication channel while utilizing a secondary communication interface to communicate with the proxy device.

Abstract: Provided are systems and methods for execution by a core of a peripheral component to provide power management for a data bus in a electronic device, such as a mobile electronic device. One method comprises determining whether a device in the peripheral component is inactive, transmitting a request for deactivation of at least one data channel to the device, receiving a command to deactivate the at least one data channel, determining whether any remaining devices in the peripheral component are active, and placing the peripheral component in a first low power mode wherein the core remains active in order to monitor a data bus clock.

Abstract: An information processing apparatus includes a receiver configured to receive a packet via a communication line, an operating processor configured to suspend an operation thereof when the information processing apparatus is in an energy saving mode, a first storage configured to store the packet received by the receiver, a determining unit including a table in which different operations of the operating processor are recorded in association with different patterns of packets and configured to determine whether to restart the operating processor when the information processing apparatus is in the energy saving mode based on a pattern of the packet stored in the first storage and the patterns of the packets in association with the operations of the operating processor recorded in the table, and a power manager configured to supply power to the operating processor based on a result determined by the determining unit to restart the operating processor.

Abstract: A method for saving power in transmission of data across buses. By knowing the power characteristics of a bus and characteristics of data to be transmitted across the bus, the data can be encoded in such a fashion as to conserve system power over transmitting the same data in an unencoded format across the bus. The encoding method may be selected before transmission of the data across the bus, and may change depending on the data to be transmitted across the bus.

Abstract: An incoming call answering and rejecting method, an electronic device, and a digital data storage media are provided. The method is applied to an electronic device having a touch screen and has the following steps. A request of an incoming call is received. A dragging signal is generated on the touch screen. When the dragging signal is an answering signal, the incoming call is answered. When the dragging signal is a rejecting signal, the incoming call is rejected.

Abstract: A system and method for operating an electronic device having a High-Definition Multimedia Interface port that is shared between an HDMI source function and an HDMI sink function of the electronic device utilizes detecting whether an external HDMI device that is attached to the HDMI port is one of an HDMI source and an HDMI sink. If the external HDMI device is detected as being an HDMI source, the HDMI sink function of the electronic device is enabled. If the external HDMI device is detected as being an HDMI sink, the HDMI source function of the electronic device is enabled.

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

Abstract: A technique for performing power management for configurable processor resources of a processor determining whether to increase, decrease, or maintain resource units for each of the configurable processor resources based on utilization of each of the configurable processor resources. A total weighted power number for the processor is substantially maintained while resource units for each of the configurable processor resources whose utilization is above a first level is increased and resource units for each of the configurable processor resources whose utilization is below a second level is decreased. The total weighted power number corresponds to a sum of weighted power numbers for the configurable processor resources.

Abstract: A method of power management for devices in a data storage fabric is disclosed. The data storage fabric includes a PHY having a first power condition and a second power condition coupled to a power condition independent device on the data storage fabric. The power condition independent device detects a change in the power configuration of the PHY from the first power condition to the second power condition. The power condition independent device then changes its power state to a comparable power state preselected to correspond with the second power condition.

Abstract: In an embodiment, a power management unit (PMU) may automatically transition (in hardware) the performance states of one or more performance domains in a system. The target performance states to which the performance domains are to transition may be programmable in the PMU by software, and software may signal the PMU that a processor in the system is to enter the sleep state. The PMU may control the transition of the performance domains to the target performance states, and may cause the processor to enter the sleep state. In an embodiment, the PMU may be programmable with a second set of target performance states to which the performance domains are to transition when the processor exits the sleep state. The PMU may control the transition of the performance domains to the second targeted performance states and cause the processor to exit the sleep state.

Abstract: A thermal protection method for a computer system including at least a processor includes monitoring the temperature and loading of the processor via a system firmware in the computer system, obtaining the current performance state level and at least an operable performance state levels of the processor when the system firmware determines that the temperature and loading of the processor exceeds a predetermined value respectively, wherein the performance state level is associated to the frequency of the processor, and setting the processor to one of the operable performance state levels, wherein the frequency of the performance state level is lower than the frequency of the current performance state level, according to the current performance state level and the operable performance state levels.

Abstract: A system and method for power management of storage resources are disclosed. A method may include detecting an occurrence of an event associated with a storage resource disposed in an array of storage resources. The method may further include transitioning the storage resource into a specified power state in response to the detection of the occurrence of the event. A system may include a storage resource and a power management module communicatively coupled to the storage resource. The storage resource may be disposed in an array of storage resources. The power management module may be operable to detect an occurrence of an event associated with the storage resource, and may be operable to transition the storage resource into a specified power state in response to the detection of the occurrence of the event.

Abstract: Energy saving circuit of a computer is connected between a power supply and a motherboard. The energy saving circuit includes six electronic switches and a switch. When the computer is in the stand-by state, and the switch is pressed, the motherboard of the computer receives a standby voltage and the motherboard maintains the stand-by state. The energy-saving circuit can shut off the standby voltage by pressing the switch when the computer is powered off to save energy.

Abstract: In a case where a first condition is met while a communication device may in a high consumption state, the communication device may transit to a first low consumption state. In a case where a second condition is met while the communication device is in a specific state which is one state of the high consumption state and the first low consumption state, the communication device may transit to a second low consumption state. The communication device may be configured to execute a packet process in a case where a receiving process for receiving a packet is executed after the communication device had transited to the first low consumption state. The communication device may be configured not to execute the packet process in a case where the receiving process for receiving the packet is executed after the communication device had transited to the second low consumption state.

Abstract: A processor includes a communicating unit, a receiving unit, a processing unit, and a power-off controller. The receiving unit receives an operation from a user. The processing unit executes processing according to a processing request received by at least one of the communicating unit and the receiving unit. If a power-off request is received from a terminal by the communicating unit, the power-off controller stops the processing unit and disconnects a power supply when the operation received from the user by the receiving unit is not being processed and a condition determined in accordance with a processing mode of the power-off request is satisfied.

Abstract: A method is described that involves controlling the traffic levels through an uncore to provide thermal management for the uncore. The method including determining if an uncore's temperature in a first uncore state is above a first threshold value and changing the first uncore state to a second uncore state if the uncore temperature is above the first threshold value.

Abstract: An inertial force sensor includes the following elements: a sensor element for converting an inertial force into an electrical signal; a sensor signal processor connected to the sensor element, for outputting an inertial force value; and a power controller for controlling electric power supply to the sensor signal processor, based on the inertial force value. When the inertial force value is maintained for a predetermined time period within a predetermined range in which a reference value is the middle value of the range, the power controller reduces the electric power supply to the sensor signal processor and updates the reference value to the inertial force value obtained after a lapse of the predetermined time period.

Abstract: When there is a memory module mounted in a memory slot, a memory power circuit provides a voltage to the memory slot. First and second power pins of the memory slot are connected. A first electronic switch is turned on. A second electronic switch is turned off. A programmable logic controller (PLC) outputs a first control signal to the memory power circuit to output the voltage to the memory slot. When there is no memory module mounted in the memory slot and the motherboard is powered on, the memory power circuit provides a voltage to the memory slot. The first and second power pins of the memory slot are disconnected. The first electronic switch is turned off. The second electronic switch is turned on. The PLC outputs a second control signal to control the memory power circuit not to output the voltage to the memory slot.

Abstract: Based on bounds of a period of reduced operation for a base device, a base device generates a power management message for transmission to a peripheral device. In the power management message, the base device inserts bounds of a period of reduced operation for the peripheral device. As a result, the periods of reduced operation conserve battery power in both devices and the two devices may reestablish a communications channel upon reaching the end of the period of reduced operation and resuming normal operations.

Abstract: In one embodiment, the present invention includes an apparatus having a core including functional units each to execute instructions of a target instruction set architecture (ISA) and a power controller to control a power mode of a first functional unit responsive to a power identification field of a power instruction of a power region of a code block to be executed on the core. Other embodiments are described and claimed.

Abstract: There is provided a signal processing device which is capable of suppressing the influence of a digital data process on an analog signal process without completely stopping a digital data processing circuit. A signal, processing device includes an analog signal processing circuit, a digital data processing circuit, a determination section configured to determine an influence of the digital data processing circuit on the analog signal processing circuit, and a control section configured to stop a partial circuit of the digital data processing circuit or lower processing capability thereof in response to a determination result of the determination section.

Abstract: Example embodiments disclosed herein relate to a computing system including a controller hub to control system sleep states, and an embedded controller including an internal timer. The embedded controller is to remove power from the controller hub when the system enters a sleep state and to enable power to the controller hub prior to the system wake time. The internal timer is to determine when to enable power to the controller hub. Example methods and machine-readable storage media are also disclosed.

Abstract: A deactivated passive user interaction sensor may be activated or deactivated on demand based on an expected use of the sensor. The expected use may be ascertained by detecting a predetermined user interaction at another sensor that is already active. Once the predetermined user interaction is detected, the active sensor may be deactivated and the sensor that is expected to be used may be activated. Total sensor power consumption may be reduced by providing a predetermined sensor activation and deactivation sequence for at least three sensors in a computing system based on predetermined user interactions with an active sensor. Methods, apparatuses, systems, and computer readable media are provided.

Abstract: A High Speed Inter Chip (HSIC) system and method for minimizing power consumption by controlling the state of the HSIC module through a control line are provided. The method between a host and a slave includes transitioning, when no communication request exists for a first reference time in an active state where all functions of the HSIC modules are enabled, to a suspend state where least functions used for maintaining a communication link of the HSIC modules and transitioning, when no communication request exists for a second reference time in the suspend state, to a power-off state where the HSIC modules turn off The HSIC communication method and apparatus are advantageous to minimize the electric current consumption of the HSIC consumption system.