Abstract: Methods and apparatus for managing power consumption in a multi-function electronic device powered by one or more batteries are provided. In one embodiment, when the power available from the one or more batteries is diminished (e.g., below a certain threshold), management of power consumption in a battery-powered electronic device (e.g., a portable electronic device) can operate or be operated to preserve one or more functions supported by the electronic device. For example, the one or more functions can be preserved by: (i) alerting a user that they should act to avoid usage of other functions that are not being preserved, and/or (ii) disabling (e.g., automatically) one or more of the other functions that are not being preserved.

Abstract: The storage control device of the present invention reduces the power consumption amount by stopping the transmission of power to enclosures that are not accessed. A plurality of additional enclosures are switch-connected via backend switches to a base enclosure. Drives that have not been accessed for a predetermined time or more undergo spin-down. When all of the drives in the enclosure enter a spin-down state, the supply of power from the power supply in the enclosure to the respective drives is stopped. The base enclosure that manages the system constitution of the storage control device turns OFF the switch connected to the enclosure when all of the drives in a certain enclosure have spun down. The transmission of power to this enclosure is accordingly stopped.

Abstract: An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.

Abstract: A method for automatically initializing the operational settings of a system from information stored within a non-volatile storage of an integrated circuit so that the operational requirements of the integrated circuit, which may be a microprocessor, are met by the system when the system is operating. During manufacturing test, environmental requirements of the integrated circuit are determined and stored within the non-volatile storage of the integrated circuit. During system initialization, environmental control values such as required operating voltage and frequency and cooling requirements are determined from the test values, which are read from the integrated circuit. The values are read by an interface of the system from an interface of the integrated circuit. System settings are controlled by the values to provide the required operating environment and the values may be captured within the system for subsequent operations and initialization sequences.

Abstract: A matching system of an electronic device and a perpheral device and a matching method thereof are described. The system includes and electric device, having an identification mechanism for identifying a specific identification code and generating a control signal or a control instruction according to an identification result; and a peripheral device, electrically coupled to the electronic device selectively. The peripheral device includes an identification code unit for storing a group identification code; and a power control unit, for controlling an operation state of the peripheral device according to the control signal or the control instruction, when the peripheral device is electrically coupled to the electronic device. If the identification result is that the specific identification code is consistent with the group identification code, the power control unit controls the entire peripheral device to work normally according to the control signal or the control instruction.

Abstract: The power supply device of the present invention supplies power individually to a plurality of disk drives by rendering a plurality of DC/DC converters redundant. One redundant power supply substrate is assigned to a plurality of normal power supply substrates. One redundant power supply substrate supports the outputs of a plurality of normal power supply substrates. The main DC/DC converters in the normal power supply substrate correspond with the subgroups on a one-for-one basis. The secondary DC/DC converters in the redundant power supply substrate each correspond with all of the respective subgroups and are able to supply power to a predetermined single disk drive among the respective disk drives in the subgroups for each of the subgroups.

Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: Administering power supplies in a data center including, upon connection of a first power supply through a power line to a circuit breaker in the data center, querying, by a power supply communications device of the first power supply through the power line, a circuit breaker communications device of the circuit breaker for a circuit breaker identification; querying, by the power supply communications device of the first power supply, for a maximum current threshold for the circuit breaker; sending the circuit breaker identification and the maximum current threshold for the circuit breaker to a management module; and determining, by the management module in dependence upon the circuit breaker identification and the maximum current threshold for the circuit breaker, whether to power on a computing device powered by the first power supply including determining whether the circuit breaker is shared by another power supply.

Abstract: Methods and systems for powering-off a Bluetooth device from a linked device are provided. A device can transmit a Bluetooth signal to a linked device to instruct the linked device to power-off. In this manner, the user need only turn off one device manually which results in all linked devices being powered off. This process can be initiated by a user through a device directly linked with the device to be powered-off or through a device that is indirectly connected, through one or more Bluetooth networks, with the device to be powered-off. This process can also be automatically initiated by a device when a set of predetermined conditions exist. Once instructed to do so, a device can initiate a predetermined power-off process which can involve terminating any ongoing functions and turning off various subsystems. In accordance with the present invention, a user can initiate a power-off of all the devices on a Bluetooth network through a single device.

Abstract: An encryption processing apparatus and method in which the difficulty of encryption analysis based on power analysis can be increased considerably are provided. By dividing an original encryption processing sequence into a plurality of groups and by mixing the processing sequence by setting dummies as necessary, several hundreds to several thousands of types of different mixed encryption processing sequences can be set, and a sequence selected from a large number of these settable sequences is performed. According to this configuration, consumption power variations which are completely different from consumption power variations caused by a regular process possessed by the original encryption processing sequence can be generated, and thus the difficulty of encryption analysis based on power analysis can be increased considerably.

Abstract: A demand based power re-allocation system includes one or more subsystems to assign a power allocation level to a plurality of servers, wherein the power allocation level is assigned by priority of the server. The system may throttle power for one or more of the plurality of servers approaching the power allocation level, wherein throttling includes limiting performance of a processor, and track server power throttling for the plurality of servers. The method compares power throttling for a first server with power throttling for remaining servers in the plurality of servers and adjusts throttling of the plurality of servers, wherein throttled servers receive excess power from unthrottled servers.

Abstract: A handheld communication device to communicate with a remote universal serial bus (USB) host controller via an integrated power and data port is provided. The device includes a microprocessor communicating with a power management integrated circuit (IC), wherein said microprocessor requires greater than 100 mA to be enumerated with the USB host controller. The device includes a USB microcontroller communicating with the USB host controller via a multiplexer and integrated power and data port, wherein the USB microcontroller requires less than 100 mA to be enumerated with the USB host controller, and wherein if a current available from the rechargeable battery is below a specified threshold required to power up the microprocessor, then the USB microcontroller performs USB enumeration with the USB host controller.

Abstract: Power control circuitry for controlling connection of a voltage source to a switched power rail powering an associated circuit is provided. A plurality of switch blocks are connected in parallel between the switched power rail and the voltage source, each switch block being controlled by an enable signal provided by a switch controller. The switch controller performs a turn-on sequence providing a series of enable signal patterns to the switch blocks. The switch controller applies a time varying generation operation to at least one sequence stage of a predetermined turn-on sequence to produce a corresponding enable signal pattern for that sequence stage. When the turn-on sequence is later repeated, the enable signal pattern produced for at least one of the sequence stages differs from the enable signal pattern previously produced for that sequence stage.

Abstract: A device comprising a temperature measurement module, a performance state module, a memory bandwidth module, and a fan speed module. The temperature measurement module is configured to determine a rate of temperature change in a server and to output a control signal when the rate of temperature change is above a threshold rate. The performance state module is configured to reduce a performance state of the device to a lowest system level in response to the control signal, and to reduce a processor power consumption and a subsystem power consumption to a minimum power level in response to reducing the performance state to the lowest system level. The memory bandwidth module is configured to reduce a memory bandwidth to a minimum bandwidth level based on the control signal. The fan speed module is configured to reduce a fan speed to a minimum level based on the control signal.

Abstract: A noise reduction method by implementing certain point-to-point delay is disclosed. In this regard a method is introduced comprising determining a frequency of a greatest noise on a high-speed data link when turning on a power delivery network, determining a delay time between a first port and a second port that minimizes the greatest noise, and turning on the second port after the delay time from turning on the first port. Other embodiments are also disclosed and claimed.

Abstract: Dynamic voltage and frequency scaling (DVFS) is an effective way to reduce energy and power consumption in microprocessor units. Current implementations of DVFS suffer from inaccurate modeling of power requirements and usage, and from inaccurate characterization of the relationships between the applicable variables. A system and method is proposed that adjusts CPU frequency and voltage based on run-time calculations of the workload processing time, as well as a calculation of performance sensitivity with respect to CPU frequency. The system and method are processor independent, and can be applied to either an entire system as a unit, or individually to each process running on a system.

Abstract: A system for activating and deactivating a hardware device including a first stage electronic deactivation unit operative, responsive to a deactivation request, to perform a first deactivation operation including deactivation of a first portion of the hardware device having low wake-up latency at a first time, a second stage electronic deactivation unit including a breaking distance timer activated subsequently to the deactivation request and operative to deactivate a second portion of the hardware device having high wake-up latency at a subsequent second time separated from the first time, and a power management system including a power source and a power supply regulator operative to control the supply of power in accordance with a selectable one of a plurality of regulator settings, selected using a hardware setting selector. Responsive to a wakeup event, the first portion of the hardware device is reactivated and the breaking distance timer is deactivated.

Abstract: A method for monitoring the supply voltage of an electronic device includes the steps of: determining an operating condition of the electronic device, adjusting a plurality of reference voltages dependent on the operating condition of the electronic device, wherein each of the plurality of reference voltages is adjusted at a different time, and comparing the supply voltage of the electronic device with at least one of the plurality of reference voltages.

Abstract: An information processing apparatus is disclosed as an example. The information processing apparatus sends data to an image forming apparatus and causes the image forming apparatus to generate an image. The information processing apparatus includes a receiving unit configured to receive information that is sent from an image forming apparatus and indicates whether the image forming apparatus has a power saving function, a determination unit configured to determine, on the basis of the information received by the receiving unit, whether the image forming apparatus has the power saving function, and a setting unit configured to perform setting on a communication program in the information processing apparatus so as to reduce a number of times a power saving mode of the image forming apparatus having the power saving function is released due to communication between the information processing apparatus and the image forming apparatus.

Abstract: A system and method for operating system power management in a computing device for power over Ethernet (PoE). Computing devices such as portable computers or embedded devices having an operating system (OS) can leverage power management features in an OS. Power management state information such as user parameters, computing device parameters, application parameters, IT parameters, network parameters, etc. can be used to generate power requests that are acted upon by power sourcing equipment.

Abstract: A system and method for enabling power over Ethernet (PoE) for legacy devices. Legacy devices often represent a large installed base of devices. This installed base of devices (e.g., mobile computing devices) may have little or no PoE functionality. It is a feature of the present invention that an external device (e.g., dongle) can be used to retrofit such an installed base of devices for use with state of the art PoE functionality.

Abstract: Reducing current draw of solid state drives from a shared power supply of a computer at computer startup, each SSD including computer memory, a capacitor, a disk controller, and a charge controller, the disk controller configured to enable the charge controller to charge the capacitor upon receiving a charge command, the SSDs organized into startup groups characterized by a position in a predefined startup order. Upon startup of the computer, beginning with a first startup group in the predefined startup order and until the last startup group in the predefined startup order has received a charge command, embodiments include, sending, by a storage device initiator, a charge command to a startup group to initiate charging of the capacitor of each solid state drive in the startup group and waiting a predefined period of time before sending another charge command to a next startup group in the predefined startup order.

Abstract: An image forming apparatus includes an operating unit, a controller, and a transmission line that connects the operating unit to the controller. The operating unit includes a USB device that transmits data to the controller and receives data from the controller via the transmission line, and the controller includes a USB host that transmits data to the operating unit and receives data from the operating unit via the transmission line.

Abstract: Provided is a method used in a computer system which includes at least one host computer, the method including managing a job to be executed by the host computer and a power supply of the host computer, the method including the procedures of: receiving the job; storing the received job; scheduling an execution plan for the stored job; determining, based on the execution plan of the job, a timing to execute power control of the host computer; determining a host computer to execute the power control when the determined timing to execute the power control is reached; controlling the power supply of the determined host computer; and executing the scheduled job.

Abstract: A method and system of adaptive power control based on post package characterization of integrated circuits. Characteristics of a specific integrated circuit are used to adaptively control power of the integrated circuit.

Abstract: An integrated circuit includes a first clock island, a second clock island, a clock generator, and a first programmable delay element. The first clock island is configured to receive a first clock signal. The second clock island is configured to receive a second clock signal. The clock generator is configured to provide a generated clock signal and the first and second clock signals are based on the generated clock signal. The first programmable delay element is coupled between the clock generator and the first clock island. The first programmable delay element is configured to receive the generated clock signal and provide the first clock signal. The integrated circuit is configured to account for a clock skew between the first and second clock signals when information is transferred between the first and second clock islands.

Abstract: A storage device for storing data includes: an interface controller connectable to a host via a interface, the interface controller having an active state capable of transmitting data to the host and an inactive state having a lower power consumption than the active state; a medium for storing data; a head for read out data stored in the medium; and a processor for executing a process including receiving a command for reading out data stored in the medium from the host, determining timing when the data read out from the medium reaches the interface controller, and starting transition of the interface controller from the inactive state into the active state before the determined timing.

Abstract: Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.

Abstract: The present invention relates to an apparatus and method for controlling power to a Universal Serial Bus (USB) device. The present invention provides an apparatus for controlling power to a USB device, the USB device being used to connect a Personal Computer (PC) with a peripheral device, the power control apparatus including a plug-in port for connecting the peripheral device with the PC, a state detector for detecting whether the peripheral device is in a preparation completion state, a power supply unit for supplying power to the USB device, and a power control unit for controlling the power supply unit so that power is supplied to the USB device if it is determined that the peripheral device is in a plugged-in state, and if it is determined that the peripheral device is in a preparation completion state by the state detector.

Abstract: A method and system of adaptive power control. Characteristics of a specific integrated circuit are used to adaptively control power of the integrated circuit.

Abstract: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits are connected to a voltage regulation circuit that provides the integrated circuit voltage source. These measurement circuits provide signals to control the voltage regulation circuit to adjust the voltage output to the integrated circuit based upon a measurement values obtained on the semiconductor device. These measurements include temperature and IR drop at locations on the semiconductor substrate, along with the frequency response of integrated circuit.

Abstract: A programmable system-on-a-chip integrated circuit device comprises a programmable logic block, a non-volatile memory block, an analog sub-system, an analog input/output circuit block, and a digital input/output circuit block. A programmable interconnect architecture includes programmable elements and interconnect conductors. Ones of the programmable elements are coupled to the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, the digital input/output circuit block, and to the interconnect conductors, such that inputs and outputs of the programmable logic block, the non-volatile memory block, the analog sub-system, the analog input/output circuit block, and the digital input/output circuit block can be programmably coupled to one another.

Abstract: A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

Abstract: A core cluster includes a cache memory, a core, and a cluster cache controller. The cache memory stores and provides instructions and data. The core accesses the cache memory or a cache memory provided in an adjacent core cluster, and performs an operation. The cluster cache controller allows the core to access the cache memory when the core requests memory access. The cluster cache controller allows the core to access the cache memory provided in the adjacent core cluster when the core requests a clustering to the adjacent core cluster. The cluster cache controller allows a core provided in the adjacent core cluster to access the cache memory when the core receives a clustering request from the adjacent core cluster.

Abstract: A power management system comprises a power management module configured to determine a power draw limit for operating an electronic device by a power source, the power management module configured to control use of power-consuming elements of the electronic device based on a prioritization of the power-consuming elements to limit a power draw by the electronic device from the power source to the power draw limit.

Abstract: A processing system includes a processor (20) having an idle mode node for generating an idle mode signal indicating whether the processor is in an idle mode and a memory (22) having a data retention node for receiving a data retention mode signal. The memory includes circuitry for placing the memory in a low power state responsive to the data retention mode signal. The idle mode signal drives the data retention node, such that the memory is placed in the low power state when the processor is in idle mode.

Abstract: Techniques for managing lower power states for data links are described. An apparatus may comprise a memory unit to store a device connection manager for a controller of a bi-directional serial link connected to a device. The apparatus may comprise a processor operative to execute the device connection manager, the device connection manager operative to read a register of the controller storing information indicating an interface of the controller for the bi-directional serial link is operating in a lower power management state, send a control directive on a periodic basis for the interface to transition to a temporary active state, and receive an interrupt from the interface indicating the device is disconnected from the bi-directional serial link during a temporary active state. Other embodiments are described and claimed.

Abstract: A method and system for estimating processor utilization from power measurements provides an estimate of processor utilization that can be computed outside of the processor and operating system. Measurements of the processor power consumption are gathered over short intervals in a histogram. The idle power consumption of the processor is determined, and a threshold value higher than the idle power consumption level is computed from the idle power consumption. The number of histogram counts for bins greater than the threshold is normalized to the total number of measurements, providing a fractional value that corresponds to the processor utilization over the measurement interval. The fractional value can then be used in a power management algorithm that adjusts the frequency and optionally the voltage of the processor or group of processors based on their utilization.

Abstract: An apparatus and method provide power to perform functions on a computing device. In one example, the apparatus contains multiple processors that may operate at different power levels to consume different amounts of power. Also, any of the multiple processors may perform different functions. For example, one processor may be a low power processor that may control or operate at least one peripheral device to perform a low capacity function. Control may also switch from the low power processor to a high capacity processor. In one example, the high capacity processor controls the low power processor and further controls the at least one peripheral device through the lower power processor.

Abstract: One embodiment disclosed relates to a system for power distribution to network devices. The system includes a plurality of network switches each having an internal power supply and a plurality of ports for connecting to the network devices and an external power supply having a plurality of output ports for connecting to the network switches. The external power supply communicates power available to the network switches. Each network switch determines amounts and priority levels of power for the network devices connected thereto, sums together the amounts at each priority level, determines additional amounts and priority levels of power required beyond the internal power supply capability, and sends a power request to the external power supply. The external power supply allocates power to the network switches depending on the power requests received.

Abstract: A system and method is disclosed for providing a plurality of hardware performance monitors for adaptive voltage scaling in an integrated circuit system that comprises a plurality of clock domains. Each hardware performance monitor is associated with one of the plurality of clock domains and provides a signal that measures a performance of its respective clock domain temperature, process corner and supply voltage. The difference between the measured performance and a nominal expected performance for each hardware performance monitor is determined. The largest of the plurality of difference signals is selected and used in an advanced power controller to provide adaptive voltage scaling for the integrated circuit system.

Abstract: A method of optimizing performance of a multi-core chip having a plurality of cores includes the steps of determining a Vdd-frequency SCHMOO characteristic for each of the plurality of cores individually; saving data indicative of the Vdd-frequency SCHMOO characteristics for each of the plurality of cores; configuring the cores to obtain a configuration providing at least one of optimum power consumption and optimum performance, for a given workload, based on the saved data; and saving the configuration such that it may be updated and used on at least one of a periodic and a continual basis.

Abstract: A power control apparatus for automatically turning on and off a motherboard, the power control apparatus includes a power supply supplying electric power to the motherboard periodically, a control circuit including a first switch element, a second switch element, a first capacitor, a second capacitor, a first resistor, and a second resistor. When the power supply is powered up, the second capacitor is charged, the second switch element is turned on, a second terminal of the second switch element outputs a low level signal to power up the motherboard. When the motherboard is powered up, the first capacitor is charged, the first switch element is turned on, the second switch element is turned off, the second terminal of the second switch element outputs a high level signal. The motherboard is powered off when the power supply is powered off.

Abstract: Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.

Abstract: An apparatus, system, and method are disclosed for event, time, and failure state recording in a power supply. Disclosed is a power supply that receives AC voltage as an input and provides regulated DC voltage as an output; a microcontroller integrated into the power supply that regulates output voltage and monitors, records, and reports operating conditions of the power supply; and a non-volatile solid-state storage that can be repeatedly read from, written to, and erased by the microcontroller and integrated within the microcontroller such that only a single address is needed to access both the microcontroller and the solid-state storage, the solid-state storage configured to store operating data received from the microcontroller, the operating data including the recorded operating conditions of the power supply.

Abstract: Method and apparatus for servicing commands such as the type issued by a host device to load an operating system from an associated data storage device. A controller is adapted to, upon receipt of a selected command sequence comprising a first command followed by a second command, determine an elapsed time interval between the first and second commands. The controller further uses the elapsed time interval to subsequently service the first and second commands during a subsequent receipt of the selected command sequence. Preferably, a command history table is generated to list the commands in the command sequence and the associated time intervals, and to use the time intervals to predict when the next command will occur. Readback data are pre-fetched to a buffer to expedite servicing of the commands, and the controller selectively enters one or more reduced power modes between successive commands to reduce power consumption levels.

Abstract: A computing device operates over a range of voltages and frequencies and over a range of processor usage levels. The computing device includes at least a variable frequency generator, a variable voltage power supply and voltage supply level and clocking frequency management circuitry. The variable frequency generator is coupled to the processor and delivers a clock signal to the processor. The variable voltage power supply is coupled to the processor and delivers voltage to the processor. The voltage supply level and clocking frequency management circuitry adjust both the voltage provided by the variable voltage power supply and the frequency of the signal provided by the variable frequency generator. The computing device includes a temperature sensor that provides signals indicative of the temperature of the processor and the voltage supply level and clocking frequency management circuitry adjusts the voltage and/or the clocking frequency provided by the variable voltage power supply.

Abstract: A method to manage power in a computing device comprising a controller assembly and a storage assembly comprising a plurality of data storage devices, by selecting a processor parameter, establishing a threshold processor parameter value, establishing a threshold over-parameter time interval, selecting a data storage device parameter, and establishing a nominal data storage device parameter value. The method determines an actual processor parameter value. If the actual processor parameter value is less than or equal to the threshold processor parameter value, the method operates each of the plurality of data storage devices using the nominal data storage device parameter value. If the actual processor parameter value is greater than the threshold processor parameter value, then the method determines an actual over-parameter time interval.

Abstract: A power supply unit includes a communication unit and a control unit. The communication unit is capable of performing communication with a first processing unit group constituted of a plurality of processing units connected thereto. The control unit controls powers to the plurality of processing units through the communication so that the powers are turned on in an order corresponding to an order of connection and assigns, to the plurality of processing units, respectively, IDs of numbers corresponding to the order of turning-on of the powers each time the power is turned on.

Abstract: Dynamically managing power consumption in a computer system having at least two parallel power converters in order to improve efficiency. A maximum power capacity for each of the power converters is determined and then power consumption of the computer system is monitored. If the power consumption of the computer system can be provided by less than all of the parallel power converters then one or more of the power converters is turned off, such that a reduced number of parallel power converters remains turned on. A reduced maximum power capacity of the reduced number of parallel power converters is determined and a power cap value is set for the computer system that is less than or equal to the reduced maximum power capacity. The computer system is throttled at the power cap to prevent power consumption of the computer system from exceeding the power cap value.