Abstract: For controlling power sequence in a blade center environment, a relationship component module creates a topology of interdependent relationships of devices in the blade center environment. The devices include server blades, storage blades, and switch modules. A sequence module defines a sequence of the devices in the blade center environment to power off and on based on the topology of interdependent relationships. The sequence includes an order of a first independent blade server, each dependent storage blade of the first independent blade server, and a second independent blade server. A monitor component module monitors a command from an Advanced Management Module (AMM) to regulate power for the devices in the blade center environment. The AMM regulates power within the blade center. A validation module validates that the command does not violate the interdependent relationships and the sequence of devices or else blocks the command if the command is not validated.

Abstract: A wireless electronic-ink display device supported in packaging, and employing a power switching mechanism which operates to prevent leakage, drainage or discharge of the electro-chemical battery until a change in predetermined state of configuration occurs. The wireless electronic-ink based display device comprises (i) a power source module with an electro-chemical battery, (ii) a power management module for managing the power levels within the wireless electronic-ink display device, and (iii) a power switching module, arranged between the power source module and the power management module, and automatically responsive to a change in at least one predefined state of device configuration, to prevent leakage, drainage or discharge of the electro-chemical battery until a change in predetermined state of configuration occurs.

Abstract: A multi-supply power supply circuit has a first power supply regulating circuit that produces a first power supply voltage; and a second power supply regulating circuit that receives the first power supply voltage from the first power supply regulating circuit as an enable input signal and is operative to produce a second and different power supply voltage. In one embodiment, the first power supply voltage may reach a steady state condition prior to the second power supply voltage reaching a steady state condition. In one example, the multi-supply power supply circuit includes a plurality of cascaded low drop out power supply regulating circuits.

Abstract: An image formation apparatus includes a reception section, a function section, an image formation section and a power output device. The reception section is configured to be connected to a communication line over which image information and power are transmitted. The reception section receives the image information and the power transmitted over the communication line. The function section receives supply of the power received by the reception section, to function. The image formation section forms an image on a medium based on the image information received by the reception section or the function section. The power output device receives power supply from a commercial power supply. The power output device outputs power of a predetermined voltage to the image formation section.

Abstract: A time sequence control circuit that can control time sequence of a computer. After the computer is turned on, a power supply terminal outputs a high level enabling signal to an enabling pin of a power supply circuit, the power supply circuit is active. A power supply pin of the power supply circuit outputs a standard voltage to a power pin of each of the motherboard components. A first electronic switch is turned on, a second electronic switch is turned off, and a power supply state pin of the power supply circuit outputs a high level power supply state signal to a power state input pin of a main chip after the power supply circuit outputs the standard voltage.

Abstract: A method for determining power consumption in a data storage system is provided. The method comprises determining data access patterns for at least a first storage device in a storage system based on operations performed by the first storage device; and calculating power consumption for the storage system by interpolating costs associated with the operations performed by the first storage device, wherein the cost associated with each operation is determined based on: (1) various levels of activities for the first storage device and a mix of workload characteristics, and (2) predetermined power consumption measurements obtained from one or more benchmarks for same operations performed by a second storage device in a test environment.

Abstract: A power supply start-up sequencing mechanism for controlling activation of a plurality of power supply circuits with a predetermined timing is disclosed. The mechanism comprises a time value generator arranged to provide a time value signal; and for each of the power supply circuits, a logic circuit arranged to receive the time value signal and from the received signal provide an activation signal to the respective power supply circuit, wherein the respective logic circuit is associated with a start timing value for the respective power supply circuit such that the activation signal is provided when the associated start timing value coincides with the received time value signal. An apparatus comprising such a mechanism, and a method for controlling activation of a plurality of power supply circuits are also disclosed.

Abstract: The described implementations relate to energy-aware server management. One implementation involves an adaptive control unit configured to manage energy usage in a server farm by transitioning individual servers between active and inactive states while maintaining response times for the server farm at a predefined level.

Abstract: In the field of electronic technologies, a power supply selector and a power supply selection method are provided. The power supply selector includes: a first selection module, configured to select a power supply from multiple candidate power supplies; a control module, coupled to the first selection module, and configured to use the power supply selected by the first selection module as a power supply, and compare voltages of the multiple candidate power supplies to generate a control signal of each candidate power supply; and a second selection module, coupled to the control module, and configured to select a power supply for output in the multiple candidate power supplies under the control of the control signal of each candidate power supply. The technical solution is used to select a power supply from multiple candidate power supplies.

Abstract: A power supply system includes a power supply unit, a number of electrical loads and a sequence circuit. The power supply unit provides power for the electrical loads through the sequence circuit. When any one of the electrical loads fails the sequence circuit will record the failure, shut down and lock the power supply unit to prevent the power supply unit from powering the electrical loads.

Abstract: A motherboard includes a motherboard power supply connector and a time delay circuit. The motherboard power supply connector connects a power supply unit. The motherboard power supply connector has a power supply on pin and a power good pin. The power good pin is configured for receiving a power good signal from the power supply unit. The time delay circuit has an input terminal and an output terminal. The input terminal is configured for receiving a power supply on signal. The output terminal is connected to the power supply on pin and is configured for sending the power supply on signal to the power supply on pin after a time delay determined by the time delay circuit.

Abstract: An integrated circuit includes a global power supply node. A first power domain has a first power management circuit, which includes a local power supply node. A first power control circuit is capable of receiving an input signal. A second power control circuit has a higher current capacity than the first power control circuit. The first power control circuit and the second power control circuit are coupled to the local power supply node and the global power supply node. The input signal is configured to initiate a power sequence, e.g., a power up process or a power down process, in the first power control circuit. A first control signal generated by the first power control circuit is configured to initiate a power sequence in the second power control circuit.

Abstract: A computer system has at least one supply device, at least one system component with a data-processing device and at least one communications device. The supply device has at least one programmable control module that is supplied with an operating energy by a voltage source coupled to the at least one supply device and operated independently thereof.

Abstract: A local area network system includes switching circuitry and in-band data ports under control of the switching circuitry. Device management circuitry is configured to manage the local area network device and system power is configured to provide power to the switching circuitry and the device management circuitry. An out-of-band data port is coupled to the device management circuitry. The out-of-band data port is supplied with a Power-over-Ethernet supply.

Abstract: Methods and systems for supplying power to multiple voltage islands using a single supply source are disclosed. Aspects of one method may include providing power to a first of a plurality of voltage islands, and individually controlling providing of power to each of a remaining portion of the plurality of voltage islands. For example, when an electronic system is first powered on, a low current voltage source may be used to supply power to a primary voltage island. As a higher current voltage source becomes available, power derived from the higher current voltage source may be provided to the primary voltage island and to secondary voltage islands. Power to each of the secondary voltage islands may be, for example, individually controlled via a power MOS transistor. The power MOS transistor may also be configured to allow a faster blocking time than unblocking time.

Abstract: A mechanism is provided for using a power proxy unit combined with on-chip actuators to meet a defined power target value identifying a target power consumption of a component of a data processing system. A power manager in the data processing system identifies a proxy power threshold value, for the defined power target value, identifying a maximum power usage for the component, and a power usage estimate value identifying a current power usage estimate for the component. The power manager sends a set of signals to one or more on-chip actuators in the power proxy unit associated with the component in response to the power usage estimate value being greater than the power proxy threshold value. The one or more on-chip actuators adjusts a set of operational parameters associated with the component in order to meet the defined power target value.

Abstract: A central processing unit (CPU) start-up circuit for controlling a CPU of a portable electronic device includes a power management unit (PMU) connected to the CPU, an awaking circuit connected to the CPU, and a main power supply connected to the CPU, the PMU and the awaking circuit. The main power supply provides working electric power to the CPU, the PMU detects the status of the main power supply and generates a status signal (SS) according to the detecting result, the awaking circuit detects the status of the main power supply and generates a waking signal (WS) according to the detecting result, and the SS and the WS are both transmitted to the CPU to cooperatively control the CPU to be switched on and switched off.

Abstract: A semiconductor integrated circuit has an internal circuit to which operation power is supplied or interrupted, and a power supply control circuit for controlling the supply and interruption of operation power to the internal circuit in accordance with an operation mode. The power supply control circuit has a storage circuit and a power supply control sequence circuit. The storage circuit inputs and holds switching instruction data for instructing switching between supply and interruption of the operation power and low-power-consumption-mode data determining an operation mode of the interruption of operation power and cancellation of the interruption.

Abstract: A method for power managing hardware. The method includes determining hardware to power manage, sending a tracing request from a power management control to a tracing framework to obtain usage data of the hardware, and identifying a first probe to obtain first tracing data corresponding to the usage data in a first hardware control software component, where the first hardware control software is configured to interact with the hardware. The method further includes enabling the first probe, obtaining the first tracing data from the first probe, where the first tracing data is obtained when the first probe is encountered during execution of the first hardware control software, and modifying operation of the hardware using the first tracing data.

Abstract: A network equipment for a powered device of a PoE system is adapted to be connected to multiple network lines, each transmitting a network signal, and a DC power that is carried on the network signal, and that has a magnitude smaller than a power necessary for driving power-consuming components of the powered device. The network equipment includes: multiple Ethernet network ports, each coupled to a respective network line; a transformer module coupled to the Ethernet network ports, and configured to separate the DC powers from the network signals; a power module coupled to the transformer module for combining the DC powers into a supplying power; and a signal processing circuit coupled to the power module for receiving at least a portion of the supplying power, and coupled to the transformer module for processing the network signals. The supplying power has a magnitude sufficient for driving the power-consuming components.

Abstract: A technique for determining task allocation for reducing power consumption of an entire system is disclosed. This system includes physical computers, a cooling apparatus for cooling the physical computers, and a power-saving control server for controlling the physical computers and cooling apparatus. The power-saving control server includes a virtual server layout generator which sets up a plurality of sets of task allocations with respect to the physical computers, a server power calculator for calculating power consumption of the physical computers in each task allocation, a physical computer profile used to estimate a heat release amount of the physical computers in each task allocation, a cooling power calculator which computes power consumption of the cooling apparatus, and a virtual server relocator which determines a task allocation with a total of calculated values of the server/cooling power calculators being minimized to be the optimum task allocation for the physical computers.

Abstract: A midspan unit arranged to supply power to a powered device over data communication cabling constituted of a signal conditioner exhibiting a transfer function with a gain of not less than ?0.4 dB as compared with: (K1*(s+R/L1+a)^m)/((s+R/L2+b)^n) over a predetermined frequency range associated with the data transmitted from the powered device. s represents 2*?*(??1)*f, wherein f represents the predetermined frequency range associated with the data terminal equipment to be powered. R represents the signal source impedance in parallel with the load termination impedance. L1 represents the effective inductance of a data transformer winding of the data transmitter of the powered device, the effective inductance determined responsive to power received by the powered device from the power sourcing equipment; and L2 represents the effective inductance of the data transformer winding of the data transmitter of the powered device expected by a receiver of the switch or hub equipment.

Abstract: A circuit for controlling time sequence of a motherboard to supply power for a motherboard component includes a control circuit, a switch circuit, and a power conversion circuit. The control circuit is configured for receiving a startup signal during turning on the motherboard. The startup signal is configured to turn off the control circuit to delay a first voltage signal received by the first power receiving terminal for a period of time before outputting a new voltage signal. The switch circuit is configured for being turned off under the control of the new voltage signal. The power conversion circuit is configured for converting a second voltage signal into a supply voltage in response to the switch circuit being turned off, to provide the supply voltage to the motherboard component.

Abstract: A device comprising a temperature measurement module, a performance state module, and a fan speed module. The temperature measurement module is configured to determine a temperature in a server, and to output a first control signal when temperature in the server is above a threshold. The performance state module is configured to change a performance state of the device to a lowest system performance state in response to the first control signal, and further configured to reduce a processor power consumption and a subsystem power consumption to a minimum power level in response to reducing the performance state to the lowest system performance state. The fan speed module is configured to reduce a fan speed to a minimum fan speed level based on the first control signal.

Abstract: Each of a plurality of control units starts the control unit with one of a first start method and a second start. When a first control unit among the control units starts with a second start method, the first control unit instructs a second control unit among the control units to start with the second start method. Thus, all the control units are started with the same start method.

Abstract: In a method for monitoring power consumption by a system within an integrated circuit, one or more software programs are executed on the system on a chip (SOC). While the program executes, power control settings of a plurality of functional units within the SOC may be adjusted in response to executing the one or more software programs, whereby power consumption within the SOC varies over time. The power control settings may be changed in response to explicit directions from the executing software, or may occur autonomously in response to load monitoring control modules within the SOC. A sequence of power states is reported for the plurality of functional units within the SOC. Each of the sequence of power states may include clock frequencies from multiple clock domains, voltage levels for multiple voltage domains, initiator activity, target activity, memory module power enablement, or power enablement of each of the plurality of functional units.

Abstract: Embodiments provide a process and system for automatic management of networked devices based on the state of the network connection. The process automatically manages the power state of a networked computerized device according to a trigger event that corresponds to the state of an attached network connection. The network connection of an attached networked device is monitored for a pre-defined trigger event. Once a trigger event has been observed, the power state of the attached network device is managed to correspond to the trigger event.

Abstract: An electronic apparatus and a method of conserving energy comprises providing an energy-conservation module to control use of one or more energy-saving mechanism by a hardware element. The energy-conservation module comprises a performance estimation module that estimates a performance level requirement of the hardware element and a slack time. A cost-benefit qualifier module is provided that uses one or more generic algorithm and at least one separate record that characterizes power use and performance by the hardware element in relation to a Performance Power state of the selected energy-saving mechanism in order to determine an existence of an energy saving. The cost-benefit qualifier module sets the hardware element to use the Performance Power state of the selected energy-saving mechanism if the energy-saving exists.

Abstract: A switching device is comprising connectors and switching part, which is connected via the connectors to a working power supply unit, a redundant power supply unit, a battery unit and a power supply output terminal, and, in an initial state, connects the power supply output terminal and the working power supply unit, and connects the battery unit and the redundant power supply unit is connected, and in a spare state, cuts a connection between the battery unit and the redundant power supply unit, and connects the power supply output terminal and the redundant power supply unit.

Abstract: Embodiments of a system for receiving power management guidelines from a first plurality of components of a system, and developing a power management policy to manage one or more of a second plurality of components of the system based at least in part on the received power management guidelines. Other embodiments are described.

Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: An information processing apparatus used to reduce power supply to nonvolatile memory when in power saving mode. To accomplish this, the information processing apparatus stores data in the nonvolatile memory that can be used in power saving mode to a volatile memory to which power will still be supplied while in power saving mode. Further, the information processing apparatus enables the operating system to recognize the storage area in which the data is stored as a replacement for the nonvolatile memory.

Abstract: In a packet processing device capable of reducing power consumption when time intervals between input packets is increased and an input traffic capacity is reduced, packet processors, N in number (N is an integer of one or more), sequentially perform processing in response to an input packet to output a processed packet and processor packet detectors detect whether or not a packet exists in the packet processors. Responsive to a result of the processor packet detectors, a power supply switch unit controls power supply to the packet processors. Thus, each of the packet processors is intermittently put into an active state by intermittent power supply.

Abstract: Provided is a communication device capable of efficiently performing a power supply control when reducing power consumption by reducing the time during which the power is supplied. In the device, a CPU power saving control unit (301) switches between a normal mode in which the power is supplied to a CPU (302) and a low power consumption mode in which the power supply is stopped at predetermined timing. A session management table (321) stores transmission intervals before and after conversion. An information conversion section (322) converts the transmission intervals of session maintenance messages according to a predetermined rule so that the transmission intervals of the session maintenance messages of respective protocols are mutually synchronized between the protocols.

Abstract: Various example implementations are disclosed. According to one example implementation, a system may include multiple logic devices, a power input, and a logic controller. The logic devices may each be configured to assert a request for auxiliary power to a logic controller. The power input may be configured to provide the auxiliary power to one or more of the logic devices. The logic controller may be configured to poll the logic devices by polling less than all of the logic devices at a time to determine whether the logic devices assert the request for the auxiliary power.

Abstract: A computer system includes a power supply, a timing control circuit including a delay module, and a south bridge chip. The power supply outputs necessary voltages to the computer system and a first power good signal. The necessary voltages include a system voltage. The timing control circuit generates a second power good signal to the south bridge chip according to the first power good signal. The first power good signal is delayed a first time to be effective after voltages of the system voltage rise to a rated value. The second power good signal is generated after the first power good signal is delayed a second time by the delay module. The first power good signal indicates that the necessary voltages are ready in response to being effective. The second power good signal indicates that necessary input powers of the south bridge chip are ready in response to being effective.

Abstract: An apparatus, system, and method are disclosed for controlling power sequence in a blade center environment. A blade center environment has many devices requiring power. A relationship component module creates a topology of interdependent relationships of the devices. A monitor component module monitors commands to regulate power for devices. A validating module validates that the commands do not violate the interdependent relationships defined in the topology and returns a failure message if the command is not validated.

Abstract: A single terminal is used to configure an integrated circuit into one of three states. A circuit within the integrated circuit is coupled to the terminal and determines whether the terminal: 1) is coupled by a low impedance to a voltage source, or 2) is coupled by a medium impedance to the voltage source, or 3) is floating or substantially floating. The circuit asserts a first digital logic signal when the circuit determines that the terminal is coupled by the low impedance to the voltage source. The circuit asserts a second digital logic signal when the circuit determines that the terminal is coupled by the medium impedance to the voltage source. The circuit asserts a third digital logic signal when the circuit determines that the terminal is floating or substantially floating. The terminal and circuit are particular suited for use in a Power Management Unit (PMU) Integrated Circuit.

Abstract: A control for a field device comprises a monitoring unit that is separate from a control unit for controlling the field device which monitoring unit, when the control unit is in a sleep mode, waits for an activation signal in order to switch the control unit to the operating mode.

Abstract: A power management controller (PMC) that interfaces with a processor comprising one or more cores. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a target power-state. For each respective core, the state monitor may monitor active-state residency, non-active-state residency, Direct Memory Access (DMA) transfer activity associated with the respective core, Input/Output (I/O) processes associated with the respective core, and the value of a timer-tick (TT) interval associated with the respective core. The status monitor may derive respective status information for the respective core based on the monitoring and indicate whether the respective core should be allowed to transition to the corresponding target power-state. The PMC may transition the respective processor core to the corresponding target power-state accordingly.

Abstract: A microcontroller including: a first voltage detection circuit that generates a first detection signal when a power supply voltage decreases to a voltage lower than a first voltage value; a second voltage detection circuit that generates a second detection signal when the power supply voltage decreases to a voltage lower than a second voltage value that is smaller than the first voltage value; a CPU that has a function of switching between a normal operation mode and a standby mode, performs an interrupt processing operation to shift from the normal operation mode to the standby mode when the first detection signal is generated, and shifts to the standby mode independently of the interrupt processing operation when the second detection signal is generated; and a first memory circuit that stores information indicating that the CPU has shifted to the standby mode before completing the interrupt processing operation.

Abstract: A power control circuit includes an input/output controller hub (ICH), and first to third metal-oxide-semiconductor field effect transistors (MOSFETs). A drain of the first MOSFET is connected to a standby power source through a first resistor. A gate of the first MOSFET is connected to a sleep control terminal of the ICH through a second resistor. A drain of the second MOSFET is connected to the drain of the first MOSFET through a third resistor. A gate of the second MOSFET is connected to a general purpose input/output terminal of the ICH through a fourth resistor. A source of the third MOSFET is connected to the standby power source. A gate of the third MOSFET is connected to the drain of the second MOSFET. A drain of the third MOSFET is connected to a power terminal of an onboard network interface card.

Abstract: A soft start sequencer is disclosed for starting a plurality of voltage regulators, the soft start sequencer comprising a first clock for clocking a plurality of soft start circuits, wherein each soft start circuit for ramping a reference signal from a first value to a second value over a ramp time after a delay time. Each soft start circuit comprises a divider operable to divide the first clock by an integer N to generate a second clock, a first counter clocked by the first clock, the first counter operable to time the delay time, and a second counter clocked by the second clock, the second counter operable to time the ramp time after the delay time.

Abstract: A system and method for implementing a common control bus in a multi-regulator power supply integrated circuit. The integrated circuit may, for example, comprise first and second power regulator modules that control at least one characteristic of respective power signals. The integrated circuit may also, for example, comprise a communication interface module that receives power control information related to operation of the first and second power regulator modules over a shared data bus. An exemplary method may, for example, comprise receiving power control information over a data bus. The method may also, for example, comprise determining which of a plurality of power regulators corresponds to the received power control information. The method may further, for example, comprise determining a regulator control signal, based at least in part on the received power control information, and provide the regulator control signal to the determined regulator(s) to control operation of the determined regulator(s).

Abstract: A forward converter circuit includes a transformer having a primary winding and a secondary winding. A first transistor is coupled in series with the primary winding and a second transistor is coupled in series with the secondary winding. A control circuit generating control signals for controlling operation of the first and second transistors. The control signals are generated responsive to the values in certain triggered counting circuits satisfying programmable thresholds.

Abstract: An information handling system having plural processing modules, such as an information handling system blade chassis having plural information handling system blades, allocates power by determining an actual load sharing power loss associated with plural power supplies and applying the actual load sharing power loss to determine how much power to allocate to the information handling system modules. A chassis manager determines actual load sharing power loss by retrieving power information from plural power supplies. The actual load sharing power loss replaces a worst-case load sharing power loss assumed value to increase the amount power available for allocation to the information handling system modules.

Abstract: A controller and a method for power sequencing a computer. The controller may be configured to provide to a south bridge, before the south bridge has completed power management resets, a real time clock signal at a first frequency, and provide to the south bridge, after the south bridge has completed power management resets, a real time clock signal at a second frequency.

Abstract: A data processing device including an inter-VM notification management unit 1242, a resuming judgment unit 1244 and a scheduled interruption time acquisition unit 1245, such that, when it is necessary to notify a virtual machine in a power-saving state, the resuming judgment unit 1244 judges whether to cause the virtual machine to return from the power saving state, based on a time until an interruption acquired by the scheduled interruption time acquisition unit 1245. This structure prevents unnecessary transitions between states, and realizes the power saving for the apparatus.

Abstract: An apparatus for generating a power-up signal of a semiconductor memory apparatus includes a first power-up signal generator that generates a first power-up signal to be activated on the basis of a comparison between a power supply voltage level supplied to the semiconductor memory apparatus and a first set voltage level, and a second power-up signal generator that generates a second power-up signal to be activated with a predetermined delay time on the basis of a comparison between the power supply voltage level and a second set voltage level.

Abstract: A system which includes a disk drive or other storage device coupled to a host system provides for reduction of the amount or rate of drive power consumption using procedures which are at least partially executed on the host. The system can be configured to reduce average power draw, maximum power draw, or both. Host-based procedures can be tailored to specific and/or changing environments and can decrease some or all expenses associated with previous attempts to reduce HDD power consumption.