Abstract: The present disclosure provides an electronic device having rotary input members. The device includes a substantially cylindrical main body, at least one hollow rotary input member rotatably connected to the main body, at least one pair of pads including two pads spaced from each other, arranged on the main body and beneath the at least one rotary input member, at least one selection contact arranged on an internal surface of the at least one rotary input member, and a processing unit. When a closed loop includes a pair of pads, a selection contact and the processing unit is formed, the processing unit determines input characters according to a relationship table.

Abstract: In some embodiments, the invention involves modification of the processor utilization calculations that are used by operating system power management services to improve processor efficiency. An embodiment of the present invention is a system and method relating to power management policies under operating system control. In at least one embodiment, the present invention is intended to modify the processor utilization evaluation process so that C-state transition time and/or unhalted reference cycles are included in the calculation. Other embodiments are described and claimed.

Abstract: A power management apparatus includes: a service request monitor block for receiving service requests by service groups to provide load information of service platforms belonging to the respective service groups; a platform information collection block for collecting a configuration information of the service platforms and collecting load information of the service platforms in a predetermined cycle; a platform power state alteration block for altering power states of the service platforms by request; and a management interface block for providing a setup interface for a load-based and a time-based power control and providing platform profile information generated based on the load information.

Abstract: An exemplary electronic device includes a detecting component and a storage unit. The detecting component generates detecting signals when the electronic device has been disassembled. The storage unit stores disassemble history information based on detecting signals received from the detecting component.

Abstract: A device for controlling power comprising a power source input, at least one power contact or outlet, a power control relay, a digital signal input port and a digital signal detector. The device controls power from the power source input to the at least one power contact or outlet by operation of the power control relay. The power control relay opens or closes based on the presence of a digital signal or lack thereof. The detection of the presence of the digital signal or the lack thereof is accomplished by the digital signal detector electrically coupled to the digital signal input port. Detection of a digital signal may be accomplished by using one or more Ethernet signal detectors capable of detecting data transmission or the presence of PoE. Additionally, a method is taught to control power to power consuming devices by using the aforementioned device.

Abstract: A network system forms a computer network, and includes: a collecting unit; a calculating unit; and a display unit. The collecting unit collects power consumption information from a connecting device. The power consumption information shows power consumption of the connecting device. The calculating unit calculates power consumption of the computer network based on the collected power consumption information. The calculated power consumption is itemized into constituent units based on a configuration of the computer network. The display unit displays the calculated power consumption.

Abstract: A process for transmitting a message between a first electronic device and a second electronic device of an energy distribution network is described. The process includes generating, by the first electronic device, a first data encryption key identifying the second electronic device on the basis of a main data encryption key and an identification code of the second electronic device. The process further includes generating, by the first electronic device and the second electronic device, a communication key on the basis of said first data encryption key and a reference datum.

Abstract: Handshaking circuits are provided in a communications cable and in a device operable to be mated with the communications cable. Before a device can utilize the power supply signal of such a communications channel, the two handshaking circuits must sufficiently identify one another over a power supply signal with a decreased voltage. The decreased voltage allows for a cable plug to be provided with a safe, protected power that cannot cause harm to a human. The decreased voltage also reduces the chance that a device can receive a primary power supply signal from the cable before the device sufficiently identifies itself. Accordingly, a laptop may be connected to a portable music player, but the voltage of the power supply signal provided by the laptop to the cable may be decreased on-cable until the handshaking circuit of the portable music player sufficiently performs a handshaking operation with a on-cable handshaking circuit.

Abstract: A liquid crystal display device includes a liquid crystal panel, a driving circuit and a backlight unit supplying light to the liquid crystal panel. The liquid crystal display device further includes a power management unit. The driving circuit includes a plurality of sub-circuits. The power management unit may provide a common voltage to the driving circuit and the backlight unit. A driving method of the liquid crystal display device includes halting an image display operation of a liquid crystal panel in response to a change of an operation mode. The driving method further includes sequentially changing operations of the plurality of sub-circuits.

Abstract: A mobile phone that uses OS virtualization for minimizing power consumption in mobile phones is provided. Apparatus and methods may involve conserving processor power in a mobile phone according to the invention may include the following steps. A first step may be awakening a first processing core from a low power state in response to a first operating system (OS) thread. A following step may include processing the first OS thread using the first processing core. A next step may include determining whether utilization of the first processing core over a first time period has exceeded a predetermined threshold. The method may also include awakening a second processing core from a low power consumption state if utilization of the first processing core over a first time period has exceeded a predetermined threshold.

Abstract: Methods and systems are provided for managing power allocation to a SAS target coupled with a SAS initiator through a SAS expander. The expander exchanges messages with the target to manage the power allocation to the target. The target transmits a power request message through the expander to the initiator. In some embodiments, the initiator transmits a power request received message to the expander. The expander may then transmit a power grant message to the target in response to receiving the power request received message. In other embodiments, the expander monitors the messages transmitted from the target to the initiator. The expander may then transmit a power grant message to the target in response to the expander monitoring the power request message.

Abstract: A system and method is provided to measure the power consumption of circuits whereby, in one aspect, a processor's temperature is maintained so that its power consumption is measured at the point the processor throttles.

Abstract: A multi-processing system-on-chip including a cluster of processors having respective CPUs is operated by: defining a master CPU within the respective CPUs to coordinate operation of said multi-processing system, running on the CPU a cluster manager agent. The cluster manager agent is adapted to dynamically migrate software processes between the CPUs of said plurality and change power settings therein.

Abstract: A main computer for vehicle includes a central processing unit and a programmable logic device. The central processing unit is configured for controlling operations of the main computer. The programmable logic device is coupled to the central processing unit and includes a built-in power state machine for managing power statuses of the main computer. The power state machine includes a turn-off status, an operating status, and a predetermined status located between the turn-off status and the operating status.

Abstract: An information processing apparatus includes a plurality of storage units, a mirroring control unit configured to execute mirroring processing, which includes writing processing for writing same data on each of the plurality of storage units and reading processing for reading data from either one of the plurality of storage units, and a power control unit configured to independently control supply of power to the plurality of storage units. If the supply of power to the plurality of storage units is reduced, if the mirroring control unit starts the writing processing, the information processing apparatus resumes the power supply to the plurality of storage units, and if the mirroring control unit starts the reading processing, the information processing apparatus resumes the power supply to a specific storage unit from which the data is read, and configured to execute control not to resume the power supply to the other storage unit(s).

Abstract: A method and apparatus for fail-safe start-up circuit for subthreshold current sources have been disclosed.

Abstract: A method and apparatus for user activity-based dynamic power management and policy creation for mobile platforms are described. In one embodiment, the method includes the monitoring of one or more sensor values of a mobile platform device to gather sensor activity data. Once the sensor activity data is gathered, the user state may be predicted according to the gathered user activity and an updated user state model. In one embodiment, the user state model is updated according to the sensor activity data. In one embodiment, a switch occurs from the present power management policy to a new power management policy if the new user state differs from a present user state by a predetermined amount. In one embodiment, at least one time-out parameter of a selected power management policy may be adjusted to comply with a predicted user state. Other embodiments are described and claimed.

Abstract: A method, computer program product, and system are provided for controlling a clock distribution network. For example, an embodiment of the method can include programming a predetermined delay time into a plurality of processing elements and controlling an activation and de-activation of these processing elements in a sequence based on the predetermined delay time. The processing elements are located in a system incorporating the clock distribution network, where the predetermined delay time can be programmed in a control register of a clock gate control circuit residing in the processing element. Further, when controlling the activation and de-activation of the processing elements, this activity can be controlled with a state machine based on the system's mode of operation.

Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Abstract: A system including an integrated circuit (IC) and a power supply regulator external to the IC. The IC operates in accordance with an active mode and a lower power mode, and is configured to retain a logical state during the low power mode. The power supply regulator is configured to i) supply a first voltage potential to a first pin of the IC during the active mode, and ii) disable the first voltage potential during the low power mode. The IC is configured to provide a first feedback signal from an internal supply of the IC to the power supply regulator via the first pin.

Abstract: Methods, computers, and products for managing power consumption of a computer, the computer including a computer processor and managing power consumption of a computer includes: dynamically during operation of the computer, setting, by an in-band power manager in dependence upon performance metrics of the computer processor, a current performance state (‘p-state’) of the computer processor; and providing, by the in-band power manager to an out-of-band power manager, the current p-state of the computer processor.

Abstract: A computer system capable of dynamically modulating an operation voltage and an operation frequency of a CPU comprises: a CPU from which a VID1 is outputted based on a real load of the CPU; a VID converting/comparing controller capable of determining to operate in an bypass mode or a calculation mode in response to the received VID1 signal and capable of outputting a VID2 signal and a control signal; a frequency generator for generating a CPU clock with a specific frequency to the CPU in response to the control signal; and a PWM controller capable of generating the operation voltage to the CPU in response to the VID2 signal; wherein when the VID converting/comparing controller is switched to operate in the calculation mode, the VID1 signal is not equal to the VID2 signal and the specific frequency is modulated to either a higher or a lower than a normal operation frequency by the VID converting/comparing controller.

Abstract: A computer system capable of dynamically modulating a core-voltage and a clock frequency of a CPU is provided.

Abstract: Systems and methods are disclosed for detecting the connection of a FireWire peer to a FireWire device. In one embodiment, a device may determine whether a peer connection is present based on peer detection circuit configured in each FireWire port of a FireWire device. When no peer is connected to a device, a peer connection in the circuit may be open, and a current path through the circuit may provide a low detect signal, indicating that no peer is connected. When a peer is connected to a detecting device, the current may pass through a resistance in the detected peer to provide a high detect signal, indicating that a peer is connected. In some embodiments, once a peer is detected, the FireWire system of the detecting device may be powered on, and the peer detection circuit may be powered off.

Abstract: Gaming machines and related methods for controlling and managing electrical current to peripheral devices in a gaming machine are described. A gaming machine having multiple high-current peripheral devices drawing power from a single power supply within the gaming machine is able to regulate the timing at which the peripherals may receive power. The gaming machine may be a multi-station gaming machine, such as a gaming table, where each station has various standard peripheral devices. The gaming machine determines whether the power required by the peripherals at any given time will exceed a threshold current supply and, if so, delays the operation of one of the peripherals to regulate the amount of current the power supply has to supply at any given time. Current usage and time overlaps of two or more peripheral devices are determined using current profiles of the devices.

Abstract: A semiconductor IC device capable of power-sharing includes a first power line configured to be supplied with a first power, a second power line configured to be supplied with a second power, a switching block configured to connect the first power line with the second power line in response to a first control signal, and a power-sharing control block configured to generate the control signal in accordance with a plurality of operation command signals.

Abstract: A power supply includes a power supply module, a microcontroller, a setting unit, a number of switch units, a number of current detection units, and a number of output connectors. Each switch unit is connected to one output connector via one current detection unit. The power supply module converts an alternating current (AC) voltage into a direct current (DC) to power electronic devices connected to each output connector by the corresponding switch unit, and the corresponding current detection unit. Each current detection unit detects a current passing through the output connector. The microcontroller calculates a total power of the power supply module according the detected currents and the DC voltage, and turns off all the switch units when the total power is greater than a predetermined current according to a protection mode set in the setting unit.

Abstract: A semiconductor integrated circuit includes a scan chain which includes: first flip-flops contained in a first circuit and second flip-flops contained in a second circuit, wherein the first flip-flops and the second flip-flops are connected in a series connection in a scan path test mode to operate as a shift register, and a first selecting circuit configured to selectively output a test data in the scan path test mode and internal state data indicating an internal state of the first flip-flops and read from a memory circuit in a restoring operation in a normal mode to the series connection.

Abstract: Methods, systems, and devices are disclosed for producing and delivering packetized power within a DC computing environment. Within the DC computing environment a power requirement or request is communicated to a power router. The power router then determines a power source capable of fulfilling the power requirement and then causes the power to be delivered in packetized form. The packetized power is appended to a message header which allows the power packet to be received by the requesting device.

Abstract: Methods and systems to balance the load among a set of processing units, such as servers, in a manner that allows the servers periods of low power consumption. This allows energy efficient operation of the set of processing units. Moreover, the process is adaptable to variations in systemic response times, so that systemic response times may be improved when operational conditions so dictate.

Abstract: A system and method for tunneling control over a MAC/PHY interface for legacy ASIC support. Energy efficient Ethernet control or status information can be communicated over a MAC/PHY interface using control codes that are embedded in sequence ordered sets. These sequence ordered sets would not affect the data flow and can be tunneled within an existing interface (e.g., XAUI, XFI, xxMII or derivative interfaces) without generating errors.

Abstract: Reducing current draw of solid state drives from a shared power supply of a computer at computer startup, each SSD including computer memory, a capacitor, a disk controller, and a charge controller, the disk controller configured to enable the charge controller to charge the capacitor upon receiving a charge command, the SSDs organized into startup groups characterized by a position in a predefined startup order. Upon startup of the computer, beginning with a first startup group in the predefined startup order and until the last startup group in the predefined startup order has received a charge command, embodiments include, sending, by a storage device initiator, a charge command to a startup group to initiate charging of the capacitor of each solid state drive in the startup group and waiting a predefined period of time before sending another charge command to a next startup group in the predefined startup order.

Abstract: A micro-processor includes a clock generator configured to generate a fetch clock, a decoding clock, an execution clock, and a write-back clock that are sequentially enabled; a volatile memory device configured to output pre-stored program data in response to the fetch clock; a command decoder configured to decode the program data in response to the decoding clock and generate a decoding command; an arithmetic device configured to perform an arithmetic operation according to the command of the decoding command in response to the execution clock; and a peripheral circuit device configured to be operated according to the command of the decoding command in response to the write-back clock.

Abstract: An information handling system includes a processing system, a low-power processing system, and a chipset. The processing system is configured to operate using a power system configured to power a shared resource of the processing system and a non-shared resource of the processing system, and to disable the non-shared resource during a reduced operating state of the processing system. The low-power processing system is configured to access the shared resource of the processing system during operation of the low-power processing system, wherein the operation of the low-power processing system is separate from the operation of the processing system. The chipset includes a processor of the processing system and operable to be enabled during operation of the processing system, wherein the processor is configured to be disabled during operation of the low-power processing system.

Abstract: An information handling system (IHS) is disclosed providing a power supply operable to provide an output current to the IHS during power initiation. The IHS may also include a first power component associated with a first power stage wherein the first power stage may have a first current threshold. Furthermore, the IHS may include a power control logic coupled to the power supply and the first power component. As such, the power control logic may be operable to communicate the first power stage to the power supply, and if the output current does not exceed the first current threshold during the first power stage, the power control logic may be operable to communicate a second power stage having a second current threshold to the power supply.

Abstract: Disclosed is a dynamic detector to detect an environmental condition including a power-supply level relative to a predetermined threshold signal during a training phase; and an adjustable buffer, coupled with the dynamic detector, configured to adjust output drive strength during the training phase in response to the detected environmental condition.

Abstract: Illustrative embodiments estimate power consumption within a multi-core microprocessor chip. An authorized user selects a set of activities to be monitored. A value for each activity of the set of activities is stored in a separate counter of a set of counters, forming a set of stored values. The value comprises the count multiplied by a weight factor specific to the activity. The set of activities are grouped into subsets. The stored values corresponding to each activity in each subset are summed, forming a total value for each subset. The total value of each subset is multiplied by a factor corresponding to the subset, forming a scaled value for each subset. The scaled value of each subset is summed, forming a power usage value. A power manager adjusts the operational parameters of the unit based on a comparison of the power usage value to a threshold value.

Abstract: A computer system includes a main device and a subordinate device. Data transmission and reception by means of an optical transmission system are performed by connecting the main device and the subordinate device by an optical transmission cable. The subordinate device, a power of which needs to be cut-off prior to the main device, includes a light reception determination part and a power supply control part. The light reception determination part determines whether the main device is in a power-off state by presence or absence of light reception based on a light-receiving amount received by a photoelectric converter. When it is determined that the main device is in the power-off state, the power supply control part controls a power supply device so as to cut-off the power of the subordinate device.

Abstract: Circuit, method for operating a circuit, and use, having a voltage regulator, which has a regulator output for providing a supply voltage, which for the supply can be connected to at least one first digital subcircuit via a first switch and to a second digital subcircuit via a second switch, wherein the voltage regulator is formed to output a first status signal dependent on the supply voltage, and to turn on the first switch by the first status signal is connected to a first control input of the first switch, and the first switch is formed to output a second status signal dependent on its switching state, and to turn on the second switch by the second status signal is connected to a second control input of the second switch.

Abstract: A method, system, and computer program product for optimizing power consumption of an executing processor executing. The method includes determining a first sensitivity relationship (SR) based on a first and a second performance metric value (PMV) measured at a first and second operating frequency (OF), respectively. The first SR predicts workload performance over a range of OFs. A third OF is determined based on the first SR and a specified workload performance floor. A third PMV is measured by executing the processor operating at the third OF. A second SR based on the second and third PMVs is then determined. The first and second SRs are logically combined to generate a third SR. Based on the third SR, a fourth OF is outputted.

Abstract: A suspend mode is provided that can be asserted using an Internal Configuration Access Port (ICAP) of an integrated circuit such as a Field Programmable Gate Array (FPGA), as supposed to a dedicated external suspend pin typically accessed by a device external to the FPGA. The ICAP is designed to assert the suspend mode through a configuration block to maintain the state of the configuration memory array while lowering power, in a similar manner to when an external suspend pin is accessed. Internal circuits can, thus, be used to assert a suspend mode through the ICAP.

Abstract: A method is disclosed that includes receiving a classification voltage at a powered device from a network. The classification voltage includes a baseline voltage level that is below an operating voltage range of the powered device and includes a sequence of distinct signal elements derived from the classification voltage. The method further includes detecting a number of signal elements of the sequence of distinct signal elements. A current is drawn until the number of signal elements exceeds a predetermined number.

Abstract: A computer motherboard includes a number of peripheral device interfaces, first and second voltage output terminals, and a number of power supply circuits corresponding to the S peripheral device interfaces. Each peripheral device interface includes a first power pin and a second power pin. Each power supply circuit includes a delay circuit, and first to third electronic switches. The delay circuit controls the first electronic switch to be turned on after a delay time. The delay times of the power supply circuits are different. The second and third electronic switches are turned on in response to the first electronic switch being turned on. The first voltage output terminal is connected to the first power pin through the second electronic switch. The second voltage output terminal is connected to the second power pin through the third electronic switch.

Abstract: A time sequence control circuit is provided to control time sequence of a motherboard of a computer. A first voltage received by a power supply receiving terminal is greater than a preset voltage before a signal control terminal on the motherboard receives a second voltage during turning on the computer. During shutting off the computer, the first voltage at the power supply receiving terminal drops and is less than the preset voltage, and the second voltage supplied to the signal control terminal on the motherboard is shut off.

Abstract: A method of managing power consumption by a plurality of blade servers within a processing system. The speed of at least one of the plurality of blade servers is reduced in response to the processing system reaching a power or thermal threshold. At least one of the plurality of blade servers is identified as not being critical to maintain in a working state and the critical blade server is put in a sleep state. A satellite management controller may control blade server power consumption and heat generation in various ways that combine processor speed-stepping and control of processor sleep states. Known sleep states save more power than speed-stepping by turning off the processor and/or volatile memory. The processor speed and sleep-states of at least one non-critical blade server, and optionally the processor speed of a critical processor, may be changed in order to control the power consumption below a power threshold or control the temperature below a thermal threshold.

Abstract: A master/slave device system includes a baseboard, a master device connected to the baseboard, and at least one slave device communicatively connected to the master device. The baseboard provides a power source. A switch connects the power source and the at least one slave device. The switch is capable of being switched on when a predetermined time is reached. The at least one slave device is capable of automatically setting an address at the moment the switch is switched on. The master device is capable of identifying the at least one slave device using the address.

Abstract: A portable electronic device is operative to facilitate power sharing with at least a second electronic device coupled thereto. The portable electronic device includes a battery power source, a first port adapted for connection to a first network connection and a second port adapted for connection to a second network connection. An input stage in the portable electronic device is connected to the first port. The input stage is operative to supply power received from the first network connection through the first port to the battery power source for recharging the battery power source. The portable electronic device further includes an output stage connected to the second port. The output stage is operative to supply power from the battery power source to the second network connection through the second port.

Abstract: A system for powering on downstream devices includes a master device; a first slave device; and a first communication link connecting the master device to the slave device for enabling the master device to transmit data signals to the slave device. The master device includes a power-on signal generator for injecting a power-on signal onto the communication link and the first slave device includes a power-on signal receiver for detecting the power-on signal injected on the communication link by the power-on signal generator and powering on the first slave device.

Abstract: System and method for controlling a fan. A value may be received for controlling the fan. The value may include a first number of bits and may correspond to a linear function of temperature. A first value may be determined using a first number of bits of the value. A modification to the first value may be determined based on a second number of bits of the value. A new output value may be generated based on the first value and the modification to the first value. The new output value may correspond to a first nonlinear function of temperature. The new output value may be provided for controlling the fan.

Abstract: The invention has disclosed a system power management circuit comprising: a printed circuit board and a hardware monitor. The printed circuit board includes at least a first power connector, a second power connector, and more than one detection circuits disposed thereon; wherein the first power connector is used for electrically connecting a power supply, the second power connector is used for electrically connecting a power connector of a motherboard, inputs of the detection circuits are electrically connected to the first power connector, respectively. The hardware monitor is electrically connected to outputs of the detection circuits, and used for converting electrical signals outputted from the outputs of the detection circuits into corresponding digital signals, as well as for transmitting the digital signals to the motherboard via a two-wire bus, the two-wire bus is bi-directional, and may be an I2C or a SM bus.