Abstract: The present invention discloses a power-aware compiling method, wherein the power model of an application program are established via building and analyzing the control flow chart and the data flow chart of the application program; each functional unit of the application program is assigned a power mode; a judgment is undertaken to determine whether the idle functional units are independent; if none dependency exists between those idle function units, the program codes of the same idle function units are merged into a new basic block, and the idle functional units are turned off for saving power; each new basic block is assigned an appropriate power mode; the basic blocks with the same power modes are merged to reduce the transitions between different power modes; thus, the power consumed by changing voltage or frequency can be decreased.

Abstract: A data processing unit having a field of clocked logic cells (PAEs) which is operable in different configuration states and a clock preselecting means for preselecting logic cell clocking. The clock preselecting means is designed in such a way that, depending on the state, a first clock is preselected at least at a first cell (PAE) and an additional clock is preselected at least at an additional cell.

Abstract: A system may include a switchover element configurable to source or sink power from or to an electronic device electrically coupled to the switchover element and a controller in communication with the switchover element. The controller may be configured to determine if the electronic device is healthy. When the electronic device is healthy, the controller may configure the switchover element to deliver power from the electronic device to the system and configure the switchover element to provide the power to any unhealthy electronic device electrically coupled to the system.

Abstract: An apparatus for on-demand power management including a system controller, a clock domain manager coupled to the system controller and a power distribution manager coupled to the system controller. The system controller monitors a processing demand in a processing system. The clock domain manager provides one or more clock frequencies and, in response to the processing demand, switches between a first set of clock frequencies and a second set of clock frequencies without halting the processing system. The power distribution manager provides one or more operating voltages and, in response to the processing demand, switches between a first set of voltages and a second set of voltages without halting the processing system.

Abstract: A device (12) supplies energy to a rapid cycling and/or rapidly cycled integrated circuit (13, 52) which includes a circuit load (17) and an internal capacity (15) connected parallel to the circuit load (17). The integrated circuit (13, 52) has a high cycle frequency (f1) especially at least in the MHz range. A supply unit (14) especially designed as a current source is directly connected to the internal capacity (15). The supply unit (14) has an internal resistance, the impedance level of which is so high at the cycle frequency (f1) that a current (ID2) supplying the circuit load (17) originates to a greater degree from the internal capacity (15) than from the supply unit (14). At least one auxiliary load, current sink or load controller is provided as an integral component of the integrated circuit and is connected to the circuit load to smooth load fluctuations.

Abstract: A memory controller, a method of testing memory power management modes in an integrated circuit and an integrated circuit. In one embodiment, the memory controller includes a power management mode test controller couplable to a test access port and at least one memory core and configured to respond to a signal provided via the test access port by providing an ordered signal-setting sequence to the at least one memory core to cause the at least one memory core to enter into and exit from at least one memory power management mode.

Abstract: Based on bounds of a period of reduced operation for a base device, a base device generates a power management message for transmission to a peripheral device. In the power management message, the base device inserts bounds of a period of reduced operation for the peripheral device. As a result, the periods of reduced operation conserve battery power in both devices and the two devices may reestablish a communications channel upon reaching the end of the period of reduced operation and resuming normal operations.

Abstract: A power supply control apparatus that includes an instruction component, an execution component and a power supply control component is provided. The power supply control component is equipped with at least two measurement functions that have different measurement durations for cases in which the duration until interrupting the power supply to device(s) is measured, wherein measurement is activated with a first measurement function of relatively long measurement duration at a completion time of prior image processing, and measurement is activated with a second measurement function of relatively short measurement duration for device(s) to which power is being supplied at the time of completion of the prior image processing but which are not required in later image processing.

Abstract: A starting device includes a first transform device that restores a first transfer signal, which is converted from an input signal supplied from an input device, to the input signal, and outputs the input signal to a computer, and a power connecting device that starts the computer when the input signal restored by the first transform device includes a starting signal.

Abstract: An image forming apparatus includes a printing unit, a controlling unit, and a monitoring unit to monitor, while the printing unit and the controlling unit are in a power-saving mode in which power supply to the printing unit and the controlling unit is stopped, whether there is a resuming factor for resuming operation from the power-saving mode. When the resuming factor is detected, the monitoring unit sends to the printing unit a request to resume operation and a request to set a printing mode, before sending a request to resume operation to the controlling unit.

Abstract: A storage system includes a housing, a cooling unit cooling the interior of the housing, and a plurality of control units adapted to control the cooling unit. The control units each include a mount state acquisition unit acquiring a mount state of the control unit in the housing, an operation state acquisition unit acquiring an operation state of the cooling unit, and a determining unit determining a provisional main control unit, from among the plurality of control units, that is operable to control the entire cooling unit based on information acquired from the mount state acquisition unit and the operation state acquisition unit.

Abstract: This invention is a power management scheme for a shared memory multiprocessor system which splits the control logic between the master-specific logic and memory bank logic. Power-down is initiated from a central power-down controller. This central power-down controller informs the master and target specific logic. Further memory accesses are blocked. All pending activities complete. The central controller then proceeds to power down the memory and informs the master and target specific logic upon completion. No requests for wakeup are initiated by master-specific logic from the time a power-down request is received until the completion of power-down.

Abstract: Controlling processors and processor hardware components in a computing device based on execution load and a power saving preference. The power saving preference relates to responsiveness of the processors versus power consumption of the processors to manage battery life of the device. The processors and processor hardware components may be powered on and off based on a determined execution load for the processors and based on the power saving preference. For example, arithmetic logic units, caches, vectorization units, and units for graphics or multimedia support may be individually enabled or disabled based on the execution load and the power saving preference.

Abstract: Disclosed are a circuit and a method for controlling dynamic in-rush current in a power management circuit. The circuit includes a current limiting unit having a first quantity of sleep mode devices. A voltage drop minimization unit is coupled to the current limiting unit and has a second quantity of sleep mode devices. The second quantity of sleep mode devices is greater than the first quantity of sleep mode devices. A sequential enabling unit is coupled to both the current limiting unit and the voltage drop minimization unit. The sequential enabling unit is configured to turn on the voltage drop minimization unit after the current limiting unit in accordance with a predetermined delay.

Abstract: Integrated circuits are provided with circuitry such as multiplexers that can be selectively configured to route different adjustable power supply voltages to different circuit blocks on the integrated circuits. The circuit blocks may contain memory elements that are powered by the power supply voltages and that provide corresponding static output control signals at magnitudes that are determined by the power supply voltages. The control signals from the memory elements may be applied to the gates of transistors in the circuit blocks. Logic on an integrated circuit may be powered at a given power supply voltage level. The memory elements may provide their output signals at overdrive voltage levels that are elevated with respect to the given power supply voltage level. Memory elements associated with circuit blocks that contain critical paths can be overdriven at voltages that are larger than memory elements associated with circuit blocks that contain noncritical paths.

Abstract: A power management device can include a power management device housing, a power input associated with the power management device housing, and a plurality of power outputs associated with the power management device housing. At least certain power outputs can be connectable to one or more electrical loads external to the power management device housing and to the power input. In some embodiments, a communications bus can be associated with the power management device housing and one or more power control sections can also be associated with the power management device housing. In some embodiments, one or more power control sections can communicate with the communications bus and with one or more corresponding power outputs among the plurality of power outputs. In some embodiments, a power information display can communicate with the communications bus.

Abstract: A data path controller, a computer device, an apparatus and a method are disclosed for integrating power management functions into a data path controller to manage power consumed by processors and peripheral devices. By embedding power management within the data path controller, the data path controller can advantageously modify its criteria in-situ so that it can adapt its power management actions in response to changes in processors and peripheral devices. In addition, the data path controller includes a power-managing interface that provides power-monitoring ports for monitoring and/or quantifying power consumption of various components. In one embodiment, the data path controller includes a power-monitoring interface for selectably monitoring power of a component.

Abstract: Methods and apparatus, including computer program products, are provided for shutting down a host, such as a computer, server, and the like, to enable power savings. In one aspect, there is provided a computer-implemented method. The computer-implemented method includes determining whether to shutdown an application at a virtual machine. The determination is made using information from the application. The virtual machine and application operate on a host. A power management mechanism of the host may be initiated to enable a power savings when compared to not shutting down the host. Related apparatus, systems, methods, and articles are also described.

Abstract: In an example embodiment, a method for speculative power saving. The beginning portion of a header (e.g. a physical layer convergence protocol “PLCP” header of a beacon) is processed to determine whether a predefined bit is set that indicates whether the frame contains any delivery traffic indication for buffered multicast and/or unicast frames. If the bit is set, indicating the frame contains no delivery traffic indication of buffered frames, receiving and processing of the frame stops (e.g. the remainder of the PPDU is not processed) and the receiver switches to a power save state. In an example embodiment, if a predefined NULL beacon frame is detected, receiving and processing of the frame (and PPDU) stops and the receiver switches to a power save state.

Abstract: A method, apparatus, article of manufacture, and system, the method including, in some embodiments, determining an impedance of a power distribution network of a load for a range of frequencies, and adjusting a functionality of the load based on a relationship between the impedance of the power distribution network for the range of frequencies and the functionality of the load.

Abstract: Provided is a control method for an advanced configuration and power interface (ACPI) in a computer system. The computer system comprises a processor and a bus master, wherein the processor, as defined by the ACPI specification, has a first state (C0 state), a second state (C1 state), a third state (C2 state), a fourth state (C3 state) and a fifth state (C4 state). The method comprises enabling the processor to run in the C2 state when a request from the bus master is issued before the processor enters the C3 state, or enables the processor to ignore the C4 state and complete the C3 state when the request from the bus master is issued at the C3 state and before entering the C4 state.

Abstract: A method and apparatus for power management of a network element. In one embodiment of the invention, a networking card configuration request is received for a type of networking card irrespective of a networking card of that type being inserted into the network element. The network element does not enable networking cards unless they are successfully configured and inserted. The amount of power that the networking card consumes is determined without reading a power consumption value from that card. If it is determined that allowing that type of networking card to be configured would exceed the power capacity of the network element, the configuration request is denied and the networking card, if or when inserted remains disabled and is not powered up. However, if allowing that type of networking card to be configured would not exceed the power capacity, the configuration request is accepted, the amount of power that type of networking card consumes is allocated, and the card will be enabled when inserted.

Abstract: An automatically configurable power control unit (PCU) is described that can be configured and used to satisfy requirements of different power domain of an integrated circuit. When implemented the PCU is automatically configured into a power control manager (PCM) along with other PCU's used with additional power domains in the integrated circuit. The PCM dispatches power on and off commands to each PCU contained within the PCM, schedules power on and off sequences amongst a plurality of PCU controlled by the PCM, blocks inappropriate power mode commands and monitors the state of each power domain coupled to the various PCU controlled by the PCM.

Abstract: A power monitor for electronic devices, such as computer chips, is used to estimate the power consumption and to compare the estimated power consumption against the power budget. The estimated power consumption is based on activity signals from various functional blocks of the computer chip. The activity signals that are monitored correlate accurately to the total number of flip-flops that are active at a given time. If the estimated power consumption exceeds the power budget, the speed of the clock signals supplied to the computer chip is reduced.

Abstract: Described is a storage system and method for managing and optimizing power consumption in a storage system. Logical devices are mapped to physical disk drives. A plurality of power profiles is defined. Each power profile is associated with a mode of operation for a physical disk drive. One of the power profiles is assigned to each logical device. One of the physical disk drives is identified for which every logical device mapped to that physical disk drive has been assigned the same power profile. The identified physical disk drive is operated in the mode of operation associated with said same power profile. The mapping of the logical devices to the physical disk drives may be changed in order to group logical devices assigned the same power profile onto the same physical disk drive.

Abstract: A computer system including a power supply, a plurality of mainboards, and a power controller is provided. Each of the mainboards corresponds to a standby voltage, respectively. The power supply generates a standby power, and generates a main power according to a power enabling signal. The power controller is coupled between the power supply and the mainboards, for generating the power enabling signal and a control signal according to whether an amount of the mainboards is greater than a predetermined value, and selectively outputting the control signal to at least one of the mainboards. When the mainboards receive the control signal, regardless being in a booting state or a non-booting state, the mainboards receive the main power and converts the main power into a standby voltage corresponding thereto. When failing to receive the control signal, the mainboards convert the standby power into the standby voltage corresponding thereto.

Abstract: Systems and methods for power management in an information handling system are disclosed. A method may include determining a power requirement of resources configured to receive power from a plurality of power supply units including one or more online power supply units, one or more redundant power supply units, and one or more standby power supply units. The method may also include determining a power capacity of the one or more online power supply units. The method may additionally include determining if the power capacity of the one or more online power supply units exceeds the power requirement of the resources. The method may further include transitioning at least one of the power supply units based on such determining steps.

Abstract: A host device and a storage device with a Serial ATA (SATA) architecture to independently transition to a deeper low power state after first entering an initial low power state without first transitioning to the Active state. The transition from the Partial state to the Slumber state is direct and the transition may be enabled, but not negotiated through a handshaking process.

Abstract: A method for reducing power consumption of a processor is disclosed comprising steps of applying time-frequency transformation to a plurality of load values of the processor to obtain the feature sampling cycle of the processor, and adjusting the voltage/frequency of the processor based on said feature sampling cycle. With the method of the present invention, the processor load value in next time interval can be accurately predicted, and thus the voltage/frequency of the processor in the next time interval can be adjusted on the basis of the load value.

Abstract: A device capable of controlling a supply voltage and a supply frequency using information of a manufacturing process variation includes a data storage device storing data indicating performance of the device, a decoder decoding the data stored in the data storage device and outputting decoded data, and a frequency control block outputting a frequency controlled clock signal in response to the decoded data output from the decoder. The device further includes a voltage control block outputting a level controlled supply voltage in response to the decoded data. The voltage control block outputs a body bias control voltage controlling a body bias voltage of at least one of a plurality of transistors embodied in the semiconductor device in response to the decoded data. The performance is operational speed of the device or leakage current of the semiconductor device.

Abstract: A method and apparatus to control an operating clock frequency of a hard disk drive. The method includes analyzing a command workload, and changing the operating clock frequency of the hard disk drive based on an analysis result. Alternatively, the method includes measuring a time taken to receive a predetermined number of write/read commands and controlling the operating clock frequency of the hard disk drive based on a result of a comparison of the measured time with at least one reference value. An operating clock frequency control block included in the hard disk drive executes the method.

Abstract: A plurality of power budgets are sent to a corresponding plurality of power consumers by a power management point, wherein a total power budget managed by the power management point includes a sum of the plurality of power budgets and an available power budget not assigned to the plurality of power consumers. An additional power request having a power increase amount is received from a first power consumer of the plurality of power consumers. The additional power request is approved when the power increase amount does not exceed the available power budget. The available power budget is decreased by the power increase amount. An approval of the additional power request is sent to the first power consumer.

Abstract: An apparatus for selectively enabling power including a power supply, and a device having a controller and an input activated by a user. The controller is selectively powered by the power supply. While the device is in a sleep state, a sensing circuit senses activation of the input by the user and enables the power supply to provide power to the controller in response to the sensed activation of the input by the user. A latch circuit causes the power supply to continue to provide power to the controller. The controller is responsive to the sensed activation of the input by the user for enabling the latch circuit and for disabling the latch circuit, thereby reentering the device into a sleep state.

Abstract: Apparatus and methods for setting wakeup times in a communication device are disclosed where setting the wakeup times includes estimating the lock on time of a frequency synthesizer in order to minimize the wakeup time and extend sleep times for maximal energy savings. A disclosed apparatus includes an estimator to receive a current lock on time of a frequency synthesizer, which is the time taken by the frequency synthesizer to lock on to particular frequency after a wakeup signal has been issued to turn on the synthesizer after a sleep period. The estimator calculates a latest estimated lock on time based at least on the current lock on time of the frequency synthesizer and determines an enable signal timing information based on the estimated lock on time. The apparatus also includes a timer configured to receive the enable signal timing information and issue at least one enable signal to turn on other circuitry in the transceiver after the synthesizer lock on period based thereon.

Abstract: The electric power supply system includes a first terminal that electric power is supplied thereto from a first power supply to operate, a second terminal that is connected to the first terminal and that electric power is supplied thereto from a second power supply to operate, and a controller that controls electric power supply so as to supply electric power from the first terminal to the second terminal based on the operation state of the first terminal.

Abstract: A processor has: a power table including a plurality of power control registers each rewritably storing power control information; a condition determiner for rewritably storing a plurality of operating conditions (e.g., a comparison address to be compared with the program counter) and determining which one of the plurality of operating conditions is satisfied by a current operation of the processor so as to supply an index signal to select one of the plurality of power control registers based on the determination; and a voltage/clock controller for controlling the power consumption in a control object circuit block according to the power control information in one of the power control registers that is selected by the index signal.

Abstract: Embodiments of a system for regulating an efficiency of a power supply in a computer system are described. During operation, the system measures an output load of the power supply using one or more telemetry monitors in the computer system. Then, the system determines if an efficiency of the power supply corresponding to the measured output load is within a predetermined range that includes an optimal efficiency of the power supply. If the efficiency is outside of the predetermined range, the system performs remedial action so that the power supply operates at an adjusted efficiency that falls within the predetermined range.

Abstract: A system and method is provided to measure the power consumption of circuits whereby, in one aspect, a processor's temperature is maintained so that its power consumption is measured at the point the processor throttles.

Abstract: A processor may comprise one or more cores, where each respective core may comprise one or more state registers, and non-volatile memory configured to store microcode instructions executed by the respective processor core. The processor may further comprise a power management controller (PMC) interfacing with each respective core, and a state monitor (SM) interfacing with the PMC. The PMC may be configured to communicate with each respective core, such that microcode executed by the respective processor core may recognize when a request is made to transition the respective core to a low-power state. The microcode may communicate the request to the PMC, which may in turn determine if the request is for the respective core to transition to a zero-power state. If it is, the PMC may communicate with the SM to determine whether to transition the respective processor core to the zero-power state, and initiate transition to the zero-power state if a determination to transition to the zero-power state is made.

Abstract: A control apparatus connected to the plurality of image processing apparatuses by way of a network judges whether to apply current to a data processing unit held by the image processing apparatus based on a predetermined current application judging rule and transmits a result of judgment to the image processing apparatus. Each image processing apparatus, in the case of receiving the result of judgment of whether to apply current to the data processing unit through a NIC from the control apparatus, controls a current application state of the data processing unit based on the result of judgment. The data processing unit is divided in a plurality of functional blocks, and the current application to the data processing unit is controlled, functional block by functional block.

Abstract: A method for changing power states of a computer sends a shutdown event to all running applications before the computer goes to sleep to prevent data loss in a sleep state of the computer. Furthermore, the method stores a system memory image into a flash memory before the computer goes to the sleep state. Moreover, the method restores the system memory image from the flash memory to the system memory when the computer exit the sleep state to come back the work state.

Abstract: A universal serial bus power control circuit including at least one first switch which selectively couples a power source node to an external power node, a comparator which detects when the external power node is charged, a feedback node for enabling voltage regulation, a charge circuit and a controller. The charge circuit charges the external power node from the power source node and selectively couples the feedback node to at least one of the power source node and the external power node. The controller opens the first switch when the external power node is not charged, controls the charge circuit to charge the external power node while coupling the feedback node to the power source node, and closes the first switch and couples the feedback node to the external power node in a host mode when the external power node is charged.

Abstract: A remote connection system capable of generating a wake-up command and method thereof include a remote connector with a power supply input receiver capable of being connected to a power source and further capable of receiving a power supply for the purpose of powering the remote connector. The remote connector further includes a plurality of input ports allowing the coupling of a connector thereto and providing for the transmission of information thereacross. The remote connector further includes a wireless receiver capable of wirelessly receiving a wireless command and a transmitter capable of generating the wake-up command in response to the wireless command. The remote connector further includes a remote device capable of receiving a user input command, generating the wireless command and thereupon wirelessly transmitting the command to the wireless receiver of the remote connector.

Abstract: A semiconductor integrated circuit includes a plurality of internal blocks, a supply unit, and a control unit. The supply unit is configured to supply a clock signal to each of the plurality of internal blocks. The control unit is configured to detect power consumption in the semiconductor integrated circuit and to control the supply unit to start supplying the clock signal to each of the internal blocks one by one if the detected power consumption has stabilized.

Abstract: A system including plural storage devices provides a technique for controlling storage devices in which files are located by a file system, and turning on or off the storage devices based on prediction of the start or end of access to the files. A program that manages power to the storage devices and data access to the storage devices via the files includes means or functions for allocating a storage device as an area in which a file is located, for selecting a storage device in which a file is located, for predicting that access to a file is started for commanding turning on power to a storage device based on the prediction that access to a file is started, for predicting that access to a file terminates, and for commanding turning off power to a storage device based on the prediction that access to a file terminates.

Abstract: Disclosed is a method, apparatus and computer program product for reducing memory power consumption in a server system. The server system includes a memory controller and a plurality of Dual Inline Memory Modules (DIMMs). The method for reducing the memory power consumption includes determining a status of a channel of a plurality of channels of the memory controller. The plurality of channels is associated with the plurality of DIMMs of the server system. The status of the channel represents a presence of at least one scheduled transaction in the channel. The method further includes monitoring the status of the channel by checking whether the status of the channel is in an idle mode for a period of at least equal to a first threshold time. Thereafter, the method includes driving the channel into a power down state based on the monitoring of the status of the channel.

Abstract: A memory power controller comprises a clock generation circuitry for generating a first clock signal and a second clock signal responsive to a source clock and a determination that the source clock has a period greater than a predetermined value. The first clock is generated responsive to a determination that the source clock has a period greater than the predetermined value and the second clock is generated responsive to the determination that the source clock has a period less than the predetermined value. Memory time-out circuitry generates a memory enable/disable signal to control operation of an associated memory responsive to the clock signal and the determination that the source clock has a period greater than the predetermined value. The memory time-out circuitry further synchronizes the memory enable/disable signal with the source clock.

Abstract: To reduce the electric power consumption in a computer system having at least one server and at least one data processing apparatus, the data processing apparatus includes an electric power consumption state control module by which electric power consumption of the data processing apparatus can be changed, obtains a use relationship between each server and each processing apparatus included in the computer system, monitors a change in a state of the server, searches for a related data processing apparatus in the use relationship with the server, obtains a state of at least one related server in the use relationship with the related data processing apparatus, determines whether an electric power consumption state of the related data processing apparatus is to be changed or not based on the state of the related server, and changes the electric power consumption state of the related data processing apparatus.

Abstract: A system and method for power management of storage enclosures are disclosed. A system may include a storage enclosure and a host communicatively coupled to the storage enclosure. The storage enclosure may include at least one storage resource and a management module. The host may be configured to: (a) communicate data to the at least one storage resource via a particular transmission protocol; (b) communicate a power down command via the particular transmission protocol to the storage enclosure, the power down command operable to transition the storage enclosure from a high-power state to a low-power state; and (c) communicate a power up command via the particular transmission protocol to the storage enclosure, the power up command operable to transition the storage enclosure from the low-power state to the high-power state.

Abstract: A method and apparatus are provided for reducing the energy consumption of an electronic terminal. The method implements a step of modifying the timeout-before-standby duration for said terminal after an action performed by and/or on said terminal at a current instant, depending on the membership of the current instant in a given temporal category, from among at least two predefined temporal categories.