Clock gating approach to accommodate infrequent additional processing latencies
A processor system has a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal when the lengthy operation is activated. The clock control circuit receives the clock signal and outputs a gated clock signal only when the first device is not producing the control signal. The processor unit runs off of the gated clock signal. The first device may be a memory, and the lengthy operation may be correction of a soft error in memory. According to a second aspect, the first device requires a longer clock cycle rather than more clock cycles. The clock can be gated to effectively double the period when the lengthy operation is activated.
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The clock system shown in
Soft errors in memory are fairly rare. However, when they occur, they must be corrected, and an extra clock cycle is required to do this. The processor expects the memory to return the information in a single clock cycle. If the memory simply delays, problems will result in the processor pipeline, which is connected to memory interfaces.
One way to handle correction of soft errors in memory is to add wait states to the system. Wait states require additional logic and flip-flops to handle a hand shaking mechanism. The additional logic increases the size of the chip and affects speed. Adding wait states could also require changes to the architecture of the CPU or other blocks of the system.
SUMMARY OF THE INVENTIONThe present inventor proposes a processor system having a first device, a clock control circuit and a processor. The first device receives a clock signal, runs a plurality of operations including a lengthy operation requiring more than a single clock cycle to complete, and produces a control signal when the lengthy operation is run. The clock control circuit receives the clock signal and outputs a gated clock signal only when the first device is not producing the control signal. The processor unit runs off of the gated clock signal.
The first device may be a memory, and the lengthy operation may be correction of a soft error in memory.
The control signal may be high when the lengthy operation is not activated and low when the lengthy operation is activated. The clock control circuit may include an AND gate.
The lengthy operation may require one to three extra clock cycles.
According to a second aspect of the invention, a processor system has an input, a first device, a clock control circuit and a processor unit. The input receives a first clock signal having a first period. The first device runs a plurality of operations including a lengthy operation requiring a clock cycle having a second period, longer than the first period, to complete. The first device produces a control signal when the lengthy operation is activated. The clock control circuit receives the first clock signal and outputs a gated clock signal only when the first device is not producing the control signal. Both the first device and the processor unit run off of the gated clock signal. The first device may be an interrupt control unit, which receives a plurality of interrupt signals, such that the lengthy operation occurs when one of the interrupt signals is received at the interrupt control unit. The second period may be≦twice the first period.
These and other objects and advantages of the present invention will become more apparent and more readily appreciated from the following description of the preferred embodiments, taken in conjunction with the accompanying drawings of which:
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout.
The block that requires one or more extra clock cycles produces an output indicating when the extra clock cycles are required. In
The clock gating scheme shown in
A clock gating scheme similar to that shown in
In
It is possible that one or more of the interrupt signals will take significantly more time to process than the other interrupt signals. In
The interrupt signal Int2 is used to control the clock in the same manner as the Not Error signal did in
Comparing the schemes shown in
Potential advantages associated with the clock gating scheme include that it is simple to implement. It may require less additional logic than required by other approaches. It may be possible to implement the clock gating scheme without changing the architecture of the rest of the system. The clock gating scheme according to the second aspect eliminates a critical path so that it does not affect the performance of the system. The performance is affected only when the lengthy task is activated, which may be rare.
The invention has been described in detail with particular reference to preferred embodiments thereof and examples, but it will be understood that variations and modifications can be effected within the spirit and scope of the invention.
Claims
1. A control system, comprising:
- a first device configured to receive a first clock signal having a first clock cycle, and run an operation that requires more than the first clock cycle to complete, and to produce a control signal as long as the operation is activated; and
- a control circuit configured to extend a first duration of the first clock cycle to a time sufficient for the first device to complete the operation whenever the control signal is asserted by the first device.
2. The control system of claim 1, wherein the control circuit extends the duration of the first clock cycle by inhibiting the first clock signal for the time sufficient to complete the operation.
3. The control system of claim 1, wherein the time sufficient to complete the operation is equal to or greater than two of the first clock cycles.
4. The control system of claim 1, wherein the first device receives requests to perform operations, wherein one or more of the requests for one or more of the operations that cannot be completed by the first device within the first clock cycles are provided to the control circuit via one or more corresponding paths, and wherein every time that the one or more of the requests is received on the one or more corresponding paths, the control circuit increases the duration of the first clock cycle from the first durations to the time sufficient to complete the operation which is equal to or greater than two of the first cycles.
5. The control system of claim 1, further comprising a second device configured to receive the first clock signal.
6. The control system of claim 5, wherein the second device is configured to receive requests for the first device to perform operations, and wherein if two or more of the requests are received at the same time, the second device sends a one of the two or more requests which has a highest priority to the first device.
7. The control system of claim 1, wherein the first device is a processor and the operation is an interrupt request.
8. A control system, comprising:
- a first device configured to receive a first clock signal having a first clock cycle and to provide an output of the first device which indicates an operation is not complete when the operation cannot be completed by the first device within the first clock cycle; and
- a second device configured to receive the first clock signal when the output of the first device is not provided and to receive a second clock signal which has a second clock cycle with a duration sufficient for the first device to complete the operation when the output is provided.
9. The control system of claim 8, further comprising a control circuit configured to generate the second clock signal from the first clock signal by inhibiting the first clock signal for at least the time to complete the operation.
10. The control system of claim 8, wherein the first device is a processor.
11. The control system of claim 8, wherein the operation is a processing of an interrupt request.
12. The control system of claim 8, further comprising a third device configured to receive the first clock signal when the output of the first device is not provided and to receive the second clock signal when the output of the first device is provided.
13. A control system, comprising:
- a processor;
- a control unit which receives requests at corresponding inputs to perform operations and transfers the requests to the processor, wherein if two or more of the requests are received at the same time, the control unit transfers one of the two or more requests which has a highest priority to the processor; and
- a clock circuit configured to provide a clock signal to the processor, wherein the clock circuit increases a period of the clock signal when a predetermined one or more of the requests are received by the control unit.
14. The control system of claim 13, wherein the clock circuit increases the period of the clock signal by inhibiting the clock signal whenever the predetermined one or more of the requests are present at the corresponding inputs of the control unit.
15. The control system of claim 13, wherein the clock circuit includes a trigger circuit that increases the period of the clock signal by asserting an output that inhibits the clock signal when the predetermined one or more of the requests are received by the control unit.
16. The control system of claim 15, further comprising a logic circuit that is
- configured to receive the clock signal and the output of the trigger circuit, wherein the logic circuit inhibits the clock signal from being provided to the processor when the trigger circuit asserts the output.
17. A method of providing a clock, comprising:
- providing a first clock signal having a first clock cycle to a first device;
- running an operation that requires more than the first clock cycle to complete;
- producing a control signal as long as the operation is activated;
- increasing a period of the first clock cycle to a time sufficient to complete the operation whenever the control signal is asserted by the first device.
18. The method of claim 17, wherein increasing the period of the first clock signal comprises inhibiting the first clock signal for the time sufficient to complete the operation.
19. The method of claim 17, wherein providing the first clock signal comprises providing the first clock signal to a second device.
20. The method of claim 17, comprising:
- receiving requests to perform operations, wherein one or more of the operations corresponding to one or more of the requests cannot be completed by the first device within the first clock cycle; and
- increasing the period of the first clock signal every time the one or more of the requests are received.
21. The method of claim 20, wherein receiving requests to perform operations comprises, if two or more of the requests are received at the same time, sending a one of the two or more of the requests which has a highest priority to the first device.
22. A method of providing a clock to a first device and a second device, comprising:
- providing a first clock signal having a first clock cycle to the first device and to the second device;
- asserting an output of the first device as long as the first device has not completed an operation within the first clock cycle; and
- providing a second clock signal to the second device as long as the output of the first device is asserted, wherein the second clock signal has a period that is equal to or greater than the time to complete the operation.
23. The method of claim 22, wherein providing the second clock signal comprises generating the second clock signal from the first clock signal by inhibiting the first clock signal for at least the time to complete the operation.
24. A control system, comprising:
- a first processing means configured to receive a first clock signal and provide an output which indicates a time to complete an operation when the operation cannot be completed by the first processing means within a period of the first clock signal;
- a second logic means configured to receive the first clock signal when the output of the first processing means is not provided and to receive a second clock signal when the output of the first processing means is provided; and
- a control means configured to generate the second clock signal from the first clock signal by inhibiting the first clock signal for the period that is equal to or greater than the time to complete the operation.
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Type: Grant
Filed: Feb 21, 2003
Date of Patent: Jun 26, 2007
Patent Publication Number: 20040168134
Assignee: Infineon Technologies AG (Munich)
Inventor: Nutan Prasad (San Jose, CA)
Primary Examiner: Phallaka Kik
Attorney: Staas & Halsey LLP
Application Number: 10/370,053
International Classification: G06F 17/50 (20060101); G06F 1/04 (20060101); G06F 9/00 (20060101); G06F 15/16 (20060101); H03L 7/00 (20060101); H03K 17/28 (20060101); H03K 19/00 (20060101);